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d9b94f28 | 1 | /* |
f2cff6b1 | 2 | * Copyright 2004, 2007 Freescale Semiconductor. |
d9b94f28 JL |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
f2cff6b1 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
d9b94f28 JL |
15 | * GNU General Public License for more details. |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8548cds board configuration file | |
25 | * | |
26 | * Please refer to doc/README.mpc85xxcds for more info. | |
27 | * | |
28 | */ | |
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
32 | /* High Level Configuration Options */ | |
33 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
34 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
35 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
36 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ | |
37 | #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ | |
38 | ||
f2cff6b1 ES |
39 | #define CONFIG_PCI /* enable any pci type devices */ |
40 | #define CONFIG_PCI1 /* PCI controller 1 */ | |
41 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
42 | #undef CONFIG_RIO | |
43 | #undef CONFIG_PCI2 | |
44 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
8ff3de61 | 45 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
f2cff6b1 ES |
46 | |
47 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
d9b94f28 JL |
48 | #define CONFIG_ENV_OVERWRITE |
49 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
50 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ | |
39b18c4f | 51 | #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
d9b94f28 JL |
52 | |
53 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ | |
54 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
55 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
f2cff6b1 | 56 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
d9b94f28 | 57 | |
2cfaa1aa | 58 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
d9b94f28 | 59 | |
25eedb2c JL |
60 | #define CONFIG_FSL_VIA |
61 | #define CONFIG_FSL_CDS_EEPROM | |
62 | ||
d9b94f28 JL |
63 | /* |
64 | * When initializing flash, if we cannot find the manufacturer ID, | |
65 | * assume this is the AMD flash associated with the CDS board. | |
66 | * This allows booting from a promjet. | |
67 | */ | |
68 | #define CONFIG_ASSUME_AMD_FLASH | |
69 | ||
70 | #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ | |
71 | ||
72 | #ifndef __ASSEMBLY__ | |
73 | extern unsigned long get_clock_freq(void); | |
74 | #endif | |
75 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
76 | ||
77 | /* | |
78 | * These can be toggled for performance analysis, otherwise use default. | |
79 | */ | |
f2cff6b1 ES |
80 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
81 | #define CONFIG_BTB /* toggle branch predition */ | |
82 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
83 | #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ | |
d9b94f28 JL |
84 | |
85 | /* | |
86 | * Only possible on E500 Version 2 or newer cores. | |
87 | */ | |
88 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
89 | ||
d9b94f28 JL |
90 | #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ |
91 | #define CFG_MEMTEST_END 0x00400000 | |
92 | ||
93 | /* | |
94 | * Base addresses -- Note these are effective addresses where the | |
95 | * actual resources get mapped (not physical addresses) | |
96 | */ | |
f2cff6b1 | 97 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
d9b94f28 | 98 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
f69766e4 | 99 | #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ |
d9b94f28 JL |
100 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
101 | ||
f2cff6b1 ES |
102 | #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) |
103 | #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) | |
104 | #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) | |
105 | ||
d9b94f28 JL |
106 | /* |
107 | * DDR Setup | |
108 | */ | |
109 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
110 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
111 | ||
112 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
113 | ||
114 | /* | |
115 | * Make sure required options are set | |
116 | */ | |
117 | #ifndef CONFIG_SPD_EEPROM | |
118 | #error ("CONFIG_SPD_EEPROM is required") | |
119 | #endif | |
120 | ||
121 | #undef CONFIG_CLOCKS_IN_MHZ | |
122 | ||
d9b94f28 JL |
123 | /* |
124 | * Local Bus Definitions | |
125 | */ | |
126 | ||
127 | /* | |
128 | * FLASH on the Local Bus | |
129 | * Two banks, 8M each, using the CFI driver. | |
130 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
131 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
132 | * | |
133 | * BR0, BR1: | |
134 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
135 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
136 | * Port Size = 16 bits = BRx[19:20] = 10 | |
137 | * Use GPCM = BRx[24:26] = 000 | |
138 | * Valid = BRx[31] = 1 | |
139 | * | |
f2cff6b1 ES |
140 | * 0 4 8 12 16 20 24 28 |
141 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
142 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
d9b94f28 JL |
143 | * |
144 | * OR0, OR1: | |
145 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
146 | * Reserved ORx[17:18] = 11, confusion here? | |
147 | * CSNT = ORx[20] = 1 | |
148 | * ACS = half cycle delay = ORx[21:22] = 11 | |
149 | * SCY = 6 = ORx[24:27] = 0110 | |
150 | * TRLX = use relaxed timing = ORx[29] = 1 | |
151 | * EAD = use external address latch delay = OR[31] = 1 | |
152 | * | |
f2cff6b1 ES |
153 | * 0 4 8 12 16 20 24 28 |
154 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
d9b94f28 JL |
155 | */ |
156 | ||
f2cff6b1 ES |
157 | #define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */ |
158 | #define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ | |
d9b94f28 JL |
159 | |
160 | #define CFG_BR0_PRELIM 0xff801001 | |
161 | #define CFG_BR1_PRELIM 0xff001001 | |
162 | ||
163 | #define CFG_OR0_PRELIM 0xff806e65 | |
164 | #define CFG_OR1_PRELIM 0xff806e65 | |
165 | ||
166 | #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} | |
167 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
168 | #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ | |
169 | #undef CFG_FLASH_CHECKSUM | |
170 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
171 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
172 | ||
f2cff6b1 | 173 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
d9b94f28 JL |
174 | |
175 | #define CFG_FLASH_CFI_DRIVER | |
176 | #define CFG_FLASH_CFI | |
177 | #define CFG_FLASH_EMPTY_INFO | |
178 | ||
179 | ||
180 | /* | |
181 | * SDRAM on the Local Bus | |
182 | */ | |
f2cff6b1 ES |
183 | #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ |
184 | #define CFG_LBC_CACHE_SIZE 64 | |
185 | #define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ | |
186 | #define CFG_LBC_NONCACHE_SIZE 64 | |
187 | ||
188 | #define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */ | |
d9b94f28 JL |
189 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
190 | ||
191 | /* | |
192 | * Base Register 2 and Option Register 2 configure SDRAM. | |
193 | * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. | |
194 | * | |
195 | * For BR2, need: | |
196 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
197 | * port-size = 32-bits = BR2[19:20] = 11 | |
198 | * no parity checking = BR2[21:22] = 00 | |
199 | * SDRAM for MSEL = BR2[24:26] = 011 | |
200 | * Valid = BR[31] = 1 | |
201 | * | |
f2cff6b1 | 202 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
203 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
204 | * | |
205 | * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into | |
206 | * FIXME: the top 17 bits of BR2. | |
207 | */ | |
208 | ||
f2cff6b1 | 209 | #define CFG_BR2_PRELIM 0xf0001861 |
d9b94f28 JL |
210 | |
211 | /* | |
212 | * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. | |
213 | * | |
214 | * For OR2, need: | |
215 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
216 | * XAM, OR2[17:18] = 11 | |
217 | * 9 columns OR2[19-21] = 010 | |
f2cff6b1 | 218 | * 13 rows OR2[23-25] = 100 |
d9b94f28 JL |
219 | * EAD set for extra time OR[31] = 1 |
220 | * | |
f2cff6b1 | 221 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
222 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
223 | */ | |
224 | ||
225 | #define CFG_OR2_PRELIM 0xfc006901 | |
226 | ||
f2cff6b1 ES |
227 | #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
228 | #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ | |
229 | #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
230 | #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
d9b94f28 JL |
231 | |
232 | /* | |
233 | * LSDMR masks | |
234 | */ | |
235 | #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) | |
236 | #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) | |
237 | #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) | |
238 | #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) | |
239 | #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) | |
240 | #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) | |
241 | #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) | |
242 | #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) | |
243 | #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) | |
244 | #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) | |
245 | ||
246 | #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) | |
247 | #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) | |
248 | #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) | |
249 | #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) | |
250 | #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) | |
251 | #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) | |
252 | #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) | |
253 | #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) | |
254 | ||
255 | /* | |
256 | * Common settings for all Local Bus SDRAM commands. | |
257 | * At run time, either BSMA1516 (for CPU 1.1) | |
f2cff6b1 | 258 | * or BSMA1617 (for CPU 1.0) (old) |
d9b94f28 JL |
259 | * is OR'ed in too. |
260 | */ | |
261 | #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ | |
262 | | CFG_LBC_LSDMR_PRETOACT7 \ | |
263 | | CFG_LBC_LSDMR_ACTTORW7 \ | |
264 | | CFG_LBC_LSDMR_BL8 \ | |
265 | | CFG_LBC_LSDMR_WRC4 \ | |
266 | | CFG_LBC_LSDMR_CL3 \ | |
267 | | CFG_LBC_LSDMR_RFEN \ | |
268 | ) | |
269 | ||
270 | /* | |
271 | * The CADMUS registers are connected to CS3 on CDS. | |
272 | * The new memory map places CADMUS at 0xf8000000. | |
273 | * | |
274 | * For BR3, need: | |
275 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
276 | * port-size = 8-bits = BR[19:20] = 01 | |
277 | * no parity checking = BR[21:22] = 00 | |
f2cff6b1 ES |
278 | * GPMC for MSEL = BR[24:26] = 000 |
279 | * Valid = BR[31] = 1 | |
d9b94f28 | 280 | * |
f2cff6b1 | 281 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
282 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
283 | * | |
284 | * For OR3, need: | |
f2cff6b1 | 285 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
d9b94f28 | 286 | * disable buffer ctrl OR[19] = 0 |
f2cff6b1 ES |
287 | * CSNT OR[20] = 1 |
288 | * ACS OR[21:22] = 11 | |
289 | * XACS OR[23] = 1 | |
d9b94f28 | 290 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
f2cff6b1 ES |
291 | * SETA OR[28] = 0 |
292 | * TRLX OR[29] = 1 | |
293 | * EHTR OR[30] = 1 | |
294 | * EAD extra time OR[31] = 1 | |
d9b94f28 | 295 | * |
f2cff6b1 | 296 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
297 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
298 | */ | |
299 | ||
25eedb2c JL |
300 | #define CONFIG_FSL_CADMUS |
301 | ||
d9b94f28 | 302 | #define CADMUS_BASE_ADDR 0xf8000000 |
f2cff6b1 ES |
303 | #define CFG_BR3_PRELIM 0xf8000801 |
304 | #define CFG_OR3_PRELIM 0xfff00ff7 | |
d9b94f28 JL |
305 | |
306 | #define CONFIG_L1_INIT_RAM | |
f2cff6b1 | 307 | #define CFG_INIT_RAM_LOCK 1 |
d9b94f28 | 308 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
f2cff6b1 ES |
309 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
310 | ||
311 | #define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ | |
d9b94f28 | 312 | |
f2cff6b1 | 313 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
d9b94f28 JL |
314 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
315 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
316 | ||
f2cff6b1 ES |
317 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
318 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
d9b94f28 JL |
319 | |
320 | /* Serial Port */ | |
f2cff6b1 | 321 | #define CONFIG_CONS_INDEX 2 |
d9b94f28 JL |
322 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
323 | #define CFG_NS16550 | |
324 | #define CFG_NS16550_SERIAL | |
f2cff6b1 | 325 | #define CFG_NS16550_REG_SIZE 1 |
d9b94f28 JL |
326 | #define CFG_NS16550_CLK get_bus_freq(0) |
327 | ||
f2cff6b1 | 328 | #define CFG_BAUDRATE_TABLE \ |
d9b94f28 JL |
329 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
330 | ||
f2cff6b1 ES |
331 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
332 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
d9b94f28 JL |
333 | |
334 | /* Use the HUSH parser */ | |
335 | #define CFG_HUSH_PARSER | |
f2cff6b1 | 336 | #ifdef CFG_HUSH_PARSER |
d9b94f28 JL |
337 | #define CFG_PROMPT_HUSH_PS2 "> " |
338 | #endif | |
339 | ||
40d5fa35 | 340 | /* pass open firmware flat tree */ |
b90d2549 KG |
341 | #define CONFIG_OF_LIBFDT 1 |
342 | #define CONFIG_OF_BOARD_SETUP 1 | |
343 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
40d5fa35 | 344 | |
20476726 JL |
345 | /* |
346 | * I2C | |
347 | */ | |
348 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
349 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
f2cff6b1 | 350 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
d9b94f28 JL |
351 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
352 | #define CFG_I2C_EEPROM_ADDR 0x57 | |
353 | #define CFG_I2C_SLAVE 0x7F | |
f2cff6b1 | 354 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
20476726 | 355 | #define CFG_I2C_OFFSET 0x3000 |
d9b94f28 JL |
356 | |
357 | /* | |
358 | * General PCI | |
362dd830 | 359 | * Memory space is mapped 1-1, but I/O space must start from 0. |
d9b94f28 | 360 | */ |
f2cff6b1 ES |
361 | #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
362 | ||
d9b94f28 JL |
363 | #define CFG_PCI1_MEM_BASE 0x80000000 |
364 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
f2cff6b1 | 365 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
cbfc7ce7 MM |
366 | #define CFG_PCI1_IO_BASE 0x00000000 |
367 | #define CFG_PCI1_IO_PHYS 0xe2000000 | |
f2cff6b1 | 368 | #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ |
d9b94f28 | 369 | |
f2cff6b1 ES |
370 | #ifdef CONFIG_PCI2 |
371 | #define CFG_PCI2_MEM_BASE 0xa0000000 | |
d9b94f28 | 372 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
f2cff6b1 | 373 | #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
ffa621a0 | 374 | #define CFG_PCI2_IO_BASE 0x00000000 |
41fb7e0f | 375 | #define CFG_PCI2_IO_PHYS 0xe2800000 |
f2cff6b1 ES |
376 | #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ |
377 | #endif | |
41fb7e0f | 378 | |
f2cff6b1 ES |
379 | #ifdef CONFIG_PCIE1 |
380 | #define CFG_PCIE1_MEM_BASE 0xa0000000 | |
381 | #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE | |
382 | #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
383 | #define CFG_PCIE1_IO_BASE 0x00000000 | |
384 | #define CFG_PCIE1_IO_PHYS 0xe3000000 | |
385 | #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ | |
386 | #endif | |
d9b94f28 | 387 | |
f2cff6b1 | 388 | #ifdef CONFIG_RIO |
41fb7e0f ZR |
389 | /* |
390 | * RapidIO MMU | |
391 | */ | |
392 | #define CFG_RIO_MEM_BASE 0xC0000000 | |
393 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ | |
f2cff6b1 | 394 | #endif |
d9b94f28 | 395 | |
7f3f2bd2 RV |
396 | #ifdef CONFIG_LEGACY |
397 | #define BRIDGE_ID 17 | |
398 | #define VIA_ID 2 | |
399 | #else | |
400 | #define BRIDGE_ID 28 | |
401 | #define VIA_ID 4 | |
402 | #endif | |
403 | ||
d9b94f28 JL |
404 | #if defined(CONFIG_PCI) |
405 | ||
406 | #define CONFIG_NET_MULTI | |
f2cff6b1 | 407 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d9b94f28 JL |
408 | |
409 | #undef CONFIG_EEPRO100 | |
410 | #undef CONFIG_TULIP | |
411 | ||
d9b94f28 | 412 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
f2cff6b1 ES |
413 | |
414 | /* PCI view of System Memory */ | |
415 | #define CFG_PCI_MEMORY_BUS 0x00000000 | |
416 | #define CFG_PCI_MEMORY_PHYS 0x00000000 | |
417 | #define CFG_PCI_MEMORY_SIZE 0x80000000 | |
d9b94f28 JL |
418 | |
419 | #endif /* CONFIG_PCI */ | |
420 | ||
421 | ||
422 | #if defined(CONFIG_TSEC_ENET) | |
423 | ||
424 | #ifndef CONFIG_NET_MULTI | |
f2cff6b1 | 425 | #define CONFIG_NET_MULTI 1 |
d9b94f28 JL |
426 | #endif |
427 | ||
428 | #define CONFIG_MII 1 /* MII PHY management */ | |
255a3577 KP |
429 | #define CONFIG_TSEC1 1 |
430 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
431 | #define CONFIG_TSEC2 1 | |
432 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
433 | #define CONFIG_TSEC3 1 | |
434 | #define CONFIG_TSEC3_NAME "eTSEC2" | |
f2cff6b1 | 435 | #define CONFIG_TSEC4 |
255a3577 | 436 | #define CONFIG_TSEC4_NAME "eTSEC3" |
d9b94f28 JL |
437 | #undef CONFIG_MPC85XX_FEC |
438 | ||
439 | #define TSEC1_PHY_ADDR 0 | |
440 | #define TSEC2_PHY_ADDR 1 | |
441 | #define TSEC3_PHY_ADDR 2 | |
442 | #define TSEC4_PHY_ADDR 3 | |
d9b94f28 JL |
443 | |
444 | #define TSEC1_PHYIDX 0 | |
445 | #define TSEC2_PHYIDX 0 | |
446 | #define TSEC3_PHYIDX 0 | |
447 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
448 | #define TSEC1_FLAGS TSEC_GIGABIT |
449 | #define TSEC2_FLAGS TSEC_GIGABIT | |
450 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
451 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
d9b94f28 JL |
452 | |
453 | /* Options are: eTSEC[0-3] */ | |
454 | #define CONFIG_ETHPRIME "eTSEC0" | |
f2cff6b1 | 455 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
d9b94f28 JL |
456 | #endif /* CONFIG_TSEC_ENET */ |
457 | ||
458 | /* | |
459 | * Environment | |
460 | */ | |
461 | #define CFG_ENV_IS_IN_FLASH 1 | |
462 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
463 | #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ | |
464 | #define CFG_ENV_SIZE 0x2000 | |
465 | ||
466 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
467 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
468 | ||
659e2f67 JL |
469 | /* |
470 | * BOOTP options | |
471 | */ | |
472 | #define CONFIG_BOOTP_BOOTFILESIZE | |
473 | #define CONFIG_BOOTP_BOOTPATH | |
474 | #define CONFIG_BOOTP_GATEWAY | |
475 | #define CONFIG_BOOTP_HOSTNAME | |
476 | ||
477 | ||
2835e518 JL |
478 | /* |
479 | * Command line configuration. | |
480 | */ | |
481 | #include <config_cmd_default.h> | |
482 | ||
483 | #define CONFIG_CMD_PING | |
484 | #define CONFIG_CMD_I2C | |
485 | #define CONFIG_CMD_MII | |
82ac8c97 | 486 | #define CONFIG_CMD_ELF |
2835e518 | 487 | |
d9b94f28 | 488 | #if defined(CONFIG_PCI) |
2835e518 | 489 | #define CONFIG_CMD_PCI |
d9b94f28 | 490 | #endif |
2835e518 | 491 | |
d9b94f28 JL |
492 | |
493 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
494 | ||
495 | /* | |
496 | * Miscellaneous configurable options | |
497 | */ | |
498 | #define CFG_LONGHELP /* undef to save memory */ | |
22abb2d2 | 499 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
d9b94f28 JL |
500 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
501 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
2835e518 | 502 | #if defined(CONFIG_CMD_KGDB) |
d9b94f28 JL |
503 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
504 | #else | |
505 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
506 | #endif | |
507 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
508 | #define CFG_MAXARGS 16 /* max number of command args */ | |
509 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
510 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
511 | ||
512 | /* | |
513 | * For booting Linux, the board info and command line data | |
514 | * have to be in the first 8 MB of memory, since this is | |
515 | * the maximum mapped by the Linux kernel during initialization. | |
516 | */ | |
f2cff6b1 | 517 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
d9b94f28 | 518 | |
d9b94f28 JL |
519 | /* |
520 | * Internal Definitions | |
521 | * | |
522 | * Boot Flags | |
523 | */ | |
524 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
525 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
526 | ||
2835e518 | 527 | #if defined(CONFIG_CMD_KGDB) |
d9b94f28 JL |
528 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
529 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
530 | #endif | |
531 | ||
532 | /* | |
533 | * Environment Configuration | |
534 | */ | |
535 | ||
536 | /* The mac addresses for all ethernet interface */ | |
537 | #if defined(CONFIG_TSEC_ENET) | |
10327dc5 | 538 | #define CONFIG_HAS_ETH0 |
f2cff6b1 | 539 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
d9b94f28 | 540 | #define CONFIG_HAS_ETH1 |
f2cff6b1 | 541 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
d9b94f28 | 542 | #define CONFIG_HAS_ETH2 |
f2cff6b1 | 543 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
09f3e09e | 544 | #define CONFIG_HAS_ETH3 |
f2cff6b1 | 545 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD |
d9b94f28 JL |
546 | #endif |
547 | ||
f2cff6b1 | 548 | #define CONFIG_IPADDR 192.168.1.253 |
d9b94f28 | 549 | |
f2cff6b1 ES |
550 | #define CONFIG_HOSTNAME unknown |
551 | #define CONFIG_ROOTPATH /nfsroot | |
552 | #define CONFIG_BOOTFILE 8548cds/uImage.uboot | |
553 | #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ | |
d9b94f28 | 554 | |
f2cff6b1 | 555 | #define CONFIG_SERVERIP 192.168.1.1 |
d9b94f28 | 556 | #define CONFIG_GATEWAYIP 192.168.1.1 |
f2cff6b1 | 557 | #define CONFIG_NETMASK 255.255.255.0 |
d9b94f28 | 558 | |
f2cff6b1 | 559 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
d9b94f28 | 560 | |
f2cff6b1 ES |
561 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
562 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
d9b94f28 JL |
563 | |
564 | #define CONFIG_BAUDRATE 115200 | |
565 | ||
f2cff6b1 ES |
566 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
567 | "netdev=eth0\0" \ | |
568 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
569 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
570 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
571 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
572 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
573 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
574 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
575 | "consoledev=ttyS1\0" \ | |
576 | "ramdiskaddr=2000000\0" \ | |
6c543597 | 577 | "ramdiskfile=ramdisk.uboot\0" \ |
4bf4abb8 | 578 | "fdtaddr=c00000\0" \ |
22abb2d2 | 579 | "fdtfile=mpc8548cds.dtb\0" |
f2cff6b1 ES |
580 | |
581 | #define CONFIG_NFSBOOTCOMMAND \ | |
582 | "setenv bootargs root=/dev/nfs rw " \ | |
583 | "nfsroot=$serverip:$rootpath " \ | |
d9b94f28 | 584 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
f2cff6b1 ES |
585 | "console=$consoledev,$baudrate $othbootargs;" \ |
586 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
587 | "tftp $fdtaddr $fdtfile;" \ |
588 | "bootm $loadaddr - $fdtaddr" | |
8272dc2f | 589 | |
d9b94f28 JL |
590 | |
591 | #define CONFIG_RAMBOOTCOMMAND \ | |
f2cff6b1 ES |
592 | "setenv bootargs root=/dev/ram rw " \ |
593 | "console=$consoledev,$baudrate $othbootargs;" \ | |
594 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
595 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
596 | "tftp $fdtaddr $fdtfile;" \ |
597 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
f2cff6b1 ES |
598 | |
599 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
d9b94f28 JL |
600 | |
601 | #endif /* __CONFIG_H */ |