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d9b94f28 | 1 | /* |
8b47d7ec | 2 | * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. |
d9b94f28 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
d9b94f28 JL |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8548cds board configuration file | |
9 | * | |
10 | * Please refer to doc/README.mpc85xxcds for more info. | |
11 | * | |
12 | */ | |
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* High Level Configuration Options */ | |
17 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
18 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
d9b94f28 JL |
19 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ |
20 | #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ | |
21 | ||
2ae18241 WD |
22 | #ifndef CONFIG_SYS_TEXT_BASE |
23 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
24 | #endif | |
25 | ||
8b47d7ec KG |
26 | #define CONFIG_SYS_SRIO |
27 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
28 | ||
f2cff6b1 ES |
29 | #define CONFIG_PCI /* enable any pci type devices */ |
30 | #define CONFIG_PCI1 /* PCI controller 1 */ | |
b38eaec5 | 31 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
f2cff6b1 ES |
32 | #undef CONFIG_PCI2 |
33 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 34 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
8ff3de61 | 35 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 36 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
f2cff6b1 ES |
37 | |
38 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
d9b94f28 | 39 | #define CONFIG_ENV_OVERWRITE |
f2cff6b1 | 40 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
2cfaa1aa | 41 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
d9b94f28 | 42 | |
25eedb2c | 43 | #define CONFIG_FSL_VIA |
25eedb2c | 44 | |
d9b94f28 JL |
45 | #ifndef __ASSEMBLY__ |
46 | extern unsigned long get_clock_freq(void); | |
47 | #endif | |
48 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
49 | ||
50 | /* | |
51 | * These can be toggled for performance analysis, otherwise use default. | |
52 | */ | |
f2cff6b1 ES |
53 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
54 | #define CONFIG_BTB /* toggle branch predition */ | |
d9b94f28 JL |
55 | |
56 | /* | |
57 | * Only possible on E500 Version 2 or newer cores. | |
58 | */ | |
59 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
60 | ||
b76aef60 | 61 | #ifdef CONFIG_PHYS_64BIT |
62 | #define CONFIG_ADDR_MAP | |
63 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
64 | #endif | |
65 | ||
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
67 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
d9b94f28 | 68 | |
e46fedfe TT |
69 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
70 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
d9b94f28 | 71 | |
e31d2c1e | 72 | /* DDR Setup */ |
5614e71b | 73 | #define CONFIG_SYS_FSL_DDR2 |
e31d2c1e JL |
74 | #undef CONFIG_FSL_DDR_INTERACTIVE |
75 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
76 | #define CONFIG_DDR_SPD | |
e31d2c1e | 77 | |
867b06f4 | 78 | #define CONFIG_DDR_ECC |
9b0ad1b1 | 79 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
e31d2c1e JL |
80 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
81 | ||
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
83 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
d9b94f28 | 84 | |
e31d2c1e JL |
85 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
86 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
87 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
d9b94f28 | 88 | |
e31d2c1e JL |
89 | /* I2C addresses of SPD EEPROMs */ |
90 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
91 | ||
92 | /* Make sure required options are set */ | |
d9b94f28 JL |
93 | #ifndef CONFIG_SPD_EEPROM |
94 | #error ("CONFIG_SPD_EEPROM is required") | |
95 | #endif | |
96 | ||
97 | #undef CONFIG_CLOCKS_IN_MHZ | |
fff80975 | 98 | /* |
99 | * Physical Address Map | |
100 | * | |
101 | * 32bit: | |
102 | * 0x0000_0000 0x7fff_ffff DDR 2G cacheable | |
103 | * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable | |
104 | * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable | |
105 | * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable | |
106 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable | |
107 | * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable | |
108 | * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable | |
109 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable | |
110 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable | |
111 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
112 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable | |
113 | * | |
b76aef60 | 114 | * 36bit: |
115 | * 0x00000_0000 0x07fff_ffff DDR 2G cacheable | |
116 | * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable | |
117 | * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable | |
118 | * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable | |
119 | * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable | |
120 | * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable | |
121 | * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable | |
122 | * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable | |
123 | * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable | |
124 | * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
125 | * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable | |
126 | * | |
fff80975 | 127 | */ |
128 | ||
d9b94f28 JL |
129 | /* |
130 | * Local Bus Definitions | |
131 | */ | |
132 | ||
133 | /* | |
134 | * FLASH on the Local Bus | |
135 | * Two banks, 8M each, using the CFI driver. | |
136 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
137 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
138 | * | |
139 | * BR0, BR1: | |
140 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
141 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
142 | * Port Size = 16 bits = BRx[19:20] = 10 | |
143 | * Use GPCM = BRx[24:26] = 000 | |
144 | * Valid = BRx[31] = 1 | |
145 | * | |
f2cff6b1 ES |
146 | * 0 4 8 12 16 20 24 28 |
147 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
148 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
d9b94f28 JL |
149 | * |
150 | * OR0, OR1: | |
151 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
152 | * Reserved ORx[17:18] = 11, confusion here? | |
153 | * CSNT = ORx[20] = 1 | |
154 | * ACS = half cycle delay = ORx[21:22] = 11 | |
155 | * SCY = 6 = ORx[24:27] = 0110 | |
156 | * TRLX = use relaxed timing = ORx[29] = 1 | |
157 | * EAD = use external address latch delay = OR[31] = 1 | |
158 | * | |
f2cff6b1 ES |
159 | * 0 4 8 12 16 20 24 28 |
160 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
d9b94f28 JL |
161 | */ |
162 | ||
fff80975 | 163 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
b76aef60 | 164 | #ifdef CONFIG_PHYS_64BIT |
165 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull | |
166 | #else | |
fff80975 | 167 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
b76aef60 | 168 | #endif |
d9b94f28 | 169 | |
fff80975 | 170 | #define CONFIG_SYS_BR0_PRELIM \ |
7ee41107 | 171 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) |
fff80975 | 172 | #define CONFIG_SYS_BR1_PRELIM \ |
173 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
d9b94f28 | 174 | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
176 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
d9b94f28 | 177 | |
fff80975 | 178 | #define CONFIG_SYS_FLASH_BANKS_LIST \ |
179 | {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} | |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
181 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
182 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
183 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
184 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
d9b94f28 | 185 | |
14d0a02a | 186 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d9b94f28 | 187 | |
00b1883a | 188 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_FLASH_CFI |
190 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
d9b94f28 | 191 | |
867b06f4 | 192 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
d9b94f28 JL |
193 | |
194 | /* | |
195 | * SDRAM on the Local Bus | |
196 | */ | |
fff80975 | 197 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
b76aef60 | 198 | #ifdef CONFIG_PHYS_64BIT |
199 | #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull | |
200 | #else | |
fff80975 | 201 | #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE |
b76aef60 | 202 | #endif |
6d0f6bcf | 203 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
d9b94f28 JL |
204 | |
205 | /* | |
206 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 207 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
d9b94f28 JL |
208 | * |
209 | * For BR2, need: | |
210 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
211 | * port-size = 32-bits = BR2[19:20] = 11 | |
212 | * no parity checking = BR2[21:22] = 00 | |
213 | * SDRAM for MSEL = BR2[24:26] = 011 | |
214 | * Valid = BR[31] = 1 | |
215 | * | |
f2cff6b1 | 216 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
217 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
218 | * | |
6d0f6bcf | 219 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
d9b94f28 JL |
220 | * FIXME: the top 17 bits of BR2. |
221 | */ | |
222 | ||
fff80975 | 223 | #define CONFIG_SYS_BR2_PRELIM \ |
224 | (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ | |
225 | | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) | |
d9b94f28 JL |
226 | |
227 | /* | |
6d0f6bcf | 228 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
d9b94f28 JL |
229 | * |
230 | * For OR2, need: | |
231 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
232 | * XAM, OR2[17:18] = 11 | |
233 | * 9 columns OR2[19-21] = 010 | |
f2cff6b1 | 234 | * 13 rows OR2[23-25] = 100 |
d9b94f28 JL |
235 | * EAD set for extra time OR[31] = 1 |
236 | * | |
f2cff6b1 | 237 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
238 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
239 | */ | |
240 | ||
6d0f6bcf | 241 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
d9b94f28 | 242 | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
244 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
245 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
246 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
d9b94f28 | 247 | |
d9b94f28 JL |
248 | /* |
249 | * Common settings for all Local Bus SDRAM commands. | |
250 | * At run time, either BSMA1516 (for CPU 1.1) | |
f2cff6b1 | 251 | * or BSMA1617 (for CPU 1.0) (old) |
d9b94f28 JL |
252 | * is OR'ed in too. |
253 | */ | |
b0fe93ed KG |
254 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
255 | | LSDMR_PRETOACT7 \ | |
256 | | LSDMR_ACTTORW7 \ | |
257 | | LSDMR_BL8 \ | |
258 | | LSDMR_WRC4 \ | |
259 | | LSDMR_CL3 \ | |
260 | | LSDMR_RFEN \ | |
d9b94f28 JL |
261 | ) |
262 | ||
263 | /* | |
264 | * The CADMUS registers are connected to CS3 on CDS. | |
265 | * The new memory map places CADMUS at 0xf8000000. | |
266 | * | |
267 | * For BR3, need: | |
268 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
269 | * port-size = 8-bits = BR[19:20] = 01 | |
270 | * no parity checking = BR[21:22] = 00 | |
f2cff6b1 ES |
271 | * GPMC for MSEL = BR[24:26] = 000 |
272 | * Valid = BR[31] = 1 | |
d9b94f28 | 273 | * |
f2cff6b1 | 274 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
275 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
276 | * | |
277 | * For OR3, need: | |
f2cff6b1 | 278 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
d9b94f28 | 279 | * disable buffer ctrl OR[19] = 0 |
f2cff6b1 ES |
280 | * CSNT OR[20] = 1 |
281 | * ACS OR[21:22] = 11 | |
282 | * XACS OR[23] = 1 | |
d9b94f28 | 283 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
f2cff6b1 ES |
284 | * SETA OR[28] = 0 |
285 | * TRLX OR[29] = 1 | |
286 | * EHTR OR[30] = 1 | |
287 | * EAD extra time OR[31] = 1 | |
d9b94f28 | 288 | * |
f2cff6b1 | 289 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
290 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
291 | */ | |
292 | ||
25eedb2c JL |
293 | #define CONFIG_FSL_CADMUS |
294 | ||
d9b94f28 | 295 | #define CADMUS_BASE_ADDR 0xf8000000 |
b76aef60 | 296 | #ifdef CONFIG_PHYS_64BIT |
297 | #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull | |
298 | #else | |
fff80975 | 299 | #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR |
b76aef60 | 300 | #endif |
fff80975 | 301 | #define CONFIG_SYS_BR3_PRELIM \ |
302 | (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) | |
6d0f6bcf | 303 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 |
d9b94f28 | 304 | |
6d0f6bcf JCPV |
305 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
306 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 307 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
f2cff6b1 | 308 | |
25ddd1fb | 309 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 310 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
d9b94f28 | 311 | |
6d0f6bcf | 312 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
867b06f4 | 313 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
d9b94f28 JL |
314 | |
315 | /* Serial Port */ | |
f2cff6b1 | 316 | #define CONFIG_CONS_INDEX 2 |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_NS16550_SERIAL |
318 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
319 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
d9b94f28 | 320 | |
6d0f6bcf | 321 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
d9b94f28 JL |
322 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
323 | ||
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
325 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
d9b94f28 | 326 | |
20476726 JL |
327 | /* |
328 | * I2C | |
329 | */ | |
00f792e0 HS |
330 | #define CONFIG_SYS_I2C |
331 | #define CONFIG_SYS_I2C_FSL | |
332 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
333 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
334 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
335 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
d9b94f28 | 336 | |
e8d18541 TT |
337 | /* EEPROM */ |
338 | #define CONFIG_ID_EEPROM | |
6d0f6bcf JCPV |
339 | #define CONFIG_SYS_I2C_EEPROM_CCID |
340 | #define CONFIG_SYS_ID_EEPROM | |
341 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
342 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
e8d18541 | 343 | |
d9b94f28 JL |
344 | /* |
345 | * General PCI | |
362dd830 | 346 | * Memory space is mapped 1-1, but I/O space must start from 0. |
d9b94f28 | 347 | */ |
5af0fdd8 | 348 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
b76aef60 | 349 | #ifdef CONFIG_PHYS_64BIT |
350 | #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 | |
351 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull | |
352 | #else | |
10795f42 | 353 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 354 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
b76aef60 | 355 | #endif |
6d0f6bcf | 356 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 357 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 358 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
b76aef60 | 359 | #ifdef CONFIG_PHYS_64BIT |
360 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull | |
361 | #else | |
6d0f6bcf | 362 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
b76aef60 | 363 | #endif |
6d0f6bcf | 364 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
d9b94f28 | 365 | |
f2cff6b1 | 366 | #ifdef CONFIG_PCIE1 |
f5fa8f36 | 367 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
5af0fdd8 | 368 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
b76aef60 | 369 | #ifdef CONFIG_PHYS_64BIT |
370 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
371 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull | |
372 | #else | |
10795f42 | 373 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
5af0fdd8 | 374 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
b76aef60 | 375 | #endif |
6d0f6bcf | 376 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 377 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 |
5f91ef6a | 378 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
b76aef60 | 379 | #ifdef CONFIG_PHYS_64BIT |
380 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull | |
381 | #else | |
6d0f6bcf | 382 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 |
b76aef60 | 383 | #endif |
6d0f6bcf | 384 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ |
f2cff6b1 | 385 | #endif |
d9b94f28 | 386 | |
41fb7e0f ZR |
387 | /* |
388 | * RapidIO MMU | |
389 | */ | |
fff80975 | 390 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 |
b76aef60 | 391 | #ifdef CONFIG_PHYS_64BIT |
392 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull | |
393 | #else | |
fff80975 | 394 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 |
b76aef60 | 395 | #endif |
8b47d7ec | 396 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ |
d9b94f28 | 397 | |
7f3f2bd2 RV |
398 | #ifdef CONFIG_LEGACY |
399 | #define BRIDGE_ID 17 | |
400 | #define VIA_ID 2 | |
401 | #else | |
402 | #define BRIDGE_ID 28 | |
403 | #define VIA_ID 4 | |
404 | #endif | |
405 | ||
d9b94f28 JL |
406 | #if defined(CONFIG_PCI) |
407 | ||
f2cff6b1 | 408 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d9b94f28 JL |
409 | |
410 | #undef CONFIG_EEPRO100 | |
411 | #undef CONFIG_TULIP | |
412 | ||
867b06f4 | 413 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
f2cff6b1 | 414 | |
d9b94f28 JL |
415 | #endif /* CONFIG_PCI */ |
416 | ||
d9b94f28 JL |
417 | #if defined(CONFIG_TSEC_ENET) |
418 | ||
d9b94f28 | 419 | #define CONFIG_MII 1 /* MII PHY management */ |
255a3577 KP |
420 | #define CONFIG_TSEC1 1 |
421 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
422 | #define CONFIG_TSEC2 1 | |
423 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
424 | #define CONFIG_TSEC3 1 | |
425 | #define CONFIG_TSEC3_NAME "eTSEC2" | |
f2cff6b1 | 426 | #define CONFIG_TSEC4 |
255a3577 | 427 | #define CONFIG_TSEC4_NAME "eTSEC3" |
d9b94f28 JL |
428 | #undef CONFIG_MPC85XX_FEC |
429 | ||
d3701228 | 430 | #define CONFIG_PHY_MARVELL |
431 | ||
d9b94f28 JL |
432 | #define TSEC1_PHY_ADDR 0 |
433 | #define TSEC2_PHY_ADDR 1 | |
434 | #define TSEC3_PHY_ADDR 2 | |
435 | #define TSEC4_PHY_ADDR 3 | |
d9b94f28 JL |
436 | |
437 | #define TSEC1_PHYIDX 0 | |
438 | #define TSEC2_PHYIDX 0 | |
439 | #define TSEC3_PHYIDX 0 | |
440 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
441 | #define TSEC1_FLAGS TSEC_GIGABIT |
442 | #define TSEC2_FLAGS TSEC_GIGABIT | |
443 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
444 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
d9b94f28 JL |
445 | |
446 | /* Options are: eTSEC[0-3] */ | |
447 | #define CONFIG_ETHPRIME "eTSEC0" | |
f2cff6b1 | 448 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
d9b94f28 JL |
449 | #endif /* CONFIG_TSEC_ENET */ |
450 | ||
451 | /* | |
452 | * Environment | |
453 | */ | |
5a1aceb0 | 454 | #define CONFIG_ENV_IS_IN_FLASH 1 |
867b06f4 | 455 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
456 | #define CONFIG_ENV_ADDR 0xfff80000 | |
457 | #else | |
458 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
459 | #endif | |
460 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ | |
0e8d1586 | 461 | #define CONFIG_ENV_SIZE 0x2000 |
d9b94f28 JL |
462 | |
463 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 464 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
d9b94f28 | 465 | |
659e2f67 JL |
466 | /* |
467 | * BOOTP options | |
468 | */ | |
469 | #define CONFIG_BOOTP_BOOTFILESIZE | |
470 | #define CONFIG_BOOTP_BOOTPATH | |
471 | #define CONFIG_BOOTP_GATEWAY | |
472 | #define CONFIG_BOOTP_HOSTNAME | |
473 | ||
2835e518 JL |
474 | /* |
475 | * Command line configuration. | |
476 | */ | |
1c9aa76b | 477 | #define CONFIG_CMD_IRQ |
199e262e | 478 | #define CONFIG_CMD_REGINFO |
2835e518 | 479 | |
d9b94f28 | 480 | #if defined(CONFIG_PCI) |
2835e518 | 481 | #define CONFIG_CMD_PCI |
d9b94f28 | 482 | #endif |
2835e518 | 483 | |
d9b94f28 JL |
484 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
485 | ||
486 | /* | |
487 | * Miscellaneous configurable options | |
488 | */ | |
6d0f6bcf | 489 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
490 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
491 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 492 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
2835e518 | 493 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 494 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d9b94f28 | 495 | #else |
6d0f6bcf | 496 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d9b94f28 | 497 | #endif |
6d0f6bcf JCPV |
498 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
499 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
500 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
d9b94f28 JL |
501 | |
502 | /* | |
503 | * For booting Linux, the board info and command line data | |
a832ac41 | 504 | * have to be in the first 64 MB of memory, since this is |
d9b94f28 JL |
505 | * the maximum mapped by the Linux kernel during initialization. |
506 | */ | |
a832ac41 KG |
507 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
508 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
d9b94f28 | 509 | |
2835e518 | 510 | #if defined(CONFIG_CMD_KGDB) |
d9b94f28 | 511 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
d9b94f28 JL |
512 | #endif |
513 | ||
514 | /* | |
515 | * Environment Configuration | |
516 | */ | |
d9b94f28 | 517 | #if defined(CONFIG_TSEC_ENET) |
10327dc5 | 518 | #define CONFIG_HAS_ETH0 |
d9b94f28 | 519 | #define CONFIG_HAS_ETH1 |
d9b94f28 | 520 | #define CONFIG_HAS_ETH2 |
09f3e09e | 521 | #define CONFIG_HAS_ETH3 |
d9b94f28 JL |
522 | #endif |
523 | ||
f2cff6b1 | 524 | #define CONFIG_IPADDR 192.168.1.253 |
d9b94f28 | 525 | |
f2cff6b1 | 526 | #define CONFIG_HOSTNAME unknown |
8b3637c6 | 527 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 528 | #define CONFIG_BOOTFILE "8548cds/uImage.uboot" |
f2cff6b1 | 529 | #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ |
d9b94f28 | 530 | |
f2cff6b1 | 531 | #define CONFIG_SERVERIP 192.168.1.1 |
d9b94f28 | 532 | #define CONFIG_GATEWAYIP 192.168.1.1 |
f2cff6b1 | 533 | #define CONFIG_NETMASK 255.255.255.0 |
d9b94f28 | 534 | |
f2cff6b1 | 535 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
d9b94f28 | 536 | |
f2cff6b1 | 537 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
d9b94f28 JL |
538 | |
539 | #define CONFIG_BAUDRATE 115200 | |
540 | ||
867b06f4 | 541 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
542 | "hwconfig=fsl_ddr:ecc=off\0" \ | |
543 | "netdev=eth0\0" \ | |
5368c55d | 544 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
867b06f4 | 545 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
546 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
547 | " +$filesize; " \ | |
548 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
549 | " +$filesize; " \ | |
550 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
551 | " $filesize; " \ | |
552 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
553 | " +$filesize; " \ | |
554 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
555 | " $filesize\0" \ | |
867b06f4 | 556 | "consoledev=ttyS1\0" \ |
557 | "ramdiskaddr=2000000\0" \ | |
558 | "ramdiskfile=ramdisk.uboot\0" \ | |
b24a4f62 | 559 | "fdtaddr=1e00000\0" \ |
867b06f4 | 560 | "fdtfile=mpc8548cds.dtb\0" |
f2cff6b1 ES |
561 | |
562 | #define CONFIG_NFSBOOTCOMMAND \ | |
563 | "setenv bootargs root=/dev/nfs rw " \ | |
564 | "nfsroot=$serverip:$rootpath " \ | |
d9b94f28 | 565 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
f2cff6b1 ES |
566 | "console=$consoledev,$baudrate $othbootargs;" \ |
567 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
568 | "tftp $fdtaddr $fdtfile;" \ |
569 | "bootm $loadaddr - $fdtaddr" | |
8272dc2f | 570 | |
d9b94f28 | 571 | #define CONFIG_RAMBOOTCOMMAND \ |
f2cff6b1 ES |
572 | "setenv bootargs root=/dev/ram rw " \ |
573 | "console=$consoledev,$baudrate $othbootargs;" \ | |
574 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
575 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
576 | "tftp $fdtaddr $fdtfile;" \ |
577 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
f2cff6b1 ES |
578 | |
579 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
d9b94f28 JL |
580 | |
581 | #endif /* __CONFIG_H */ |