]>
Commit | Line | Data |
---|---|---|
42d1f039 | 1 | /* |
0ac6f8b7 | 2 | * Copyright 2004 Freescale Semiconductor. |
42d1f039 WD |
3 | * (C) Copyright 2002,2003 Motorola,Inc. |
4 | * Xianghua Xiao <X.Xiao@motorola.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
0ac6f8b7 WD |
25 | /* |
26 | * mpc8560ads board configuration file | |
27 | * | |
28 | * Please refer to doc/README.mpc85xx for more info. | |
29 | * | |
30 | * Make sure you change the MAC address and other network params first, | |
31 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
42d1f039 WD |
32 | */ |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
37 | /* High Level Configuration Options */ | |
0ac6f8b7 WD |
38 | #define CONFIG_BOOKE 1 /* BOOKE */ |
39 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
40 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
9c4c5ae3 | 41 | #define CONFIG_CPM2 1 /* has CPM2 */ |
0ac6f8b7 WD |
42 | #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ |
43 | ||
44 | #define CONFIG_PCI | |
45 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
63ff004c | 46 | #undef CONFIG_TSEC_ENET /* tsec ethernet support */ |
0ac6f8b7 | 47 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
63ff004c | 48 | #define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
42d1f039 | 49 | #define CONFIG_ENV_OVERWRITE |
9aea9530 | 50 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
9aea9530 WD |
51 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
52 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ | |
42d1f039 | 53 | |
d9b94f28 JL |
54 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ |
55 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
56 | ||
42d1f039 | 57 | |
0ac6f8b7 WD |
58 | /* |
59 | * sysclk for MPC85xx | |
60 | * | |
61 | * Two valid values are: | |
62 | * 33000000 | |
63 | * 66000000 | |
64 | * | |
65 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
9aea9530 WD |
66 | * is likely the desired value here, so that is now the default. |
67 | * The board, however, can run at 66MHz. In any event, this value | |
68 | * must match the settings of some switches. Details can be found | |
69 | * in the README.mpc85xxads. | |
0ac6f8b7 WD |
70 | */ |
71 | ||
9aea9530 WD |
72 | #ifndef CONFIG_SYS_CLK_FREQ |
73 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
42d1f039 WD |
74 | #endif |
75 | ||
9aea9530 | 76 | |
0ac6f8b7 WD |
77 | /* |
78 | * These can be toggled for performance analysis, otherwise use default. | |
79 | */ | |
80 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
81 | #define CONFIG_BTB /* toggle branch predition */ | |
82 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
42d1f039 | 83 | |
0ac6f8b7 | 84 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
42d1f039 | 85 | |
0ac6f8b7 WD |
86 | #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
87 | ||
9aea9530 | 88 | #undef CFG_DRAM_TEST /* memory test, takes time */ |
0ac6f8b7 | 89 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ |
c837dcb1 | 90 | #define CFG_MEMTEST_END 0x00400000 |
42d1f039 | 91 | |
42d1f039 WD |
92 | |
93 | /* | |
94 | * Base addresses -- Note these are effective addresses where the | |
95 | * actual resources get mapped (not physical addresses) | |
96 | */ | |
0ac6f8b7 | 97 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
9aea9530 | 98 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
0ac6f8b7 | 99 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
42d1f039 | 100 | |
9aea9530 WD |
101 | |
102 | /* | |
103 | * DDR Setup | |
104 | */ | |
0ac6f8b7 | 105 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
42d1f039 | 106 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
9aea9530 WD |
107 | |
108 | #if defined(CONFIG_SPD_EEPROM) | |
109 | /* | |
110 | * Determine DDR configuration from I2C interface. | |
111 | */ | |
112 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
113 | ||
114 | #else | |
115 | /* | |
116 | * Manually set up DDR parameters | |
117 | */ | |
118 | #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ | |
119 | #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ | |
120 | #define CFG_DDR_CS0_CONFIG 0x80000002 | |
121 | #define CFG_DDR_TIMING_1 0x37344321 | |
122 | #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
123 | #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
124 | #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ | |
125 | #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ | |
126 | #endif | |
127 | ||
42d1f039 | 128 | |
0ac6f8b7 WD |
129 | /* |
130 | * SDRAM on the Local Bus | |
131 | */ | |
0ac6f8b7 | 132 | #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
0ac6f8b7 | 133 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
42d1f039 | 134 | |
0ac6f8b7 WD |
135 | #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
136 | #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
42d1f039 | 137 | |
0ac6f8b7 WD |
138 | #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ |
139 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
140 | #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ | |
42d1f039 | 141 | #undef CFG_FLASH_CHECKSUM |
0ac6f8b7 WD |
142 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
143 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
144 | ||
145 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
42d1f039 | 146 | |
42d1f039 WD |
147 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
148 | #define CFG_RAMBOOT | |
149 | #else | |
0ac6f8b7 | 150 | #undef CFG_RAMBOOT |
42d1f039 WD |
151 | #endif |
152 | ||
cf33678e WD |
153 | #define CFG_FLASH_CFI_DRIVER |
154 | #define CFG_FLASH_CFI | |
155 | #define CFG_FLASH_EMPTY_INFO | |
0ac6f8b7 WD |
156 | |
157 | #undef CONFIG_CLOCKS_IN_MHZ | |
42d1f039 | 158 | |
42d1f039 | 159 | |
0ac6f8b7 WD |
160 | /* |
161 | * Local Bus Definitions | |
162 | */ | |
163 | ||
164 | /* | |
165 | * Base Register 2 and Option Register 2 configure SDRAM. | |
166 | * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. | |
167 | * | |
168 | * For BR2, need: | |
169 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
170 | * port-size = 32-bits = BR2[19:20] = 11 | |
171 | * no parity checking = BR2[21:22] = 00 | |
172 | * SDRAM for MSEL = BR2[24:26] = 011 | |
173 | * Valid = BR[31] = 1 | |
174 | * | |
175 | * 0 4 8 12 16 20 24 28 | |
176 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
177 | * | |
178 | * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into | |
179 | * FIXME: the top 17 bits of BR2. | |
180 | */ | |
181 | ||
182 | #define CFG_BR2_PRELIM 0xf0001861 | |
183 | ||
184 | /* | |
185 | * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. | |
186 | * | |
187 | * For OR2, need: | |
188 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
189 | * XAM, OR2[17:18] = 11 | |
190 | * 9 columns OR2[19-21] = 010 | |
191 | * 13 rows OR2[23-25] = 100 | |
192 | * EAD set for extra time OR[31] = 1 | |
193 | * | |
194 | * 0 4 8 12 16 20 24 28 | |
195 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
196 | */ | |
197 | ||
42d1f039 | 198 | #define CFG_OR2_PRELIM 0xfc006901 |
0ac6f8b7 WD |
199 | |
200 | #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ | |
201 | #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ | |
202 | #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
203 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ | |
204 | ||
205 | /* | |
206 | * LSDMR masks | |
207 | */ | |
208 | #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) | |
209 | #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) | |
210 | #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) | |
211 | #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) | |
212 | #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) | |
213 | #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) | |
214 | #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) | |
215 | #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) | |
216 | #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) | |
217 | #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) | |
218 | #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) | |
219 | #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) | |
220 | #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) | |
221 | #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) | |
222 | #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) | |
223 | ||
224 | #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) | |
225 | #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) | |
226 | #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) | |
227 | #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) | |
228 | #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) | |
229 | #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) | |
230 | #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) | |
231 | #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) | |
232 | ||
233 | #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ | |
234 | | CFG_LBC_LSDMR_RFCR5 \ | |
235 | | CFG_LBC_LSDMR_PRETOACT3 \ | |
236 | | CFG_LBC_LSDMR_ACTTORW3 \ | |
237 | | CFG_LBC_LSDMR_BL8 \ | |
238 | | CFG_LBC_LSDMR_WRC2 \ | |
239 | | CFG_LBC_LSDMR_CL3 \ | |
240 | | CFG_LBC_LSDMR_RFEN \ | |
241 | ) | |
242 | ||
243 | /* | |
244 | * SDRAM Controller configuration sequence. | |
245 | */ | |
246 | #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ | |
9aea9530 | 247 | | CFG_LBC_LSDMR_OP_PCHALL) |
0ac6f8b7 | 248 | #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
9aea9530 | 249 | | CFG_LBC_LSDMR_OP_ARFRSH) |
0ac6f8b7 | 250 | #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
9aea9530 | 251 | | CFG_LBC_LSDMR_OP_ARFRSH) |
0ac6f8b7 | 252 | #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
9aea9530 | 253 | | CFG_LBC_LSDMR_OP_MRW) |
0ac6f8b7 | 254 | #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
9aea9530 | 255 | | CFG_LBC_LSDMR_OP_NORMAL) |
0ac6f8b7 | 256 | |
42d1f039 | 257 | |
9aea9530 WD |
258 | /* |
259 | * 32KB, 8-bit wide for ADS config reg | |
260 | */ | |
261 | #define CFG_BR4_PRELIM 0xf8000801 | |
42d1f039 WD |
262 | #define CFG_OR4_PRELIM 0xffffe1f1 |
263 | #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) | |
264 | ||
265 | #define CONFIG_L1_INIT_RAM | |
0ac6f8b7 | 266 | #define CFG_INIT_RAM_LOCK 1 |
9aea9530 | 267 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
0ac6f8b7 | 268 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
42d1f039 | 269 | |
0ac6f8b7 | 270 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
42d1f039 WD |
271 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
272 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
273 | ||
a1191902 | 274 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
0ac6f8b7 | 275 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
42d1f039 WD |
276 | |
277 | /* Serial Port */ | |
0ac6f8b7 WD |
278 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
279 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
280 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
42d1f039 | 281 | |
0ac6f8b7 | 282 | #define CONFIG_BAUDRATE 115200 |
42d1f039 WD |
283 | |
284 | #define CFG_BAUDRATE_TABLE \ | |
285 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
286 | ||
287 | /* Use the HUSH parser */ | |
288 | #define CFG_HUSH_PARSER | |
0ac6f8b7 | 289 | #ifdef CFG_HUSH_PARSER |
42d1f039 WD |
290 | #define CFG_PROMPT_HUSH_PS2 "> " |
291 | #endif | |
292 | ||
0e16387d MM |
293 | /* pass open firmware flat tree */ |
294 | #define CONFIG_OF_FLAT_TREE 1 | |
295 | #define CONFIG_OF_BOARD_SETUP 1 | |
296 | ||
297 | /* maximum size of the flat tree (8K) */ | |
298 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
299 | ||
300 | #define OF_CPU "PowerPC,8560@0" | |
301 | #define OF_SOC "soc8560@e0000000" | |
302 | #define OF_TBCLK (bd->bi_busfreq / 8) | |
303 | #define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" | |
304 | ||
20476726 JL |
305 | /* |
306 | * I2C | |
307 | */ | |
308 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
309 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
42d1f039 | 310 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
0ac6f8b7 | 311 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
42d1f039 | 312 | #define CFG_I2C_SLAVE 0x7F |
9aea9530 | 313 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
20476726 | 314 | #define CFG_I2C_OFFSET 0x3000 |
42d1f039 | 315 | |
0ac6f8b7 WD |
316 | /* RapidIO MMU */ |
317 | #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ | |
318 | #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE | |
319 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ | |
320 | ||
321 | /* | |
322 | * General PCI | |
362dd830 | 323 | * Memory space is mapped 1-1, but I/O space must start from 0. |
0ac6f8b7 WD |
324 | */ |
325 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
326 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
327 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
362dd830 SS |
328 | #define CFG_PCI1_IO_BASE 0x00000000 |
329 | #define CFG_PCI1_IO_PHYS 0xe2000000 | |
330 | #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ | |
0ac6f8b7 WD |
331 | |
332 | #if defined(CONFIG_PCI) | |
42d1f039 | 333 | |
42d1f039 | 334 | #define CONFIG_NET_MULTI |
9aea9530 | 335 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
0ac6f8b7 WD |
336 | |
337 | #undef CONFIG_EEPRO100 | |
42d1f039 | 338 | #undef CONFIG_TULIP |
0ac6f8b7 WD |
339 | |
340 | #if !defined(CONFIG_PCI_PNP) | |
341 | #define PCI_ENET0_IOADDR 0xe0000000 | |
342 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
343 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
42d1f039 | 344 | #endif |
0ac6f8b7 WD |
345 | |
346 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
347 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
348 | ||
349 | #endif /* CONFIG_PCI */ | |
350 | ||
351 | ||
352 | #if defined(CONFIG_TSEC_ENET) | |
353 | ||
354 | #ifndef CONFIG_NET_MULTI | |
355 | #define CONFIG_NET_MULTI 1 | |
356 | #endif | |
357 | ||
358 | #define CONFIG_MII 1 /* MII PHY management */ | |
255a3577 KP |
359 | #define CONFIG_TSEC1 1 |
360 | #define CONFIG_TSEC1_NAME "TSEC0" | |
361 | #define CONFIG_TSEC2 1 | |
362 | #define CONFIG_TSEC2_NAME "TSEC1" | |
0ac6f8b7 WD |
363 | #undef CONFIG_MPC85XX_FEC |
364 | #define TSEC1_PHY_ADDR 0 | |
365 | #define TSEC2_PHY_ADDR 1 | |
366 | #define TSEC1_PHYIDX 0 | |
367 | #define TSEC2_PHYIDX 0 | |
d9b94f28 JL |
368 | |
369 | /* Options are: TSEC[0-1] */ | |
370 | #define CONFIG_ETHPRIME "TSEC0" | |
0ac6f8b7 | 371 | |
42d1f039 | 372 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |
0ac6f8b7 WD |
373 | |
374 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
375 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
376 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ | |
377 | ||
378 | #if (CONFIG_ETHER_INDEX == 2) | |
42d1f039 WD |
379 | /* |
380 | * - Rx-CLK is CLK13 | |
381 | * - Tx-CLK is CLK14 | |
382 | * - Select bus for bd/buffers | |
383 | * - Full duplex | |
384 | */ | |
0ac6f8b7 WD |
385 | #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
386 | #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
387 | #define CFG_CPMFCR_RAMTYPE 0 | |
388 | #define CFG_FCC_PSMR (FCC_PSMR_FDE) | |
42d1f039 | 389 | #define FETH2_RST 0x01 |
0ac6f8b7 | 390 | #elif (CONFIG_ETHER_INDEX == 3) |
42d1f039 WD |
391 | /* need more definitions here for FE3 */ |
392 | #define FETH3_RST 0x80 | |
0ac6f8b7 WD |
393 | #endif /* CONFIG_ETHER_INDEX */ |
394 | ||
42d1f039 | 395 | #define CONFIG_MII /* MII PHY management */ |
0ac6f8b7 WD |
396 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
397 | ||
42d1f039 WD |
398 | /* |
399 | * GPIO pins used for bit-banged MII communications | |
400 | */ | |
401 | #define MDIO_PORT 2 /* Port C */ | |
402 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) | |
403 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
404 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
405 | ||
406 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
407 | else iop->pdat &= ~0x00400000 | |
408 | ||
409 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
410 | else iop->pdat &= ~0x00200000 | |
411 | ||
412 | #define MIIDELAY udelay(1) | |
0ac6f8b7 | 413 | |
42d1f039 WD |
414 | #endif |
415 | ||
0ac6f8b7 WD |
416 | |
417 | /* | |
418 | * Environment | |
419 | */ | |
42d1f039 | 420 | #ifndef CFG_RAMBOOT |
42d1f039 WD |
421 | #define CFG_ENV_IS_IN_FLASH 1 |
422 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
0ac6f8b7 | 423 | #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
42d1f039 WD |
424 | #define CFG_ENV_SIZE 0x2000 |
425 | #else | |
9aea9530 WD |
426 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ |
427 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
428 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
429 | #define CFG_ENV_SIZE 0x2000 | |
42d1f039 WD |
430 | #endif |
431 | ||
0ac6f8b7 WD |
432 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
433 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
42d1f039 | 434 | |
9aea9530 | 435 | #if defined(CFG_RAMBOOT) |
42d1f039 | 436 | #if defined(CONFIG_PCI) |
0ac6f8b7 | 437 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
0ac6f8b7 | 438 | | CFG_CMD_PING \ |
9aea9530 | 439 | | CFG_CMD_PCI \ |
0ac6f8b7 WD |
440 | | CFG_CMD_I2C) \ |
441 | & \ | |
9aea9530 | 442 | ~(CFG_CMD_ENV \ |
0ac6f8b7 | 443 | | CFG_CMD_LOADS)) |
42d1f039 | 444 | #elif defined(CONFIG_TSEC_ENET) |
0ac6f8b7 WD |
445 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
446 | | CFG_CMD_PING \ | |
447 | | CFG_CMD_I2C) \ | |
448 | & ~(CFG_CMD_ENV)) | |
42d1f039 | 449 | #elif defined(CONFIG_ETHER_ON_FCC) |
0ac6f8b7 WD |
450 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
451 | | CFG_CMD_MII \ | |
452 | | CFG_CMD_PING \ | |
453 | | CFG_CMD_I2C) \ | |
454 | & ~(CFG_CMD_ENV)) | |
42d1f039 WD |
455 | #endif |
456 | #else | |
457 | #if defined(CONFIG_PCI) | |
0ac6f8b7 WD |
458 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
459 | | CFG_CMD_PCI \ | |
460 | | CFG_CMD_PING \ | |
461 | | CFG_CMD_I2C) | |
42d1f039 | 462 | #elif defined(CONFIG_TSEC_ENET) |
0ac6f8b7 WD |
463 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
464 | | CFG_CMD_PING \ | |
465 | | CFG_CMD_I2C) | |
42d1f039 | 466 | #elif defined(CONFIG_ETHER_ON_FCC) |
0ac6f8b7 WD |
467 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
468 | | CFG_CMD_MII \ | |
469 | | CFG_CMD_PING \ | |
470 | | CFG_CMD_I2C) | |
42d1f039 WD |
471 | #endif |
472 | #endif | |
0ac6f8b7 | 473 | |
42d1f039 WD |
474 | #include <cmd_confdefs.h> |
475 | ||
0ac6f8b7 | 476 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
42d1f039 WD |
477 | |
478 | /* | |
479 | * Miscellaneous configurable options | |
480 | */ | |
0ac6f8b7 WD |
481 | #define CFG_LONGHELP /* undef to save memory */ |
482 | #define CFG_LOAD_ADDR 0x1000000 /* default load address */ | |
483 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
484 | ||
42d1f039 | 485 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
0ac6f8b7 | 486 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
42d1f039 | 487 | #else |
0ac6f8b7 | 488 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
42d1f039 | 489 | #endif |
0ac6f8b7 | 490 | |
42d1f039 | 491 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
0ac6f8b7 WD |
492 | #define CFG_MAXARGS 16 /* max number of command args */ |
493 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
494 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
42d1f039 WD |
495 | |
496 | /* | |
497 | * For booting Linux, the board info and command line data | |
498 | * have to be in the first 8 MB of memory, since this is | |
499 | * the maximum mapped by the Linux kernel during initialization. | |
500 | */ | |
0ac6f8b7 | 501 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
42d1f039 WD |
502 | |
503 | /* Cache Configuration */ | |
504 | #define CFG_DCACHE_SIZE 32768 | |
505 | #define CFG_CACHELINE_SIZE 32 | |
506 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
0ac6f8b7 | 507 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
42d1f039 WD |
508 | #endif |
509 | ||
510 | /* | |
511 | * Internal Definitions | |
512 | * | |
513 | * Boot Flags | |
514 | */ | |
515 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
0ac6f8b7 | 516 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
42d1f039 WD |
517 | |
518 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
519 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
520 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
521 | #endif | |
522 | ||
9aea9530 WD |
523 | |
524 | /* | |
525 | * Environment Configuration | |
526 | */ | |
527 | ||
0ac6f8b7 | 528 | /* The mac addresses for all ethernet interface */ |
42d1f039 | 529 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
0ac6f8b7 | 530 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
e2ffd59b | 531 | #define CONFIG_HAS_ETH1 |
0ac6f8b7 | 532 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
e2ffd59b | 533 | #define CONFIG_HAS_ETH2 |
0ac6f8b7 | 534 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
42d1f039 WD |
535 | #endif |
536 | ||
0ac6f8b7 WD |
537 | #define CONFIG_IPADDR 192.168.1.253 |
538 | ||
539 | #define CONFIG_HOSTNAME unknown | |
540 | #define CONFIG_ROOTPATH /nfsroot | |
541 | #define CONFIG_BOOTFILE your.uImage | |
542 | ||
543 | #define CONFIG_SERVERIP 192.168.1.1 | |
544 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
545 | #define CONFIG_NETMASK 255.255.255.0 | |
546 | ||
547 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
548 | ||
9aea9530 | 549 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
0ac6f8b7 WD |
550 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
551 | ||
552 | #define CONFIG_BAUDRATE 115200 | |
553 | ||
9aea9530 | 554 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
0ac6f8b7 WD |
555 | "netdev=eth0\0" \ |
556 | "consoledev=ttyS0\0" \ | |
557 | "ramdiskaddr=400000\0" \ | |
558 | "ramdiskfile=your.ramdisk.u-boot\0" | |
559 | ||
9aea9530 | 560 | #define CONFIG_NFSBOOTCOMMAND \ |
0ac6f8b7 WD |
561 | "setenv bootargs root=/dev/nfs rw " \ |
562 | "nfsroot=$serverip:$rootpath " \ | |
563 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
564 | "console=$consoledev,$baudrate $othbootargs;" \ | |
565 | "tftp $loadaddr $bootfile;" \ | |
566 | "bootm $loadaddr" | |
567 | ||
568 | #define CONFIG_RAMBOOTCOMMAND \ | |
569 | "setenv bootargs root=/dev/ram rw " \ | |
570 | "console=$consoledev,$baudrate $othbootargs;" \ | |
571 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
572 | "tftp $loadaddr $bootfile;" \ | |
573 | "bootm $loadaddr $ramdiskaddr" | |
574 | ||
575 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
42d1f039 WD |
576 | |
577 | #endif /* __CONFIG_H */ |