projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 9553df86 JL |
1 | /* |
| 2 | * Copyright 2007 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License | |
| 6 | * Version 2 as published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| 9 | /* | |
| 10 | * MPC8610HPCD board configuration file | |
| 11 | * | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef __CONFIG_H | |
| 15 | #define __CONFIG_H | |
| 16 | ||
| 17 | /* High Level Configuration Options */ | |
| 18 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
| 19 | #define CONFIG_MPC8610 1 /* MPC8610 specific */ | |
| 20 | #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ | |
| 21 | #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ | |
| 22 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ | |
| 23 | ||
| 24 | #ifdef RUN_DIAG | |
| 25 | #define CFG_DIAG_ADDR 0xff800000 | |
| 26 | #endif | |
| 27 | ||
| 28 | #define CFG_RESET_ADDRESS 0xfff00100 | |
| 29 | ||
| 30 | #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ | |
| 31 | #define CONFIG_PCI1 1 /* PCI controler 1 */ | |
| 32 | #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ | |
| 33 | #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ | |
| 34 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 35 | ||
| 36 | #define CONFIG_ENV_OVERWRITE | |
| 37 | ||
| 38 | #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ | |
| 39 | #undef CONFIG_DDR_DLL /* possible DLL fix needed */ | |
| 40 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ | |
| 41 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ | |
| 42 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
| 43 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 44 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 45 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ | |
| 46 | ||
| 47 | #define CONFIG_ALTIVEC 1 | |
| 48 | ||
| 49 | /* | |
| 50 | * L2CR setup -- make sure this is right for your board! | |
| 51 | */ | |
| 52 | #define CFG_L2 | |
| 53 | #define L2_INIT 0 | |
| 54 | #define L2_ENABLE (L2CR_L2E) | |
| 55 | ||
| 56 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 57 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
| 58 | #endif | |
| 59 | ||
| 60 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
| 61 | ||
| 62 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
| 63 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ | |
| 64 | #define CFG_MEMTEST_END 0x00400000 | |
| 65 | #define CFG_ALT_MEMTEST | |
| 66 | ||
| 67 | /* | |
| 68 | * Base addresses -- Note these are effective addresses where the | |
| 69 | * actual resources get mapped (not physical addresses) | |
| 70 | */ | |
| 71 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
| 72 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
| 73 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ | |
| 74 | ||
| 75 | #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) | |
| 76 | #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) | |
| 77 | #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) | |
| 78 | ||
| 79 | #define CFG_DIU_ADDR (CFG_CCSRBAR+0x2c000) | |
| 80 | ||
| 81 | /* | |
| 82 | * DDR Setup | |
| 83 | */ | |
| 84 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
| 85 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
| 86 | #define CONFIG_VERY_BIG_RAM | |
| 87 | ||
| 88 | #define MPC86xx_DDR_SDRAM_CLK_CNTL | |
| 89 | ||
| 90 | #if defined(CONFIG_SPD_EEPROM) | |
| 91 | /* | |
| 92 | * Determine DDR configuration from I2C interface. | |
| 93 | */ | |
| 94 | #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ | |
| 95 | #else | |
| 96 | /* | |
| 97 | * Manually set up DDR1 parameters | |
| 98 | */ | |
| 99 | ||
| 100 | #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ | |
| 101 | ||
| 102 | #if 0 /* TODO */ | |
| 103 | #define CFG_DDR_CS0_BNDS 0x0000000F | |
| 104 | #define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ | |
| 105 | #define CFG_DDR_EXT_REFRESH 0x00000000 | |
| 106 | #define CFG_DDR_TIMING_0 0x00260802 | |
| 107 | #define CFG_DDR_TIMING_1 0x3935d322 | |
| 108 | #define CFG_DDR_TIMING_2 0x14904cc8 | |
| 109 | #define CFG_DDR_MODE_1 0x00480432 | |
| 110 | #define CFG_DDR_MODE_2 0x00000000 | |
| 111 | #define CFG_DDR_INTERVAL 0x06180100 | |
| 112 | #define CFG_DDR_DATA_INIT 0xdeadbeef | |
| 113 | #define CFG_DDR_CLK_CTRL 0x03800000 | |
| 114 | #define CFG_DDR_OCD_CTRL 0x00000000 | |
| 115 | #define CFG_DDR_OCD_STATUS 0x00000000 | |
| 116 | #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
| 117 | #define CFG_DDR_CONTROL2 0x04400010 | |
| 118 | ||
| 119 | #define CFG_DDR_ERR_INT_EN 0x00000000 | |
| 120 | #define CFG_DDR_ERR_DIS 0x00000000 | |
| 121 | #define CFG_DDR_SBE 0x000f0000 | |
| 122 | /* Not used in fixed_sdram function */ | |
| 123 | #define CFG_DDR_MODE 0x00000022 | |
| 124 | #define CFG_DDR_CS1_BNDS 0x00000000 | |
| 125 | #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ | |
| 126 | #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ | |
| 127 | #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ | |
| 128 | #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ | |
| 129 | #endif | |
| 130 | #endif | |
| 131 | ||
| 132 | #define CFG_ID_EEPROM | |
| 133 | #define ID_EEPROM_ADDR 0x57 | |
| 134 | ||
| 135 | ||
| 136 | #define CFG_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ | |
| 137 | #define CFG_FLASH_BASE2 0xf8000000 | |
| 138 | ||
| 139 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} | |
| 140 | ||
| 141 | #define CFG_BR0_PRELIM 0xf8001001 /* port size 16bit */ | |
| 142 | #define CFG_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ | |
| 143 | ||
| 144 | #define CFG_BR1_PRELIM 0xf0001001 /* port size 16bit */ | |
| 145 | #define CFG_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ | |
| 146 | #if 0 /* TODO */ | |
| 147 | #define CFG_BR2_PRELIM 0xf0000000 | |
| 148 | #define CFG_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ | |
| 149 | #endif | |
| 150 | #define CFG_BR3_PRELIM 0xe8000801 /* port size 8bit */ | |
| 151 | #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
| 152 | ||
| 153 | ||
| 154 | #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ | |
| 155 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
| 156 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 157 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 158 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 159 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ | |
| 160 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 161 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 162 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 163 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 164 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 165 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
| 166 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 167 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 168 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 169 | ||
| 170 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 171 | #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 172 | ||
| 173 | #undef CFG_FLASH_CHECKSUM | |
| 174 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 175 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 176 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 177 | ||
| 178 | #define CFG_FLASH_CFI_DRIVER | |
| 179 | #define CFG_FLASH_CFI | |
| 180 | #define CFG_FLASH_EMPTY_INFO | |
| 181 | ||
| 182 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
| 183 | #define CFG_RAMBOOT | |
| 184 | #else | |
| 185 | #undef CFG_RAMBOOT | |
| 186 | #endif | |
| 187 | ||
| 188 | #if defined(CFG_RAMBOOT) | |
| 189 | #undef CONFIG_SPD_EEPROM | |
| 190 | #define CFG_SDRAM_SIZE 256 | |
| 191 | #endif | |
| 192 | ||
| 193 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 194 | ||
| 195 | #define CONFIG_L1_INIT_RAM | |
| 196 | #define CFG_INIT_RAM_LOCK 1 | |
| 197 | #ifndef CFG_INIT_RAM_LOCK | |
| 198 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
| 199 | #else | |
| 200 | #define CFG_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ | |
| 201 | #endif | |
| 202 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
| 203 | ||
| 204 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
| 205 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 206 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 207 | ||
| 208 | #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
| 209 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| 210 | ||
| 211 | /* Serial Port */ | |
| 212 | #define CONFIG_CONS_INDEX 1 | |
| 213 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 214 | #define CFG_NS16550 | |
| 215 | #define CFG_NS16550_SERIAL | |
| 216 | #define CFG_NS16550_REG_SIZE 1 | |
| 217 | #define CFG_NS16550_CLK get_bus_freq(0) | |
| 218 | ||
| 219 | #define CFG_BAUDRATE_TABLE \ | |
| 220 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
| 221 | ||
| 222 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
| 223 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
| 224 | ||
| 225 | /* Use the HUSH parser */ | |
| 226 | #define CFG_HUSH_PARSER | |
| 227 | #ifdef CFG_HUSH_PARSER | |
| 228 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 229 | #endif | |
| 230 | ||
| 231 | /* | |
| 232 | * Pass open firmware flat tree to kernel | |
| 233 | */ | |
| 234 | #define CONFIG_OF_FLAT_TREE 1 | |
| 235 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 236 | ||
| 237 | /* maximum size of the flat tree (8K) */ | |
| 238 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
| 239 | ||
| 240 | #define OF_CPU "PowerPC,8610@0" | |
| 241 | #define OF_SOC "soc@e0000000" | |
| 242 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
| 243 | #define OF_STDOUT_PATH "/soc@e0000000/serial@4500" | |
| 244 | ||
| 245 | #define CFG_64BIT_VSPRINTF 1 | |
| 246 | #define CFG_64BIT_STRTOUL 1 | |
| 247 | ||
| 248 | /* | |
| 249 | * I2C | |
| 250 | */ | |
| 251 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 252 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
| 253 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 254 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 255 | #define CFG_I2C_SLAVE 0x7F | |
| 256 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
| 257 | #define CFG_I2C_OFFSET 0x3000 | |
| 258 | ||
| 259 | /* | |
| 260 | * General PCI | |
| 261 | * Addresses are mapped 1-1. | |
| 262 | */ | |
| 263 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
| 264 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
| 265 | #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 266 | #define CFG_PCI1_IO_BASE 0x00000000 | |
| 267 | #define CFG_PCI1_IO_PHYS 0xe1000000 | |
| 268 | #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
| 269 | ||
| 270 | /* PCI view of System Memory */ | |
| 271 | #define CFG_PCI_MEMORY_BUS 0x00000000 | |
| 272 | #define CFG_PCI_MEMORY_PHYS 0x00000000 | |
| 273 | #define CFG_PCI_MEMORY_SIZE 0x80000000 | |
| 274 | ||
| 275 | /* For RTL8139 */ | |
| 276 | #define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) | |
| 277 | #define _IO_BASE 0x00000000 | |
| 278 | ||
| 279 | /* controller 1, Base address 0xa000 */ | |
| 280 | #define CFG_PCIE1_MEM_BASE 0xa0000000 | |
| 281 | #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE | |
| 282 | #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
| 283 | #define CFG_PCIE1_IO_BASE 0x00000000 | |
| 284 | #define CFG_PCIE1_IO_PHYS 0xe3000000 | |
| 285 | #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ | |
| 286 | ||
| 287 | /* controller 2, Base Address 0x9000 */ | |
| 288 | #define CFG_PCIE2_MEM_BASE 0x90000000 | |
| 289 | #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE | |
| 290 | #define CFG_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
| 291 | #define CFG_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */ | |
| 292 | #define CFG_PCIE2_IO_PHYS 0xe2000000 | |
| 293 | #define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ | |
| 294 | ||
| 295 | ||
| 296 | #if defined(CONFIG_PCI) | |
| 297 | ||
| 298 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 299 | ||
| 300 | #define CONFIG_NET_MULTI | |
| 301 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 302 | ||
| 303 | #if 0 /* TODO */ | |
| 304 | /* enable onboard uli network support */ | |
| 305 | #endif | |
| 306 | ||
| 307 | #define CONFIG_RTL8139 | |
| 308 | #define CONFIG_SK98 | |
| 309 | #define CONFIG_EEPRO100 | |
| 310 | #define CONFIG_TULIP | |
| 311 | ||
| 312 | #if 0 /* TODO */ | |
| 313 | /************************************************************ | |
| 314 | * USB support | |
| 315 | ************************************************************/ | |
| 316 | #define CONFIG_USB_OHCI 1 | |
| 317 | #define CONFIG_USB_KEYBOARD 1 | |
| 318 | #define CFG_DEVICE_DEREGISTER | |
| 319 | #define CFG_USB_INTERRUPT_POLL 1 | |
| 320 | #endif | |
| 321 | ||
| 322 | #if !defined(CONFIG_PCI_PNP) | |
| 323 | #define PCI_ENET0_IOADDR 0xe0000000 | |
| 324 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
| 325 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
| 326 | #endif | |
| 327 | ||
| 328 | #define CONFIG_DOS_PARTITION | |
| 329 | #define CONFIG_SCSI_AHCI | |
| 330 | ||
| 331 | #ifdef CONFIG_SCSI_AHCI | |
| 332 | #define CONFIG_SATA_ULI5288 | |
| 333 | #define CFG_SCSI_MAX_SCSI_ID 4 | |
| 334 | #define CFG_SCSI_MAX_LUN 1 | |
| 335 | #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) | |
| 336 | #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE | |
| 337 | #endif | |
| 338 | ||
| 339 | #endif /* CONFIG_PCI */ | |
| 340 | ||
| 341 | /* | |
| 342 | * BAT0 2G Cacheable, non-guarded | |
| 343 | * 0x0000_0000 2G DDR | |
| 344 | */ | |
| 345 | #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 346 | #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) | |
| 347 | #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) | |
| 348 | #define CFG_IBAT0U CFG_DBAT0U | |
| 349 | ||
| 350 | /* | |
| 351 | * BAT1 1G Cache-inhibited, guarded | |
| 352 | * 0x8000_0000 256M PCI-1 Memory | |
| 353 | * 0xa000_0000 256M PCI-Express 1 Memory | |
| 354 | * 0x9000_0000 256M PCI-Express 2 Memory | |
| 355 | */ | |
| 356 | ||
| 357 | #define CFG_DBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 358 | | BATL_GUARDEDSTORAGE) | |
| 359 | #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) | |
| 360 | #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 361 | #define CFG_IBAT1U CFG_DBAT1U | |
| 362 | ||
| 363 | /* | |
| 364 | * BAT2 32M Cache-inhibited, guarded | |
| 365 | * 0xe100_0000 1M PCI-1 I/O | |
| 366 | * 0xe200_0000 1M PCI-Express 2 I/O | |
| 367 | * | |
| 368 | */ | |
| 369 | ||
| 370 | #define CFG_DBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 371 | | BATL_GUARDEDSTORAGE) | |
| 372 | #define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) | |
| 373 | #define CFG_IBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 374 | #define CFG_IBAT2U CFG_DBAT2U | |
| 375 | ||
| 376 | /* | |
| 377 | * BAT3 1M Cache-inhibited, guarded | |
| 378 | * 0xe300_0000 1M PCI-Express 1 I/O | |
| 379 | * | |
| 380 | */ | |
| 381 | ||
| 382 | #define CFG_DBAT3L (CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 383 | | BATL_GUARDEDSTORAGE) | |
| 384 | #define CFG_DBAT3U (CFG_PCIE1_IO_PHYS | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 385 | #define CFG_IBAT3L (CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 386 | #define CFG_IBAT3U CFG_DBAT3U | |
| 387 | ||
| 388 | /* | |
| 389 | * BAT4 4M Cache-inhibited, guarded | |
| 390 | * 0xe000_0000 4M CCSR | |
| 391 | */ | |
| 392 | #define CFG_DBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 393 | | BATL_GUARDEDSTORAGE) | |
| 394 | #define CFG_DBAT4U (CFG_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 395 | #define CFG_IBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 396 | #define CFG_IBAT4U CFG_DBAT4U | |
| 397 | ||
| 398 | /* | |
| 399 | * BAT5 128K Cacheable, non-guarded | |
| 400 | * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) | |
| 401 | */ | |
| 402 | #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 403 | #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 404 | #define CFG_IBAT5L CFG_DBAT5L | |
| 405 | #define CFG_IBAT5U CFG_DBAT5U | |
| 406 | ||
| 407 | /* | |
| 408 | * BAT6 256M Cache-inhibited, guarded | |
| 409 | * 0xf000_0000 256M FLASH | |
| 410 | */ | |
| 411 | #define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 412 | | BATL_GUARDEDSTORAGE) | |
| 413 | #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 414 | #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 415 | #define CFG_IBAT6U CFG_DBAT6U | |
| 416 | ||
| 417 | /* | |
| 418 | * BAT7 4M Cache-inhibited, guarded | |
| 419 | * 0xe800_0000 4M PIXIS | |
| 420 | */ | |
| 421 | #define CFG_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 422 | | BATL_GUARDEDSTORAGE) | |
| 423 | #define CFG_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 424 | #define CFG_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 425 | #define CFG_IBAT7U CFG_DBAT7U | |
| 426 | ||
| 427 | ||
| 428 | /* | |
| 429 | * Environment | |
| 430 | */ | |
| 431 | #ifndef CFG_RAMBOOT | |
| 432 | #define CFG_ENV_IS_IN_FLASH 1 | |
| 433 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) | |
| 434 | #define CFG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ | |
| 435 | #define CFG_ENV_SIZE 0x2000 | |
| 436 | #else | |
| 437 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
| 438 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
| 439 | #define CFG_ENV_SIZE 0x2000 | |
| 440 | #endif | |
| 441 | ||
| 442 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 443 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 444 | ||
| 445 | ||
| 446 | /* | |
| 447 | * BOOTP options | |
| 448 | */ | |
| 449 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 450 | #define CONFIG_BOOTP_BOOTPATH | |
| 451 | #define CONFIG_BOOTP_GATEWAY | |
| 452 | #define CONFIG_BOOTP_HOSTNAME | |
| 453 | ||
| 454 | ||
| 455 | /* | |
| 456 | * Command line configuration. | |
| 457 | */ | |
| 458 | #include <config_cmd_default.h> | |
| 459 | ||
| 460 | #define CONFIG_CMD_PING | |
| 461 | #define CONFIG_CMD_I2C | |
| 462 | #define CONFIG_CMD_MII | |
| 463 | ||
| 464 | #if defined(CFG_RAMBOOT) | |
| 465 | #undef CONFIG_CMD_ENV | |
| 466 | #endif | |
| 467 | ||
| 468 | #if defined(CONFIG_PCI) | |
| 469 | #define CONFIG_CMD_PCI | |
| 470 | #define CONFIG_CMD_SCSI | |
| 471 | #define CONFIG_CMD_EXT2 | |
| 472 | #endif | |
| 473 | ||
| 474 | ||
| 475 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 476 | ||
| 477 | /* | |
| 478 | * Miscellaneous configurable options | |
| 479 | */ | |
| 480 | #define CFG_LONGHELP /* undef to save memory */ | |
| 481 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
| 482 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 483 | ||
| 484 | #if defined(CONFIG_CMD_KGDB) | |
| 485 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 486 | #else | |
| 487 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 488 | #endif | |
| 489 | ||
| 490 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 491 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 492 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 493 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 494 | ||
| 495 | /* | |
| 496 | * For booting Linux, the board info and command line data | |
| 497 | * have to be in the first 8 MB of memory, since this is | |
| 498 | * the maximum mapped by the Linux kernel during initialization. | |
| 499 | */ | |
| 500 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
| 501 | ||
| 502 | /* Cache Configuration */ | |
| 503 | #define CFG_DCACHE_SIZE 32768 | |
| 504 | #define CFG_CACHELINE_SIZE 32 | |
| 505 | #if defined(CONFIG_CMD_KGDB) | |
| 506 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ | |
| 507 | #endif | |
| 508 | ||
| 509 | /* | |
| 510 | * Internal Definitions | |
| 511 | * | |
| 512 | * Boot Flags | |
| 513 | */ | |
| 514 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 515 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 516 | ||
| 517 | #if defined(CONFIG_CMD_KGDB) | |
| 518 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 519 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 520 | #endif | |
| 521 | ||
| 522 | /* | |
| 523 | * Environment Configuration | |
| 524 | */ | |
| 525 | #define CONFIG_IPADDR 192.168.1.100 | |
| 526 | ||
| 527 | #define CONFIG_HOSTNAME unknown | |
| 528 | #define CONFIG_ROOTPATH /opt/nfsroot | |
| 529 | #define CONFIG_BOOTFILE uImage | |
| 530 | #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin | |
| 531 | ||
| 532 | #define CONFIG_SERVERIP 192.168.1.1 | |
| 533 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
| 534 | #define CONFIG_NETMASK 255.255.255.0 | |
| 535 | ||
| 536 | /* default location for tftp and bootm */ | |
| 537 | #define CONFIG_LOADADDR 1000000 | |
| 538 | ||
| 539 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 540 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 541 | ||
| 542 | #define CONFIG_BAUDRATE 115200 | |
| 543 | ||
| 544 | #if defined(CONFIG_PCI1) | |
| 545 | #define PCI_ENV \ | |
| 546 | "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ | |
| 547 | "echo e;md ${a}e00 9\0" \ | |
| 548 | "pci1regs=setenv a e0008; run pcireg\0" \ | |
| 549 | "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ | |
| 550 | "pci d.w $b.0 56 1\0" \ | |
| 551 | "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ | |
| 552 | "pci w.w $b.0 56 ffff\0" \ | |
| 553 | "pci1err=setenv a e0008; run pcierr\0" \ | |
| 554 | "pci1errc=setenv a e0008; run pcierrc\0" | |
| 555 | #else | |
| 556 | #define PCI_ENV "" | |
| 557 | #endif | |
| 558 | ||
| 559 | #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) | |
| 560 | #define PCIE_ENV \ | |
| 561 | "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ | |
| 562 | "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ | |
| 563 | "pcie1regs=setenv a e000a; run pciereg\0" \ | |
| 564 | "pcie2regs=setenv a e0009; run pciereg\0" \ | |
| 565 | "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ | |
| 566 | "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ | |
| 567 | "pci d $b.0 130 1\0" \ | |
| 568 | "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ | |
| 569 | "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ | |
| 570 | "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ | |
| 571 | "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ | |
| 572 | "pcie1err=setenv a e000a; run pcieerr\0" \ | |
| 573 | "pcie2err=setenv a e0009; run pcieerr\0" \ | |
| 574 | "pcie1errc=setenv a e000a; run pcieerrc\0" \ | |
| 575 | "pcie2errc=setenv a e0009; run pcieerrc\0" | |
| 576 | #else | |
| 577 | #define PCIE_ENV "" | |
| 578 | #endif | |
| 579 | ||
| 580 | #define DMA_ENV \ | |
| 581 | "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ | |
| 582 | "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ | |
| 583 | "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ | |
| 584 | "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ | |
| 585 | "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ | |
| 586 | "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ | |
| 587 | "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ | |
| 588 | "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" | |
| 589 | ||
| 590 | ||
| 591 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 592 | "netdev=eth0\0" \ | |
| 593 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 594 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 595 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 596 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 597 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
| 598 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 599 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
| 600 | "consoledev=ttyS0\0" \ | |
| 601 | "ramdiskaddr=2000000\0" \ | |
| 602 | "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ | |
| 603 | "dtbaddr=c00000\0" \ | |
| 604 | "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0" \ | |
| 605 | "bdev=sda3\0" \ | |
| 606 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ | |
| 607 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ | |
| 608 | "maxcpus=1" \ | |
| 609 | "eoi=mw e00400b0 0\0" \ | |
| 610 | "iack=md e00400a0 1\0" \ | |
| 611 | "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ | |
| 612 | "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ | |
| 613 | "md ${a}f00 5\0" \ | |
| 614 | "ddr1regs=setenv a e0002; run ddrreg\0" \ | |
| 615 | "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ | |
| 616 | "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ | |
| 617 | "md ${a}e60 1; md ${a}ef0 1d\0" \ | |
| 618 | "guregs=setenv a e00e0; run gureg\0" \ | |
| 619 | "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ | |
| 620 | "mcmregs=setenv a e0001; run mcmreg\0" \ | |
| 621 | "diuregs=md e002c000 1d\0" \ | |
| 622 | "dium=mw e002c01c\0" \ | |
| 623 | "diuerr=md e002c014 1\0" \ | |
| 624 | "othbootargs=debug\0" \ | |
| 625 | "pmregs=md e00e1000 2b\0" \ | |
| 626 | "lawregs=md e0000c08 4b\0" \ | |
| 627 | "lbcregs=md e0005000 36\0" \ | |
| 628 | "dma0regs=md e0021100 12\0" \ | |
| 629 | "dma1regs=md e0021180 12\0" \ | |
| 630 | "dma2regs=md e0021200 12\0" \ | |
| 631 | "dma3regs=md e0021280 12\0" \ | |
| 632 | PCI_ENV \ | |
| 633 | PCIE_ENV \ | |
| 634 | DMA_ENV | |
| 635 | ||
| 636 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 637 | "setenv bootargs root=/dev/nfs rw " \ | |
| 638 | "nfsroot=$serverip:$rootpath " \ | |
| 639 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 640 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 641 | "tftp $loadaddr $bootfile;" \ | |
| 642 | "tftp $dtbaddr $dtbfile;" \ | |
| 643 | "bootm $loadaddr - $dtbaddr" | |
| 644 | ||
| 645 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 646 | "setenv bootargs root=/dev/ram rw " \ | |
| 647 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 648 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 649 | "tftp $loadaddr $bootfile;" \ | |
| 650 | "tftp $dtbaddr $dtbfile;" \ | |
| 651 | "bootm $loadaddr $ramdiskaddr $dtbaddr" | |
| 652 | ||
| 653 | #define CONFIG_BOOTCOMMAND \ | |
| 654 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 655 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 656 | "tftp $loadaddr $bootfile;" \ | |
| 657 | "tftp $dtbaddr $dtbfile;" \ | |
| 658 | "bootm $loadaddr - $dtbaddr" | |
| 659 | ||
| 660 | #endif /* __CONFIG_H */ |