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5c9efb36 | 1 | /* |
1b77ca8a | 2 | * Copyright 2006, 2010-2011 Freescale Semiconductor. |
5c9efb36 | 3 | * |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
debb7354 JL |
7 | */ |
8 | ||
9 | /* | |
5c9efb36 | 10 | * MPC8641HPCN board configuration file |
debb7354 JL |
11 | * |
12 | * Make sure you change the MAC address and other network params first, | |
92ac5208 | 13 | * search for CONFIG_SERVERIP, etc. in this file. |
debb7354 JL |
14 | */ |
15 | ||
16 | #ifndef __CONFIG_H | |
17 | #define __CONFIG_H | |
18 | ||
19 | /* High Level Configuration Options */ | |
debb7354 JL |
20 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ |
21 | #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ | |
7649a590 | 22 | #define CONFIG_MP 1 /* support multiple processors */ |
53677ef1 | 23 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
d591a80e | 24 | #define CONFIG_ADDR_MAP 1 /* Use addr map */ |
debb7354 | 25 | |
2ae18241 WD |
26 | /* |
27 | * default CCSRBAR is at 0xff700000 | |
28 | * assume U-Boot is less than 0.5MB | |
29 | */ | |
30 | #define CONFIG_SYS_TEXT_BASE 0xeff00000 | |
31 | ||
debb7354 | 32 | #ifdef RUN_DIAG |
6bf98b13 | 33 | #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE |
debb7354 | 34 | #endif |
5c9efb36 | 35 | |
1266df88 BB |
36 | /* |
37 | * virtual address to be used for temporary mappings. There | |
38 | * should be 128k free at this VA. | |
39 | */ | |
40 | #define CONFIG_SYS_SCRATCH_VA 0xe0000000 | |
41 | ||
1b77ca8a KG |
42 | #define CONFIG_SYS_SRIO |
43 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
af5d100e | 44 | |
63cec581 | 45 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
b38eaec5 RD |
46 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ |
47 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ | |
63cec581 | 48 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
8ba93f68 | 49 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
4933b91f | 50 | #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ |
5c9efb36 | 51 | |
53677ef1 | 52 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
debb7354 | 53 | #define CONFIG_ENV_OVERWRITE |
debb7354 | 54 | |
4bbfd3e2 | 55 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
31d82672 | 56 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
d591a80e | 57 | #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ |
debb7354 | 58 | |
53677ef1 | 59 | #define CONFIG_ALTIVEC 1 |
debb7354 | 60 | |
5c9efb36 | 61 | /* |
debb7354 JL |
62 | * L2CR setup -- make sure this is right for your board! |
63 | */ | |
6d0f6bcf | 64 | #define CONFIG_SYS_L2 |
debb7354 JL |
65 | #define L2_INIT 0 |
66 | #define L2_ENABLE (L2CR_L2E) | |
67 | ||
68 | #ifndef CONFIG_SYS_CLK_FREQ | |
63cec581 ES |
69 | #ifndef __ASSEMBLY__ |
70 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
71 | #endif | |
53677ef1 | 72 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
debb7354 JL |
73 | #endif |
74 | ||
6d0f6bcf JCPV |
75 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
76 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
debb7354 | 77 | |
3111d32c BB |
78 | /* |
79 | * With the exception of PCI Memory and Rapid IO, most devices will simply | |
80 | * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA | |
81 | * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. | |
82 | */ | |
83 | #ifdef CONFIG_PHYS_64BIT | |
1605cc9e | 84 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f |
3111d32c | 85 | #else |
1605cc9e | 86 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 |
3111d32c BB |
87 | #endif |
88 | ||
debb7354 JL |
89 | /* |
90 | * Base addresses -- Note these are effective addresses where the | |
91 | * actual resources get mapped (not physical addresses) | |
92 | */ | |
6d0f6bcf | 93 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
c759a01a | 94 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
6d0f6bcf | 95 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
debb7354 | 96 | |
3111d32c BB |
97 | /* Physical addresses */ |
98 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
1605cc9e BB |
99 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH |
100 | #define CONFIG_SYS_CCSRBAR_PHYS \ | |
101 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ | |
102 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) | |
3111d32c | 103 | |
076bff8f YS |
104 | #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ |
105 | ||
debb7354 JL |
106 | /* |
107 | * DDR Setup | |
108 | */ | |
5614e71b | 109 | #define CONFIG_SYS_FSL_DDR2 |
6a8e5692 KG |
110 | #undef CONFIG_FSL_DDR_INTERACTIVE |
111 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
112 | #define CONFIG_DDR_SPD | |
113 | ||
114 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
115 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
116 | ||
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
118 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
1266df88 | 119 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
fcb28e76 | 120 | #define CONFIG_VERY_BIG_RAM |
debb7354 | 121 | |
6a8e5692 KG |
122 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
123 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
124 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
125 | ||
126 | /* | |
127 | * I2C addresses of SPD EEPROMs | |
128 | */ | |
129 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ | |
130 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ | |
131 | #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ | |
132 | #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ | |
133 | ||
6a8e5692 KG |
134 | /* |
135 | * These are used when DDR doesn't use SPD. | |
136 | */ | |
6d0f6bcf JCPV |
137 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
138 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F | |
139 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
140 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
141 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
142 | #define CONFIG_SYS_DDR_TIMING_1 0x39357322 | |
143 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
144 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
145 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
146 | #define CONFIG_SYS_DDR_INTERVAL 0x06090100 | |
147 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
148 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
149 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
150 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
151 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
152 | #define CONFIG_SYS_DDR_CONTROL2 0x04400000 | |
6a8e5692 | 153 | |
ad8f8687 | 154 | #define CONFIG_ID_EEPROM |
6d0f6bcf | 155 | #define CONFIG_SYS_I2C_EEPROM_NXID |
32628c50 | 156 | #define CONFIG_ID_EEPROM |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
158 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
debb7354 | 159 | |
c759a01a | 160 | #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ |
1605cc9e BB |
161 | #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE |
162 | #define CONFIG_SYS_FLASH_BASE_PHYS \ | |
163 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ | |
164 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
3111d32c | 165 | |
b81b773e | 166 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
debb7354 | 167 | |
3111d32c BB |
168 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
169 | | 0x00001001) /* port size 16bit */ | |
170 | #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ | |
debb7354 | 171 | |
3111d32c BB |
172 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ |
173 | | 0x00001001) /* port size 16bit */ | |
174 | #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ | |
debb7354 | 175 | |
3111d32c BB |
176 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ |
177 | | 0x00000801) /* port size 8bit */ | |
178 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ | |
debb7354 | 179 | |
c759a01a BB |
180 | /* |
181 | * The LBC_BASE is the base of the region that contains the PIXIS and the CF. | |
182 | * The PIXIS and CF by themselves aren't large enough to take up the 128k | |
183 | * required for the smallest BAT mapping, so there's a 64k hole. | |
184 | */ | |
185 | #define CONFIG_SYS_LBC_BASE 0xffde0000 | |
1605cc9e | 186 | #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE |
debb7354 | 187 | |
7608d75f | 188 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
c759a01a | 189 | #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) |
1605cc9e BB |
190 | #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) |
191 | #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ | |
192 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
c759a01a | 193 | #define PIXIS_SIZE 0x00008000 /* 32k */ |
5c9efb36 JL |
194 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
195 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
196 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
197 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
198 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
199 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
200 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
201 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
202 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
203 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
9af9c6bd KG |
204 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
205 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
5c9efb36 JL |
206 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
207 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
208 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
209 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
6d0f6bcf | 210 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
debb7354 | 211 | |
b5431560 | 212 | /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ |
c759a01a | 213 | #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) |
3111d32c | 214 | #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) |
b5431560 | 215 | |
170deacb | 216 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
6d0f6bcf | 217 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
debb7354 | 218 | |
6d0f6bcf JCPV |
219 | #undef CONFIG_SYS_FLASH_CHECKSUM |
220 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
221 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
14d0a02a | 222 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
bf9a8c34 | 223 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
debb7354 | 224 | |
00b1883a | 225 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_FLASH_CFI |
227 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
debb7354 | 228 | |
6d0f6bcf JCPV |
229 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
230 | #define CONFIG_SYS_RAMBOOT | |
debb7354 | 231 | #else |
6d0f6bcf | 232 | #undef CONFIG_SYS_RAMBOOT |
debb7354 JL |
233 | #endif |
234 | ||
6d0f6bcf | 235 | #if defined(CONFIG_SYS_RAMBOOT) |
fa7db9c3 | 236 | #undef CONFIG_SPD_EEPROM |
6d0f6bcf | 237 | #define CONFIG_SYS_SDRAM_SIZE 256 |
debb7354 JL |
238 | #endif |
239 | ||
240 | #undef CONFIG_CLOCKS_IN_MHZ | |
241 | ||
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
243 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
244 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
debb7354 | 245 | #else |
6d0f6bcf | 246 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
debb7354 | 247 | #endif |
553f0982 | 248 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
debb7354 | 249 | |
25ddd1fb | 250 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 251 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
debb7354 | 252 | |
221fbd22 | 253 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
6d0f6bcf | 254 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
debb7354 JL |
255 | |
256 | /* Serial Port */ | |
257 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_NS16550_SERIAL |
259 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
260 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
debb7354 | 261 | |
6d0f6bcf | 262 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
debb7354 JL |
263 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
264 | ||
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
266 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
debb7354 | 267 | |
586d1d5a JL |
268 | /* |
269 | * I2C | |
270 | */ | |
00f792e0 HS |
271 | #define CONFIG_SYS_I2C |
272 | #define CONFIG_SYS_I2C_FSL | |
273 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
274 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
275 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 | |
276 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
debb7354 | 277 | |
586d1d5a JL |
278 | /* |
279 | * RapidIO MMU | |
280 | */ | |
1b77ca8a | 281 | #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ |
3111d32c | 282 | #ifdef CONFIG_PHYS_64BIT |
1605cc9e BB |
283 | #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 |
284 | #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c | |
3111d32c | 285 | #else |
1605cc9e BB |
286 | #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE |
287 | #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 | |
3111d32c | 288 | #endif |
1605cc9e BB |
289 | #define CONFIG_SYS_SRIO1_MEM_PHYS \ |
290 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ | |
291 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) | |
1b77ca8a | 292 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ |
debb7354 JL |
293 | |
294 | /* | |
295 | * General PCI | |
296 | * Addresses are mapped 1-1. | |
297 | */ | |
49f46f3b | 298 | |
64e55d5e | 299 | #define CONFIG_SYS_PCIE1_NAME "ULI" |
46f3e385 | 300 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
3111d32c | 301 | #ifdef CONFIG_PHYS_64BIT |
46f3e385 | 302 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
1605cc9e BB |
303 | #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 |
304 | #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c | |
3111d32c | 305 | #else |
46f3e385 | 306 | #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT |
1605cc9e BB |
307 | #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT |
308 | #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 | |
3111d32c | 309 | #endif |
1605cc9e BB |
310 | #define CONFIG_SYS_PCIE1_MEM_PHYS \ |
311 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ | |
312 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) | |
46f3e385 KG |
313 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
314 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
315 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
1605cc9e BB |
316 | #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT |
317 | #define CONFIG_SYS_PCIE1_IO_PHYS \ | |
318 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ | |
319 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
46f3e385 | 320 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ |
debb7354 | 321 | |
4c78d4a6 BB |
322 | #ifdef CONFIG_PHYS_64BIT |
323 | /* | |
46f3e385 | 324 | * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. |
4c78d4a6 BB |
325 | * This will increase the amount of PCI address space available for |
326 | * for mapping RAM. | |
327 | */ | |
46f3e385 | 328 | #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS |
4c78d4a6 | 329 | #else |
46f3e385 KG |
330 | #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ |
331 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
4c78d4a6 | 332 | #endif |
46f3e385 KG |
333 | #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ |
334 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
1605cc9e BB |
335 | #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ |
336 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
337 | #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH | |
46f3e385 KG |
338 | #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ |
339 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
340 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
341 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
342 | #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ | |
343 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
1605cc9e BB |
344 | #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ |
345 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
46f3e385 KG |
346 | #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ |
347 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
348 | #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE | |
debb7354 | 349 | |
debb7354 JL |
350 | #if defined(CONFIG_PCI) |
351 | ||
53677ef1 | 352 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
debb7354 | 353 | |
53677ef1 | 354 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
debb7354 | 355 | |
debb7354 JL |
356 | #undef CONFIG_EEPRO100 |
357 | #undef CONFIG_TULIP | |
358 | ||
a81d1c0b ZW |
359 | /************************************************************ |
360 | * USB support | |
361 | ************************************************************/ | |
53677ef1 | 362 | #define CONFIG_PCI_OHCI 1 |
a81d1c0b | 363 | #define CONFIG_USB_OHCI_NEW 1 |
6d0f6bcf JCPV |
364 | #define CONFIG_SYS_USB_EVENT_POLL 1 |
365 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
366 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
367 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
a81d1c0b | 368 | |
0f460a1e | 369 | /*PCIE video card used*/ |
46f3e385 | 370 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
0f460a1e JJ |
371 | |
372 | /*PCI video card used*/ | |
46f3e385 | 373 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ |
0f460a1e JJ |
374 | |
375 | /* video */ | |
0f460a1e JJ |
376 | |
377 | #if defined(CONFIG_VIDEO) | |
378 | #define CONFIG_BIOSEMU | |
0f460a1e JJ |
379 | #define CONFIG_ATI_RADEON_FB |
380 | #define CONFIG_VIDEO_LOGO | |
46f3e385 | 381 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT |
0f460a1e JJ |
382 | #endif |
383 | ||
debb7354 | 384 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
debb7354 | 385 | |
dabf9ef8 JZ |
386 | #define CONFIG_DOS_PARTITION |
387 | #define CONFIG_SCSI_AHCI | |
388 | ||
389 | #ifdef CONFIG_SCSI_AHCI | |
344ca0b4 | 390 | #define CONFIG_LIBATA |
dabf9ef8 | 391 | #define CONFIG_SATA_ULI5288 |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
393 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
394 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
395 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
dabf9ef8 JZ |
396 | #endif |
397 | ||
debb7354 JL |
398 | #endif /* CONFIG_PCI */ |
399 | ||
debb7354 JL |
400 | #if defined(CONFIG_TSEC_ENET) |
401 | ||
debb7354 JL |
402 | #define CONFIG_MII 1 /* MII PHY management */ |
403 | ||
53677ef1 WD |
404 | #define CONFIG_TSEC1 1 |
405 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
406 | #define CONFIG_TSEC2 1 | |
407 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
408 | #define CONFIG_TSEC3 1 | |
409 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
410 | #define CONFIG_TSEC4 1 | |
411 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
debb7354 | 412 | |
debb7354 JL |
413 | #define TSEC1_PHY_ADDR 0 |
414 | #define TSEC2_PHY_ADDR 1 | |
415 | #define TSEC3_PHY_ADDR 2 | |
416 | #define TSEC4_PHY_ADDR 3 | |
417 | #define TSEC1_PHYIDX 0 | |
418 | #define TSEC2_PHYIDX 0 | |
419 | #define TSEC3_PHYIDX 0 | |
420 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
421 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
422 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
423 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
424 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
debb7354 JL |
425 | |
426 | #define CONFIG_ETHPRIME "eTSEC1" | |
427 | ||
428 | #endif /* CONFIG_TSEC_ENET */ | |
429 | ||
1605cc9e | 430 | #ifdef CONFIG_PHYS_64BIT |
3111d32c BB |
431 | #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) |
432 | #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) | |
433 | ||
1605cc9e BB |
434 | /* Put physical address into the BAT format */ |
435 | #define BAT_PHYS_ADDR(low, high) \ | |
436 | (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) | |
437 | /* Convert high/low pairs to actual 64-bit value */ | |
438 | #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) | |
439 | #else | |
440 | /* 32-bit systems just ignore the "high" bits */ | |
441 | #define BAT_PHYS_ADDR(low, high) (low) | |
442 | #define PAIRED_PHYS_TO_PHYS(low, high) (low) | |
443 | #endif | |
444 | ||
586d1d5a | 445 | /* |
c759a01a | 446 | * BAT0 DDR |
debb7354 | 447 | */ |
6d0f6bcf | 448 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
9ff32d8c | 449 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
debb7354 | 450 | |
586d1d5a | 451 | /* |
c759a01a | 452 | * BAT1 LBC (PIXIS/CF) |
af5d100e | 453 | */ |
1605cc9e BB |
454 | #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ |
455 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c BB |
456 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
457 | BATL_GUARDEDSTORAGE) | |
c759a01a BB |
458 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ |
459 | | BATU_VS | BATU_VP) | |
1605cc9e BB |
460 | #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ |
461 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c | 462 | | BATL_PP_RW | BATL_MEMCOHERENCE) |
c759a01a | 463 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
af5d100e BB |
464 | |
465 | /* if CONFIG_PCI: | |
46f3e385 | 466 | * BAT2 PCIE1 and PCIE1 MEM |
af5d100e | 467 | * if CONFIG_RIO |
c759a01a | 468 | * BAT2 Rapidio Memory |
debb7354 | 469 | */ |
af5d100e | 470 | #ifdef CONFIG_PCI |
842033e6 | 471 | #define CONFIG_PCI_INDIRECT_BRIDGE |
1605cc9e BB |
472 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ |
473 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | |
3111d32c BB |
474 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
475 | | BATL_GUARDEDSTORAGE) | |
46f3e385 | 476 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ |
af5d100e | 477 | | BATU_VS | BATU_VP) |
1605cc9e BB |
478 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ |
479 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | |
3111d32c | 480 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
af5d100e BB |
481 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
482 | #else /* CONFIG_RIO */ | |
1605cc9e BB |
483 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ |
484 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | |
3111d32c BB |
485 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
486 | BATL_GUARDEDSTORAGE) | |
1b77ca8a | 487 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ |
3111d32c | 488 | | BATU_VS | BATU_VP) |
1605cc9e BB |
489 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ |
490 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | |
3111d32c | 491 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
6d0f6bcf | 492 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
af5d100e | 493 | #endif |
debb7354 | 494 | |
586d1d5a | 495 | /* |
c759a01a | 496 | * BAT3 CCSR Space |
debb7354 | 497 | */ |
1605cc9e BB |
498 | #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ |
499 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
3111d32c BB |
500 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
501 | | BATL_GUARDEDSTORAGE) | |
c759a01a BB |
502 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ |
503 | | BATU_VP) | |
1605cc9e BB |
504 | #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ |
505 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
3111d32c | 506 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
6d0f6bcf | 507 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
debb7354 | 508 | |
3111d32c BB |
509 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
510 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
511 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
512 | | BATL_GUARDEDSTORAGE) | |
513 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
514 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
515 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
516 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
517 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
518 | #endif | |
519 | ||
586d1d5a | 520 | /* |
46f3e385 | 521 | * BAT4 PCIE1_IO and PCIE2_IO |
debb7354 | 522 | */ |
1605cc9e BB |
523 | #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ |
524 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c BB |
525 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
526 | | BATL_GUARDEDSTORAGE) | |
46f3e385 | 527 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ |
c759a01a | 528 | | BATU_VS | BATU_VP) |
1605cc9e BB |
529 | #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ |
530 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c | 531 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
6d0f6bcf | 532 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
debb7354 | 533 | |
586d1d5a | 534 | /* |
c759a01a | 535 | * BAT5 Init RAM for stack in the CPU DCache (no backing memory) |
debb7354 | 536 | */ |
6d0f6bcf JCPV |
537 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
538 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
539 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
540 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
debb7354 | 541 | |
586d1d5a | 542 | /* |
c759a01a | 543 | * BAT6 FLASH |
debb7354 | 544 | */ |
1605cc9e BB |
545 | #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ |
546 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c BB |
547 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
548 | | BATL_GUARDEDSTORAGE) | |
170deacb BB |
549 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ |
550 | | BATU_VP) | |
1605cc9e BB |
551 | #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ |
552 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c | 553 | | BATL_PP_RW | BATL_MEMCOHERENCE) |
6d0f6bcf | 554 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
debb7354 | 555 | |
bf9a8c34 BB |
556 | /* Map the last 1M of flash where we're running from reset */ |
557 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
558 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
14d0a02a | 559 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
bf9a8c34 BB |
560 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
561 | | BATL_MEMCOHERENCE) | |
562 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
563 | ||
c759a01a BB |
564 | /* |
565 | * BAT7 FREE - used later for tmp mappings | |
566 | */ | |
6d0f6bcf JCPV |
567 | #define CONFIG_SYS_DBAT7L 0x00000000 |
568 | #define CONFIG_SYS_DBAT7U 0x00000000 | |
569 | #define CONFIG_SYS_IBAT7L 0x00000000 | |
570 | #define CONFIG_SYS_IBAT7U 0x00000000 | |
debb7354 | 571 | |
debb7354 JL |
572 | /* |
573 | * Environment | |
574 | */ | |
6d0f6bcf | 575 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 576 | #define CONFIG_ENV_IS_IN_FLASH 1 |
221fbd22 SW |
577 | #define CONFIG_ENV_ADDR \ |
578 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 | 579 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
5c9efb36 | 580 | #else |
93f6d725 | 581 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 582 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
5c9efb36 | 583 | #endif |
0f2d6602 | 584 | #define CONFIG_ENV_SIZE 0x2000 |
debb7354 JL |
585 | |
586 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 587 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
debb7354 | 588 | |
659e2f67 JL |
589 | /* |
590 | * BOOTP options | |
591 | */ | |
592 | #define CONFIG_BOOTP_BOOTFILESIZE | |
593 | #define CONFIG_BOOTP_BOOTPATH | |
594 | #define CONFIG_BOOTP_GATEWAY | |
595 | #define CONFIG_BOOTP_HOSTNAME | |
596 | ||
2f9c19e4 JL |
597 | /* |
598 | * Command line configuration. | |
599 | */ | |
4f93f8b1 | 600 | #define CONFIG_CMD_REGINFO |
2f9c19e4 | 601 | |
2f9c19e4 JL |
602 | #if defined(CONFIG_PCI) |
603 | #define CONFIG_CMD_PCI | |
c649e3c9 | 604 | #define CONFIG_SCSI |
debb7354 JL |
605 | #endif |
606 | ||
debb7354 JL |
607 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
608 | ||
609 | /* | |
610 | * Miscellaneous configurable options | |
611 | */ | |
6d0f6bcf | 612 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
53677ef1 | 613 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
6d0f6bcf | 614 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
debb7354 | 615 | |
2f9c19e4 | 616 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 617 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
debb7354 | 618 | #else |
6d0f6bcf | 619 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
debb7354 JL |
620 | #endif |
621 | ||
6d0f6bcf JCPV |
622 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
623 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
624 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
debb7354 JL |
625 | |
626 | /* | |
627 | * For booting Linux, the board info and command line data | |
628 | * have to be in the first 8 MB of memory, since this is | |
629 | * the maximum mapped by the Linux kernel during initialization. | |
630 | */ | |
e1efe43c SW |
631 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
632 | #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ | |
debb7354 | 633 | |
2f9c19e4 JL |
634 | #if defined(CONFIG_CMD_KGDB) |
635 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
debb7354 JL |
636 | #endif |
637 | ||
debb7354 JL |
638 | /* |
639 | * Environment Configuration | |
640 | */ | |
641 | ||
10327dc5 | 642 | #define CONFIG_HAS_ETH0 1 |
5c9efb36 JL |
643 | #define CONFIG_HAS_ETH1 1 |
644 | #define CONFIG_HAS_ETH2 1 | |
645 | #define CONFIG_HAS_ETH3 1 | |
debb7354 | 646 | |
18b6c8cd | 647 | #define CONFIG_IPADDR 192.168.1.100 |
debb7354 JL |
648 | |
649 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 650 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 651 | #define CONFIG_BOOTFILE "uImage" |
32922cdc | 652 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
debb7354 | 653 | |
5c9efb36 | 654 | #define CONFIG_SERVERIP 192.168.1.1 |
18b6c8cd | 655 | #define CONFIG_GATEWAYIP 192.168.1.1 |
5c9efb36 | 656 | #define CONFIG_NETMASK 255.255.255.0 |
debb7354 | 657 | |
5c9efb36 | 658 | /* default location for tftp and bootm */ |
e1efe43c | 659 | #define CONFIG_LOADADDR 0x10000000 |
debb7354 | 660 | |
53677ef1 | 661 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
debb7354 JL |
662 | |
663 | #define CONFIG_BAUDRATE 115200 | |
664 | ||
53677ef1 WD |
665 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
666 | "netdev=eth0\0" \ | |
5368c55d | 667 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
53677ef1 | 668 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
669 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
670 | " +$filesize; " \ | |
671 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
672 | " +$filesize; " \ | |
673 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
674 | " $filesize; " \ | |
675 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
676 | " +$filesize; " \ | |
677 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
678 | " $filesize\0" \ | |
53677ef1 | 679 | "consoledev=ttyS0\0" \ |
e1efe43c | 680 | "ramdiskaddr=0x18000000\0" \ |
53677ef1 | 681 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
e1efe43c | 682 | "fdtaddr=0x17c00000\0" \ |
53677ef1 | 683 | "fdtfile=mpc8641_hpcn.dtb\0" \ |
3111d32c BB |
684 | "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ |
685 | "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ | |
53677ef1 WD |
686 | "maxcpus=2" |
687 | ||
53677ef1 WD |
688 | #define CONFIG_NFSBOOTCOMMAND \ |
689 | "setenv bootargs root=/dev/nfs rw " \ | |
690 | "nfsroot=$serverip:$rootpath " \ | |
691 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
692 | "console=$consoledev,$baudrate $othbootargs;" \ | |
693 | "tftp $loadaddr $bootfile;" \ | |
694 | "tftp $fdtaddr $fdtfile;" \ | |
695 | "bootm $loadaddr - $fdtaddr" | |
696 | ||
697 | #define CONFIG_RAMBOOTCOMMAND \ | |
698 | "setenv bootargs root=/dev/ram rw " \ | |
699 | "console=$consoledev,$baudrate $othbootargs;" \ | |
700 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
701 | "tftp $loadaddr $bootfile;" \ | |
702 | "tftp $fdtaddr $fdtfile;" \ | |
703 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
debb7354 JL |
704 | |
705 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
706 | ||
707 | #endif /* __CONFIG_H */ |