projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5c9efb36 JL |
1 | /* |
| 2 | * Copyright 2006 Freescale Semiconductor. | |
| 3 | * | |
| debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
| 5 | * | |
| 6 | * See file CREDITS for list of people who contributed to this | |
| 7 | * project. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of | |
| 12 | * the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 22 | * MA 02111-1307 USA | |
| 23 | */ | |
| 24 | ||
| 25 | /* | |
| 5c9efb36 | 26 | * MPC8641HPCN board configuration file |
| debb7354 JL |
27 | * |
| 28 | * Make sure you change the MAC address and other network params first, | |
| 29 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
| 30 | */ | |
| 31 | ||
| 32 | #ifndef __CONFIG_H | |
| 33 | #define __CONFIG_H | |
| 34 | ||
| 35 | /* High Level Configuration Options */ | |
| 36 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
| 37 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ | |
| 38 | #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ | |
| 53677ef1 WD |
39 | #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ |
| 40 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ | |
| 3111d32c | 41 | /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ |
| debb7354 | 42 | |
| debb7354 | 43 | #ifdef RUN_DIAG |
| 6bf98b13 | 44 | #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE |
| debb7354 | 45 | #endif |
| 5c9efb36 | 46 | |
| 6d0f6bcf | 47 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
| debb7354 | 48 | |
| 1266df88 BB |
49 | /* |
| 50 | * virtual address to be used for temporary mappings. There | |
| 51 | * should be 128k free at this VA. | |
| 52 | */ | |
| 53 | #define CONFIG_SYS_SCRATCH_VA 0xe0000000 | |
| 54 | ||
| af5d100e BB |
55 | /* |
| 56 | * set this to enable Rapid IO. PCI and RIO are mutually exclusive | |
| 57 | */ | |
| 58 | /*#define CONFIG_RIO 1*/ | |
| 59 | ||
| 60 | #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ | |
| 63cec581 ES |
61 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 62 | #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ | |
| 63 | #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ | |
| 64 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 8ba93f68 | 65 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| af5d100e | 66 | #endif |
| 4933b91f | 67 | #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ |
| 5c9efb36 | 68 | |
| 53677ef1 | 69 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| debb7354 | 70 | #define CONFIG_ENV_OVERWRITE |
| debb7354 | 71 | |
| 31d82672 | 72 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
| debb7354 | 73 | |
| 53677ef1 | 74 | #define CONFIG_ALTIVEC 1 |
| debb7354 | 75 | |
| 5c9efb36 | 76 | /* |
| debb7354 JL |
77 | * L2CR setup -- make sure this is right for your board! |
| 78 | */ | |
| 6d0f6bcf | 79 | #define CONFIG_SYS_L2 |
| debb7354 JL |
80 | #define L2_INIT 0 |
| 81 | #define L2_ENABLE (L2CR_L2E) | |
| 82 | ||
| 83 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 63cec581 ES |
84 | #ifndef __ASSEMBLY__ |
| 85 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 86 | #endif | |
| 53677ef1 | 87 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
| debb7354 JL |
88 | #endif |
| 89 | ||
| debb7354 JL |
90 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
| 91 | ||
| 6d0f6bcf JCPV |
92 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 93 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| debb7354 | 94 | |
| 3111d32c BB |
95 | /* |
| 96 | * With the exception of PCI Memory and Rapid IO, most devices will simply | |
| 97 | * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA | |
| 98 | * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. | |
| 99 | */ | |
| 100 | #ifdef CONFIG_PHYS_64BIT | |
| 101 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL | |
| 102 | #else | |
| 103 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 | |
| 104 | #endif | |
| 105 | ||
| debb7354 JL |
106 | /* |
| 107 | * Base addresses -- Note these are effective addresses where the | |
| 108 | * actual resources get mapped (not physical addresses) | |
| 109 | */ | |
| 6d0f6bcf | 110 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| c759a01a | 111 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
| 6d0f6bcf | 112 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
| debb7354 | 113 | |
| 3111d32c BB |
114 | /* Physical addresses */ |
| 115 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 116 | #ifdef CONFIG_PHYS_64BIT | |
| 117 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf | |
| d52082b1 BB |
118 | #define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ |
| 119 | | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) | |
| 3111d32c BB |
120 | #else |
| 121 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 | |
| d52082b1 | 122 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW |
| 3111d32c BB |
123 | #endif |
| 124 | ||
| 6d0f6bcf JCPV |
125 | #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) |
| 126 | #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) | |
| 63cec581 | 127 | |
| debb7354 JL |
128 | /* |
| 129 | * DDR Setup | |
| 130 | */ | |
| 6a8e5692 KG |
131 | #define CONFIG_FSL_DDR2 |
| 132 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 133 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 134 | #define CONFIG_DDR_SPD | |
| 135 | ||
| 136 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
| 137 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 138 | ||
| 6d0f6bcf JCPV |
139 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 140 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 1266df88 | 141 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
| fcb28e76 | 142 | #define CONFIG_VERY_BIG_RAM |
| debb7354 JL |
143 | |
| 144 | #define MPC86xx_DDR_SDRAM_CLK_CNTL | |
| 145 | ||
| 6a8e5692 KG |
146 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 147 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
| 148 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 149 | ||
| 150 | /* | |
| 151 | * I2C addresses of SPD EEPROMs | |
| 152 | */ | |
| 153 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ | |
| 154 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ | |
| 155 | #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ | |
| 156 | #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ | |
| 157 | ||
| 158 | ||
| 159 | /* | |
| 160 | * These are used when DDR doesn't use SPD. | |
| 161 | */ | |
| 6d0f6bcf JCPV |
162 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
| 163 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F | |
| 164 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
| 165 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
| 166 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
| 167 | #define CONFIG_SYS_DDR_TIMING_1 0x39357322 | |
| 168 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
| 169 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
| 170 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
| 171 | #define CONFIG_SYS_DDR_INTERVAL 0x06090100 | |
| 172 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 173 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
| 174 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
| 175 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
| 176 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
| 177 | #define CONFIG_SYS_DDR_CONTROL2 0x04400000 | |
| 6a8e5692 | 178 | |
| ad8f8687 | 179 | #define CONFIG_ID_EEPROM |
| 6d0f6bcf | 180 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 32628c50 | 181 | #define CONFIG_ID_EEPROM |
| 6d0f6bcf JCPV |
182 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 183 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| debb7354 | 184 | |
| c759a01a | 185 | #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ |
| 3111d32c BB |
186 | #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ |
| 187 | | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| 188 | ||
| 170deacb | 189 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
| debb7354 | 190 | |
| 3111d32c BB |
191 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 192 | | 0x00001001) /* port size 16bit */ | |
| 193 | #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ | |
| debb7354 | 194 | |
| 3111d32c BB |
195 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ |
| 196 | | 0x00001001) /* port size 16bit */ | |
| 197 | #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ | |
| debb7354 | 198 | |
| 3111d32c BB |
199 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ |
| 200 | | 0x00000801) /* port size 8bit */ | |
| 201 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ | |
| debb7354 | 202 | |
| c759a01a BB |
203 | /* |
| 204 | * The LBC_BASE is the base of the region that contains the PIXIS and the CF. | |
| 205 | * The PIXIS and CF by themselves aren't large enough to take up the 128k | |
| 206 | * required for the smallest BAT mapping, so there's a 64k hole. | |
| 207 | */ | |
| 208 | #define CONFIG_SYS_LBC_BASE 0xffde0000 | |
| 3111d32c BB |
209 | #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ |
| 210 | | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| debb7354 | 211 | |
| 7608d75f | 212 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
| c759a01a | 213 | #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) |
| 3111d32c | 214 | #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) |
| c759a01a | 215 | #define PIXIS_SIZE 0x00008000 /* 32k */ |
| 5c9efb36 JL |
216 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 217 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 218 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 219 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 220 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
| 221 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 222 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 223 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 224 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 225 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 226 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
| 227 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 228 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 229 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 6d0f6bcf | 230 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
| debb7354 | 231 | |
| b5431560 | 232 | /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ |
| c759a01a | 233 | #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) |
| 3111d32c | 234 | #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) |
| b5431560 | 235 | |
| 170deacb | 236 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 6d0f6bcf | 237 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
| debb7354 | 238 | |
| 6d0f6bcf JCPV |
239 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 240 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 241 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| bf9a8c34 BB |
242 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 243 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ | |
| debb7354 | 244 | |
| 00b1883a | 245 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
246 | #define CONFIG_SYS_FLASH_CFI |
| 247 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| debb7354 | 248 | |
| 6d0f6bcf JCPV |
249 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 250 | #define CONFIG_SYS_RAMBOOT | |
| debb7354 | 251 | #else |
| 6d0f6bcf | 252 | #undef CONFIG_SYS_RAMBOOT |
| debb7354 JL |
253 | #endif |
| 254 | ||
| 6d0f6bcf | 255 | #if defined(CONFIG_SYS_RAMBOOT) |
| fa7db9c3 | 256 | #undef CONFIG_SPD_EEPROM |
| 6d0f6bcf | 257 | #define CONFIG_SYS_SDRAM_SIZE 256 |
| debb7354 JL |
258 | #endif |
| 259 | ||
| 260 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 261 | ||
| 6d0f6bcf JCPV |
262 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 263 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
| 264 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
| debb7354 | 265 | #else |
| 6d0f6bcf | 266 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
| debb7354 | 267 | #endif |
| 6d0f6bcf | 268 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
| debb7354 | 269 | |
| 6d0f6bcf JCPV |
270 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 271 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 272 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| debb7354 | 273 | |
| 6d0f6bcf JCPV |
274 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 275 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
| debb7354 JL |
276 | |
| 277 | /* Serial Port */ | |
| 278 | #define CONFIG_CONS_INDEX 1 | |
| 279 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 6d0f6bcf JCPV |
280 | #define CONFIG_SYS_NS16550 |
| 281 | #define CONFIG_SYS_NS16550_SERIAL | |
| 282 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 283 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| debb7354 | 284 | |
| 6d0f6bcf | 285 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| debb7354 JL |
286 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 287 | ||
| 6d0f6bcf JCPV |
288 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 289 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| debb7354 JL |
290 | |
| 291 | /* Use the HUSH parser */ | |
| 6d0f6bcf JCPV |
292 | #define CONFIG_SYS_HUSH_PARSER |
| 293 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 294 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| debb7354 JL |
295 | #endif |
| 296 | ||
| 5c9efb36 JL |
297 | /* |
| 298 | * Pass open firmware flat tree to kernel | |
| 299 | */ | |
| ea9f7395 JL |
300 | #define CONFIG_OF_LIBFDT 1 |
| 301 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 302 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| debb7354 | 303 | |
| debb7354 | 304 | |
| 6d0f6bcf JCPV |
305 | #define CONFIG_SYS_64BIT_VSPRINTF 1 |
| 306 | #define CONFIG_SYS_64BIT_STRTOUL 1 | |
| debb7354 | 307 | |
| 586d1d5a JL |
308 | /* |
| 309 | * I2C | |
| 310 | */ | |
| 20476726 JL |
311 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 312 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
| debb7354 | 313 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 6d0f6bcf JCPV |
314 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 315 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 316 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
| 317 | #define CONFIG_SYS_I2C_OFFSET 0x3100 | |
| debb7354 | 318 | |
| 586d1d5a JL |
319 | /* |
| 320 | * RapidIO MMU | |
| 321 | */ | |
| c759a01a | 322 | #define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ |
| 3111d32c BB |
323 | #ifdef CONFIG_PHYS_64BIT |
| 324 | #define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL | |
| 325 | #else | |
| 6d0f6bcf | 326 | #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE |
| 3111d32c | 327 | #endif |
| 6d0f6bcf | 328 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
| debb7354 JL |
329 | |
| 330 | /* | |
| 331 | * General PCI | |
| 332 | * Addresses are mapped 1-1. | |
| 333 | */ | |
| 6d0f6bcf | 334 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 3111d32c BB |
335 | #ifdef CONFIG_PHYS_64BIT |
| 336 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL | |
| 337 | #else | |
| 6d0f6bcf | 338 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
| 3111d32c | 339 | #endif |
| 6d0f6bcf JCPV |
340 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| 341 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
| 3111d32c BB |
342 | #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 |
| 343 | #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ | |
| 344 | | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| c759a01a | 345 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ |
| debb7354 JL |
346 | |
| 347 | /* For RTL8139 */ | |
| bc09cf3c | 348 | #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) |
| 53677ef1 | 349 | #define _IO_BASE 0x00000000 |
| debb7354 | 350 | |
| b5431560 BB |
351 | #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \ |
| 352 | + CONFIG_SYS_PCI1_MEM_SIZE) | |
| 3111d32c BB |
353 | #define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ |
| 354 | + CONFIG_SYS_PCI1_MEM_SIZE) | |
| 6d0f6bcf JCPV |
355 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
| 356 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 | |
| 3111d32c BB |
357 | #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ |
| 358 | + CONFIG_SYS_PCI1_IO_SIZE) | |
| b5431560 BB |
359 | #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ |
| 360 | + CONFIG_SYS_PCI1_IO_SIZE) | |
| c759a01a | 361 | #define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE |
| debb7354 | 362 | |
| debb7354 JL |
363 | #if defined(CONFIG_PCI) |
| 364 | ||
| 53677ef1 | 365 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| debb7354 | 366 | |
| 6d0f6bcf | 367 | #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE |
| debb7354 JL |
368 | |
| 369 | #define CONFIG_NET_MULTI | |
| 53677ef1 | 370 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| debb7354 JL |
371 | |
| 372 | #define CONFIG_RTL8139 | |
| 373 | ||
| debb7354 JL |
374 | #undef CONFIG_EEPRO100 |
| 375 | #undef CONFIG_TULIP | |
| 376 | ||
| a81d1c0b ZW |
377 | /************************************************************ |
| 378 | * USB support | |
| 379 | ************************************************************/ | |
| 53677ef1 | 380 | #define CONFIG_PCI_OHCI 1 |
| a81d1c0b | 381 | #define CONFIG_USB_OHCI_NEW 1 |
| 53677ef1 | 382 | #define CONFIG_USB_KEYBOARD 1 |
| 6d0f6bcf JCPV |
383 | #define CONFIG_SYS_DEVICE_DEREGISTER |
| 384 | #define CONFIG_SYS_USB_EVENT_POLL 1 | |
| 385 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
| 386 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
| 387 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
| a81d1c0b | 388 | |
| 0f460a1e | 389 | /*PCIE video card used*/ |
| 3111d32c | 390 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT |
| 0f460a1e JJ |
391 | |
| 392 | /*PCI video card used*/ | |
| 3111d32c | 393 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
| 0f460a1e JJ |
394 | |
| 395 | /* video */ | |
| 396 | #define CONFIG_VIDEO | |
| 397 | ||
| 398 | #if defined(CONFIG_VIDEO) | |
| 399 | #define CONFIG_BIOSEMU | |
| 400 | #define CONFIG_CFB_CONSOLE | |
| 401 | #define CONFIG_VIDEO_SW_CURSOR | |
| 402 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 403 | #define CONFIG_ATI_RADEON_FB | |
| 404 | #define CONFIG_VIDEO_LOGO | |
| 405 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
| 3111d32c | 406 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT |
| 0f460a1e JJ |
407 | #endif |
| 408 | ||
| debb7354 | 409 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| debb7354 | 410 | |
| dabf9ef8 JZ |
411 | #define CONFIG_DOS_PARTITION |
| 412 | #define CONFIG_SCSI_AHCI | |
| 413 | ||
| 414 | #ifdef CONFIG_SCSI_AHCI | |
| 415 | #define CONFIG_SATA_ULI5288 | |
| 6d0f6bcf JCPV |
416 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 417 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 418 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
| 419 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
| dabf9ef8 JZ |
420 | #endif |
| 421 | ||
| 0f460a1e JJ |
422 | #define CONFIG_MPC86XX_PCI2 |
| 423 | ||
| debb7354 JL |
424 | #endif /* CONFIG_PCI */ |
| 425 | ||
| debb7354 JL |
426 | #if defined(CONFIG_TSEC_ENET) |
| 427 | ||
| 428 | #ifndef CONFIG_NET_MULTI | |
| 53677ef1 | 429 | #define CONFIG_NET_MULTI 1 |
| debb7354 JL |
430 | #endif |
| 431 | ||
| 432 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 433 | ||
| 53677ef1 WD |
434 | #define CONFIG_TSEC1 1 |
| 435 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 436 | #define CONFIG_TSEC2 1 | |
| 437 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 438 | #define CONFIG_TSEC3 1 | |
| 439 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 440 | #define CONFIG_TSEC4 1 | |
| 441 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
| debb7354 | 442 | |
| debb7354 JL |
443 | #define TSEC1_PHY_ADDR 0 |
| 444 | #define TSEC2_PHY_ADDR 1 | |
| 445 | #define TSEC3_PHY_ADDR 2 | |
| 446 | #define TSEC4_PHY_ADDR 3 | |
| 447 | #define TSEC1_PHYIDX 0 | |
| 448 | #define TSEC2_PHYIDX 0 | |
| 449 | #define TSEC3_PHYIDX 0 | |
| 450 | #define TSEC4_PHYIDX 0 | |
| 3a79013e AF |
451 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 452 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 453 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 454 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| debb7354 JL |
455 | |
| 456 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 457 | ||
| 458 | #endif /* CONFIG_TSEC_ENET */ | |
| 459 | ||
| 3111d32c BB |
460 | /* Contort an addr into the format needed for BATs */ |
| 461 | #ifdef CONFIG_PHYS_64BIT | |
| 462 | #define BAT_PHYS_ADDR(x) ((unsigned long) \ | |
| 463 | ((x & 0x00000000ffffffffULL) | \ | |
| 464 | ((x & 0x0000000e00000000ULL) >> 24) | \ | |
| 465 | ((x & 0x0000000100000000ULL) >> 30))) | |
| 466 | #else | |
| 467 | #define BAT_PHYS_ADDR(x) (x) | |
| 468 | #endif | |
| 469 | ||
| 470 | ||
| 471 | /* Put high physical address bits into the BAT format */ | |
| 472 | #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) | |
| 473 | #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) | |
| 474 | ||
| 586d1d5a | 475 | /* |
| c759a01a | 476 | * BAT0 DDR |
| debb7354 | 477 | */ |
| 6d0f6bcf JCPV |
478 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| 479 | #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) | |
| 480 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) | |
| 481 | #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U | |
| debb7354 | 482 | |
| 586d1d5a | 483 | /* |
| c759a01a | 484 | * BAT1 LBC (PIXIS/CF) |
| af5d100e | 485 | */ |
| 3111d32c BB |
486 | #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ |
| 487 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ | |
| 488 | BATL_GUARDEDSTORAGE) | |
| c759a01a BB |
489 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ |
| 490 | | BATU_VS | BATU_VP) | |
| 3111d32c BB |
491 | #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ |
| 492 | | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| c759a01a | 493 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
| af5d100e BB |
494 | |
| 495 | /* if CONFIG_PCI: | |
| c759a01a | 496 | * BAT2 PCI1 and PCI1 MEM |
| af5d100e | 497 | * if CONFIG_RIO |
| c759a01a | 498 | * BAT2 Rapidio Memory |
| debb7354 | 499 | */ |
| af5d100e | 500 | #ifdef CONFIG_PCI |
| 3111d32c BB |
501 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ |
| 502 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 503 | | BATL_GUARDEDSTORAGE) | |
| 504 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \ | |
| af5d100e | 505 | | BATU_VS | BATU_VP) |
| 3111d32c BB |
506 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ |
| 507 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| af5d100e BB |
508 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
| 509 | #else /* CONFIG_RIO */ | |
| 3111d32c BB |
510 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ |
| 511 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ | |
| 512 | BATL_GUARDEDSTORAGE) | |
| 513 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ | |
| 514 | | BATU_VS | BATU_VP) | |
| 515 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ | |
| 516 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 517 | ||
| 6d0f6bcf | 518 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ |
| 5c9efb36 | 519 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 6d0f6bcf JCPV |
520 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) |
| 521 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 522 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
| af5d100e | 523 | #endif |
| debb7354 | 524 | |
| 586d1d5a | 525 | /* |
| c759a01a | 526 | * BAT3 CCSR Space |
| 3111d32c BB |
527 | * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs |
| 528 | * instead. The assembler chokes on ULL. | |
| debb7354 | 529 | */ |
| 3111d32c BB |
530 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ |
| 531 | | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 532 | | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 533 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 534 | | BATL_GUARDEDSTORAGE) | |
| c759a01a BB |
535 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ |
| 536 | | BATU_VP) | |
| 3111d32c BB |
537 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ |
| 538 | | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 539 | | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 540 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 6d0f6bcf | 541 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
| debb7354 | 542 | |
| 3111d32c BB |
543 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
| 544 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 545 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 546 | | BATL_GUARDEDSTORAGE) | |
| 547 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 548 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 549 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 550 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 551 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
| 552 | #endif | |
| 553 | ||
| 586d1d5a | 554 | /* |
| c759a01a | 555 | * BAT4 PCI1_IO and PCI2_IO |
| debb7354 | 556 | */ |
| 3111d32c BB |
557 | #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ |
| 558 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 559 | | BATL_GUARDEDSTORAGE) | |
| 560 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \ | |
| c759a01a | 561 | | BATU_VS | BATU_VP) |
| 3111d32c BB |
562 | #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ |
| 563 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 6d0f6bcf | 564 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
| debb7354 | 565 | |
| 586d1d5a | 566 | /* |
| c759a01a | 567 | * BAT5 Init RAM for stack in the CPU DCache (no backing memory) |
| debb7354 | 568 | */ |
| 6d0f6bcf JCPV |
569 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 570 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 571 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
| 572 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
| debb7354 | 573 | |
| 586d1d5a | 574 | /* |
| c759a01a | 575 | * BAT6 FLASH |
| debb7354 | 576 | */ |
| 3111d32c BB |
577 | #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 578 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 579 | | BATL_GUARDEDSTORAGE) | |
| 170deacb BB |
580 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ |
| 581 | | BATU_VP) | |
| 3111d32c BB |
582 | #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 583 | | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 6d0f6bcf | 584 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
| debb7354 | 585 | |
| bf9a8c34 BB |
586 | /* Map the last 1M of flash where we're running from reset */ |
| 587 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
| 588 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 589 | #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 590 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
| 591 | | BATL_MEMCOHERENCE) | |
| 592 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
| 593 | ||
| c759a01a BB |
594 | /* |
| 595 | * BAT7 FREE - used later for tmp mappings | |
| 596 | */ | |
| 6d0f6bcf JCPV |
597 | #define CONFIG_SYS_DBAT7L 0x00000000 |
| 598 | #define CONFIG_SYS_DBAT7U 0x00000000 | |
| 599 | #define CONFIG_SYS_IBAT7L 0x00000000 | |
| 600 | #define CONFIG_SYS_IBAT7U 0x00000000 | |
| debb7354 | 601 | |
| debb7354 JL |
602 | /* |
| 603 | * Environment | |
| 604 | */ | |
| 6d0f6bcf | 605 | #ifndef CONFIG_SYS_RAMBOOT |
| 5a1aceb0 | 606 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 607 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) |
| 0e8d1586 | 608 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
| 5c9efb36 | 609 | #else |
| 93f6d725 | 610 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 6d0f6bcf | 611 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 5c9efb36 | 612 | #endif |
| 0f2d6602 | 613 | #define CONFIG_ENV_SIZE 0x2000 |
| debb7354 JL |
614 | |
| 615 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 616 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| debb7354 | 617 | |
| 2f9c19e4 | 618 | |
| 659e2f67 JL |
619 | /* |
| 620 | * BOOTP options | |
| 621 | */ | |
| 622 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 623 | #define CONFIG_BOOTP_BOOTPATH | |
| 624 | #define CONFIG_BOOTP_GATEWAY | |
| 625 | #define CONFIG_BOOTP_HOSTNAME | |
| 626 | ||
| 627 | ||
| 2f9c19e4 JL |
628 | /* |
| 629 | * Command line configuration. | |
| 630 | */ | |
| 631 | #include <config_cmd_default.h> | |
| 632 | ||
| 633 | #define CONFIG_CMD_PING | |
| 634 | #define CONFIG_CMD_I2C | |
| 4f93f8b1 | 635 | #define CONFIG_CMD_REGINFO |
| 2f9c19e4 | 636 | |
| 6d0f6bcf | 637 | #if defined(CONFIG_SYS_RAMBOOT) |
| 2f9c19e4 JL |
638 | #undef CONFIG_CMD_ENV |
| 639 | #endif | |
| 640 | ||
| 641 | #if defined(CONFIG_PCI) | |
| 642 | #define CONFIG_CMD_PCI | |
| 643 | #define CONFIG_CMD_SCSI | |
| 644 | #define CONFIG_CMD_EXT2 | |
| bbf4796f | 645 | #define CONFIG_CMD_USB |
| debb7354 JL |
646 | #endif |
| 647 | ||
| debb7354 JL |
648 | |
| 649 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 650 | ||
| 651 | /* | |
| 652 | * Miscellaneous configurable options | |
| 653 | */ | |
| 6d0f6bcf | 654 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 53677ef1 | 655 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 6d0f6bcf JCPV |
656 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 657 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| debb7354 | 658 | |
| 2f9c19e4 | 659 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 660 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| debb7354 | 661 | #else |
| 6d0f6bcf | 662 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| debb7354 JL |
663 | #endif |
| 664 | ||
| 6d0f6bcf JCPV |
665 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 666 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 667 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 668 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| debb7354 JL |
669 | |
| 670 | /* | |
| 671 | * For booting Linux, the board info and command line data | |
| 672 | * have to be in the first 8 MB of memory, since this is | |
| 673 | * the maximum mapped by the Linux kernel during initialization. | |
| 674 | */ | |
| 6d0f6bcf | 675 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| debb7354 | 676 | |
| debb7354 JL |
677 | /* |
| 678 | * Internal Definitions | |
| 679 | * | |
| 680 | * Boot Flags | |
| 681 | */ | |
| 682 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 683 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 684 | ||
| 2f9c19e4 JL |
685 | #if defined(CONFIG_CMD_KGDB) |
| 686 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 687 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| debb7354 JL |
688 | #endif |
| 689 | ||
| debb7354 JL |
690 | /* |
| 691 | * Environment Configuration | |
| 692 | */ | |
| 693 | ||
| 694 | /* The mac addresses for all ethernet interface */ | |
| 695 | #if defined(CONFIG_TSEC_ENET) | |
| 53677ef1 | 696 | #define CONFIG_ETHADDR 00:E0:0C:00:00:01 |
| debb7354 JL |
697 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
| 698 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD | |
| 699 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD | |
| 700 | #endif | |
| 701 | ||
| 10327dc5 | 702 | #define CONFIG_HAS_ETH0 1 |
| 5c9efb36 JL |
703 | #define CONFIG_HAS_ETH1 1 |
| 704 | #define CONFIG_HAS_ETH2 1 | |
| 705 | #define CONFIG_HAS_ETH3 1 | |
| debb7354 | 706 | |
| 18b6c8cd | 707 | #define CONFIG_IPADDR 192.168.1.100 |
| debb7354 JL |
708 | |
| 709 | #define CONFIG_HOSTNAME unknown | |
| 710 | #define CONFIG_ROOTPATH /opt/nfsroot | |
| 711 | #define CONFIG_BOOTFILE uImage | |
| 32922cdc | 712 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| debb7354 | 713 | |
| 5c9efb36 | 714 | #define CONFIG_SERVERIP 192.168.1.1 |
| 18b6c8cd | 715 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 5c9efb36 | 716 | #define CONFIG_NETMASK 255.255.255.0 |
| debb7354 | 717 | |
| 5c9efb36 JL |
718 | /* default location for tftp and bootm */ |
| 719 | #define CONFIG_LOADADDR 1000000 | |
| debb7354 JL |
720 | |
| 721 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 53677ef1 | 722 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| debb7354 JL |
723 | |
| 724 | #define CONFIG_BAUDRATE 115200 | |
| 725 | ||
| 53677ef1 WD |
726 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 727 | "netdev=eth0\0" \ | |
| 728 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 729 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 730 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 731 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 732 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
| 733 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 734 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
| 735 | "consoledev=ttyS0\0" \ | |
| 736 | "ramdiskaddr=2000000\0" \ | |
| 737 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
| 738 | "fdtaddr=c00000\0" \ | |
| 739 | "fdtfile=mpc8641_hpcn.dtb\0" \ | |
| 3111d32c BB |
740 | "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ |
| 741 | "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ | |
| 53677ef1 WD |
742 | "maxcpus=2" |
| 743 | ||
| 744 | ||
| 745 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 746 | "setenv bootargs root=/dev/nfs rw " \ | |
| 747 | "nfsroot=$serverip:$rootpath " \ | |
| 748 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 749 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 750 | "tftp $loadaddr $bootfile;" \ | |
| 751 | "tftp $fdtaddr $fdtfile;" \ | |
| 752 | "bootm $loadaddr - $fdtaddr" | |
| 753 | ||
| 754 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 755 | "setenv bootargs root=/dev/ram rw " \ | |
| 756 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 757 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 758 | "tftp $loadaddr $bootfile;" \ | |
| 759 | "tftp $fdtaddr $fdtfile;" \ | |
| 760 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| debb7354 JL |
761 | |
| 762 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
| 763 | ||
| 764 | #endif /* __CONFIG_H */ |