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04a85b3b | 1 | /* |
cd0402a7 | 2 | * (C) Copyright 2000-2010 |
04a85b3b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
04a85b3b WD |
6 | */ |
7 | ||
8 | /* | |
9 | * Pantelis Antoniou, Intracom S.A., panto@intracom.gr | |
10 | * U-Boot port on NetTA4 board | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
c26e454d WD |
16 | #if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2 |
17 | #error Unsupported CONFIG_NETPHONE version | |
18 | #endif | |
19 | ||
04a85b3b WD |
20 | /* |
21 | * High Level Configuration Options | |
22 | * (easy to change) | |
23 | */ | |
24 | ||
25 | #define CONFIG_MPC870 1 /* This is a MPC885 CPU */ | |
26 | #define CONFIG_NETPHONE 1 /* ...on a NetPhone board */ | |
27 | ||
2ae18241 WD |
28 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
29 | ||
04a85b3b WD |
30 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
31 | #undef CONFIG_8xx_CONS_SMC2 | |
32 | #undef CONFIG_8xx_CONS_NONE | |
33 | ||
34 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
35 | ||
36 | /* #define CONFIG_XIN 10000000 */ | |
37 | #define CONFIG_XIN 50000000 | |
79fa88f3 WD |
38 | /* #define MPC8XX_HZ 120000000 */ |
39 | #define MPC8XX_HZ 66666666 | |
04a85b3b WD |
40 | |
41 | #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ | |
42 | ||
43 | #if 0 | |
44 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
45 | #else | |
46 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
47 | #endif | |
48 | ||
49 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ | |
50 | ||
51 | #define CONFIG_PREBOOT "echo;" | |
52 | ||
53 | #undef CONFIG_BOOTARGS | |
54 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 | 55 | "tftpboot; " \ |
79fa88f3 WD |
56 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
57 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
04a85b3b WD |
58 | "bootm" |
59 | ||
74de7aef | 60 | #define CONFIG_SOURCE |
04a85b3b | 61 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
6d0f6bcf | 62 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
04a85b3b WD |
63 | |
64 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
65 | ||
66 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
67 | ||
68 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
69 | #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ | |
70 | ||
7be044e4 JL |
71 | /* |
72 | * BOOTP options | |
73 | */ | |
74 | #define CONFIG_BOOTP_SUBNETMASK | |
75 | #define CONFIG_BOOTP_GATEWAY | |
76 | #define CONFIG_BOOTP_HOSTNAME | |
77 | #define CONFIG_BOOTP_BOOTPATH | |
78 | #define CONFIG_BOOTP_BOOTFILESIZE | |
79 | #define CONFIG_BOOTP_NISDOMAIN | |
04a85b3b WD |
80 | |
81 | #undef CONFIG_MAC_PARTITION | |
82 | #undef CONFIG_DOS_PARTITION | |
83 | ||
84 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
85 | ||
04a85b3b | 86 | #define FEC_ENET 1 /* eth.c needs it that way... */ |
6d0f6bcf | 87 | #undef CONFIG_SYS_DISCOVER_PHY |
04a85b3b | 88 | #define CONFIG_MII 1 |
0f3ba7e9 | 89 | #define CONFIG_MII_INIT 1 |
04a85b3b WD |
90 | #define CONFIG_RMII 1 /* use RMII interface */ |
91 | ||
92 | #define CONFIG_ETHER_ON_FEC1 1 | |
53677ef1 | 93 | #define CONFIG_FEC1_PHY 8 /* phy address of FEC */ |
04a85b3b WD |
94 | #define CONFIG_FEC1_PHY_NORXERR 1 |
95 | ||
96 | #define CONFIG_ETHER_ON_FEC2 1 | |
97 | #define CONFIG_FEC2_PHY 4 | |
98 | #define CONFIG_FEC2_PHY_NORXERR 1 | |
99 | ||
100 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
101 | ||
e18a1061 JL |
102 | |
103 | /* | |
104 | * Command line configuration. | |
105 | */ | |
106 | #include <config_cmd_default.h> | |
107 | ||
e18a1061 JL |
108 | #define CONFIG_CMD_DHCP |
109 | #define CONFIG_CMD_PING | |
110 | #define CONFIG_CMD_MII | |
111 | #define CONFIG_CMD_CDP | |
112 | ||
04a85b3b WD |
113 | |
114 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
115 | #define CONFIG_MISC_INIT_R | |
116 | ||
04a85b3b WD |
117 | /* |
118 | * Miscellaneous configurable options | |
119 | */ | |
6d0f6bcf JCPV |
120 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
121 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
04a85b3b | 122 | |
6d0f6bcf | 123 | #define CONFIG_SYS_HUSH_PARSER 1 |
04a85b3b | 124 | |
e18a1061 | 125 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 126 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
04a85b3b | 127 | #else |
6d0f6bcf | 128 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
04a85b3b | 129 | #endif |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
131 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
132 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
04a85b3b | 133 | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
135 | #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ | |
04a85b3b | 136 | |
6d0f6bcf | 137 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
04a85b3b | 138 | |
6d0f6bcf | 139 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
04a85b3b | 140 | |
04a85b3b WD |
141 | /* |
142 | * Low Level Configuration Settings | |
143 | * (address mappings, register initial values, etc.) | |
144 | * You should know what you are doing if you make changes here. | |
145 | */ | |
146 | /*----------------------------------------------------------------------- | |
147 | * Internal Memory Mapped Register | |
148 | */ | |
6d0f6bcf | 149 | #define CONFIG_SYS_IMMR 0xFF000000 |
04a85b3b WD |
150 | |
151 | /*----------------------------------------------------------------------- | |
152 | * Definitions for initial stack pointer and data area (in DPRAM) | |
153 | */ | |
6d0f6bcf | 154 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 155 | #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
25ddd1fb | 156 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 157 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
04a85b3b WD |
158 | |
159 | /*----------------------------------------------------------------------- | |
160 | * Start addresses for the final memory configuration | |
161 | * (Set up by the startup code) | |
6d0f6bcf | 162 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
04a85b3b | 163 | */ |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
165 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
04a85b3b | 166 | #if defined(DEBUG) |
6d0f6bcf | 167 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
04a85b3b | 168 | #else |
6d0f6bcf | 169 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
04a85b3b | 170 | #endif |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
172 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
c26e454d | 173 | #if CONFIG_NETPHONE_VERSION == 2 |
6d0f6bcf | 174 | #define CONFIG_SYS_FLASH_BASE4 0x40080000 |
c26e454d WD |
175 | #endif |
176 | ||
6d0f6bcf | 177 | #define CONFIG_SYS_RESET_ADDRESS 0x80000000 |
04a85b3b WD |
178 | |
179 | /* | |
180 | * For booting Linux, the board info and command line data | |
181 | * have to be in the first 8 MB of memory, since this is | |
182 | * the maximum mapped by the Linux kernel during initialization. | |
183 | */ | |
6d0f6bcf | 184 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
04a85b3b WD |
185 | |
186 | /*----------------------------------------------------------------------- | |
187 | * FLASH organization | |
188 | */ | |
c26e454d | 189 | #if CONFIG_NETPHONE_VERSION == 1 |
6d0f6bcf | 190 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
c26e454d | 191 | #elif CONFIG_NETPHONE_VERSION == 2 |
6d0f6bcf | 192 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
c26e454d | 193 | #endif |
6d0f6bcf | 194 | #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
04a85b3b | 195 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
197 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
04a85b3b | 198 | |
5a1aceb0 | 199 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 200 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
04a85b3b | 201 | |
6d0f6bcf | 202 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) |
0e8d1586 | 203 | #define CONFIG_ENV_SIZE 0x4000 |
04a85b3b | 204 | |
6d0f6bcf | 205 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) |
0e8d1586 | 206 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
04a85b3b WD |
207 | |
208 | /*----------------------------------------------------------------------- | |
209 | * Cache Configuration | |
210 | */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
e18a1061 | 212 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 213 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
04a85b3b WD |
214 | #endif |
215 | ||
216 | /*----------------------------------------------------------------------- | |
217 | * SYPCR - System Protection Control 11-9 | |
218 | * SYPCR can only be written once after reset! | |
219 | *----------------------------------------------------------------------- | |
220 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
221 | */ | |
222 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 223 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
04a85b3b WD |
224 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
225 | #else | |
6d0f6bcf | 226 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
04a85b3b WD |
227 | #endif |
228 | ||
229 | /*----------------------------------------------------------------------- | |
230 | * SIUMCR - SIU Module Configuration 11-6 | |
231 | *----------------------------------------------------------------------- | |
232 | * PCMCIA config., multi-function pin tri-state | |
233 | */ | |
234 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 235 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
04a85b3b | 236 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 237 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
04a85b3b WD |
238 | #endif /* CONFIG_CAN_DRIVER */ |
239 | ||
240 | /*----------------------------------------------------------------------- | |
241 | * TBSCR - Time Base Status and Control 11-26 | |
242 | *----------------------------------------------------------------------- | |
243 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
244 | */ | |
6d0f6bcf | 245 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
04a85b3b WD |
246 | |
247 | /*----------------------------------------------------------------------- | |
248 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
249 | *----------------------------------------------------------------------- | |
250 | */ | |
6d0f6bcf | 251 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
04a85b3b WD |
252 | |
253 | /*----------------------------------------------------------------------- | |
254 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
255 | *----------------------------------------------------------------------- | |
256 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
257 | */ | |
6d0f6bcf | 258 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
04a85b3b WD |
259 | |
260 | /*----------------------------------------------------------------------- | |
261 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
262 | *----------------------------------------------------------------------- | |
263 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
264 | * interrupt status bit | |
265 | * | |
266 | */ | |
267 | ||
268 | #if CONFIG_XIN == 10000000 | |
269 | ||
270 | #if MPC8XX_HZ == 120000000 | |
6d0f6bcf | 271 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 272 | (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 273 | PLPRCR_TEXPS) |
04a85b3b | 274 | #elif MPC8XX_HZ == 100000000 |
6d0f6bcf | 275 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 276 | (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 277 | PLPRCR_TEXPS) |
04a85b3b | 278 | #elif MPC8XX_HZ == 50000000 |
6d0f6bcf | 279 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 280 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 281 | PLPRCR_TEXPS) |
04a85b3b | 282 | #elif MPC8XX_HZ == 25000000 |
6d0f6bcf | 283 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 284 | (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 285 | PLPRCR_TEXPS) |
04a85b3b | 286 | #elif MPC8XX_HZ == 40000000 |
6d0f6bcf | 287 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 288 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 289 | PLPRCR_TEXPS) |
04a85b3b | 290 | #elif MPC8XX_HZ == 75000000 |
6d0f6bcf | 291 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 292 | (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 293 | PLPRCR_TEXPS) |
04a85b3b WD |
294 | #else |
295 | #error unsupported CPU freq for XIN = 10MHz | |
296 | #endif | |
297 | ||
298 | #elif CONFIG_XIN == 50000000 | |
299 | ||
300 | #if MPC8XX_HZ == 120000000 | |
6d0f6bcf | 301 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 302 | (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 303 | PLPRCR_TEXPS) |
04a85b3b | 304 | #elif MPC8XX_HZ == 100000000 |
6d0f6bcf | 305 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 306 | (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 307 | PLPRCR_TEXPS) |
c26e454d | 308 | #elif MPC8XX_HZ == 66666666 |
6d0f6bcf | 309 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
c26e454d | 310 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 311 | PLPRCR_TEXPS) |
04a85b3b WD |
312 | #else |
313 | #error unsupported CPU freq for XIN = 50MHz | |
314 | #endif | |
315 | ||
316 | #else | |
317 | ||
318 | #error unsupported XIN freq | |
319 | #endif | |
320 | ||
321 | ||
322 | /* | |
323 | *----------------------------------------------------------------------- | |
324 | * SCCR - System Clock and reset Control Register 15-27 | |
325 | *----------------------------------------------------------------------- | |
326 | * Set clock output, timebase and RTC source and divider, | |
327 | * power management and some other internal clocks | |
79fa88f3 WD |
328 | * |
329 | * Note: When TBS == 0 the timebase is independent of current cpu clock. | |
04a85b3b WD |
330 | */ |
331 | ||
332 | #define SCCR_MASK SCCR_EBDF11 | |
333 | #if MPC8XX_HZ > 66666666 | |
6d0f6bcf | 334 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
04a85b3b WD |
335 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
336 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
337 | SCCR_DFALCD00 | SCCR_EBDF01) | |
338 | #else | |
6d0f6bcf | 339 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
04a85b3b WD |
340 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
341 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
342 | SCCR_DFALCD00) | |
343 | #endif | |
344 | ||
345 | /*----------------------------------------------------------------------- | |
346 | * | |
347 | *----------------------------------------------------------------------- | |
348 | * | |
349 | */ | |
6d0f6bcf JCPV |
350 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
351 | #define CONFIG_SYS_DER 0 | |
04a85b3b WD |
352 | |
353 | /* | |
354 | * Init Memory Controller: | |
355 | * | |
356 | * BR0/1 and OR0/1 (FLASH) | |
357 | */ | |
358 | ||
359 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
360 | ||
361 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
362 | * restrict access enough to keep SRAM working (if any) | |
363 | * but not too much to meddle with FLASH accesses | |
364 | */ | |
6d0f6bcf JCPV |
365 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
366 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
04a85b3b WD |
367 | |
368 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
6d0f6bcf | 369 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
04a85b3b | 370 | |
6d0f6bcf JCPV |
371 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
372 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
373 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
04a85b3b | 374 | |
c26e454d WD |
375 | #if CONFIG_NETPHONE_VERSION == 2 |
376 | ||
377 | #define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ | |
378 | ||
6d0f6bcf JCPV |
379 | #define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
380 | #define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
381 | #define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
c26e454d WD |
382 | |
383 | #endif | |
384 | ||
04a85b3b WD |
385 | /* |
386 | * BR3 and OR3 (SDRAM) | |
387 | * | |
388 | */ | |
389 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
390 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ | |
391 | ||
392 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 393 | #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
04a85b3b | 394 | |
6d0f6bcf JCPV |
395 | #define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
396 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) | |
04a85b3b WD |
397 | |
398 | /* | |
399 | * Memory Periodic Timer Prescaler | |
400 | */ | |
401 | ||
402 | /* | |
403 | * Memory Periodic Timer Prescaler | |
404 | * | |
405 | * The Divider for PTA (refresh timer) configuration is based on an | |
406 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
407 | * the number of chip selects (NCS) and the actually needed refresh | |
408 | * rate is done by setting MPTPR. | |
409 | * | |
410 | * PTA is calculated from | |
411 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
412 | * | |
413 | * gclk CPU clock (not bus clock!) | |
414 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
415 | * | |
416 | * 4096 Rows from SDRAM example configuration | |
417 | * 1000 factor s -> ms | |
418 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
419 | * 4 Number of refresh cycles per period | |
420 | * 64 Refresh cycle in ms per number of rows | |
421 | * -------------------------------------------- | |
422 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
423 | * | |
424 | * 50 MHz => 50.000.000 / Divider = 98 | |
425 | * 66 Mhz => 66.000.000 / Divider = 129 | |
426 | * 80 Mhz => 80.000.000 / Divider = 156 | |
427 | */ | |
428 | ||
6d0f6bcf | 429 | #define CONFIG_SYS_MAMR_PTA 234 |
04a85b3b WD |
430 | |
431 | /* | |
432 | * For 16 MBit, refresh rates could be 31.3 us | |
433 | * (= 64 ms / 2K = 125 / quad bursts). | |
434 | * For a simpler initialization, 15.6 us is used instead. | |
435 | * | |
6d0f6bcf JCPV |
436 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
437 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
04a85b3b | 438 | */ |
6d0f6bcf JCPV |
439 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
440 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
04a85b3b WD |
441 | |
442 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
443 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
444 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
04a85b3b WD |
445 | |
446 | /* | |
447 | * MAMR settings for SDRAM | |
448 | */ | |
449 | ||
450 | /* 8 column SDRAM */ | |
6d0f6bcf | 451 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
04a85b3b WD |
452 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
453 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
454 | ||
455 | /* 9 column SDRAM */ | |
6d0f6bcf | 456 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
04a85b3b WD |
457 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
458 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
459 | ||
04a85b3b WD |
460 | #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ |
461 | ||
462 | /****************************************************************/ | |
463 | ||
464 | #define DSP_SIZE 0x00010000 /* 64K */ | |
465 | #define NAND_SIZE 0x00010000 /* 64K */ | |
04a85b3b WD |
466 | |
467 | #define DSP_BASE 0xF1000000 | |
468 | #define NAND_BASE 0xF1010000 | |
04a85b3b | 469 | |
04a85b3b WD |
470 | /*****************************************************************************/ |
471 | ||
6d0f6bcf | 472 | #define CONFIG_SYS_DIRECT_FLASH_TFTP |
79fa88f3 WD |
473 | |
474 | /*****************************************************************************/ | |
475 | ||
c26e454d | 476 | #if CONFIG_NETPHONE_VERSION == 1 |
04a85b3b | 477 | #define STATUS_LED_BIT 0x00000008 /* bit 28 */ |
c26e454d WD |
478 | #elif CONFIG_NETPHONE_VERSION == 2 |
479 | #define STATUS_LED_BIT 0x00000080 /* bit 24 */ | |
480 | #endif | |
481 | ||
6d0f6bcf | 482 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
04a85b3b WD |
483 | #define STATUS_LED_STATE STATUS_LED_BLINKING |
484 | ||
485 | #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ | |
486 | #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ | |
487 | ||
488 | #ifndef __ASSEMBLY__ | |
489 | ||
490 | /* LEDs */ | |
491 | ||
492 | /* led_id_t is unsigned int mask */ | |
493 | typedef unsigned int led_id_t; | |
494 | ||
495 | #define __led_toggle(_msk) \ | |
496 | do { \ | |
6d0f6bcf | 497 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \ |
04a85b3b WD |
498 | } while(0) |
499 | ||
500 | #define __led_set(_msk, _st) \ | |
501 | do { \ | |
502 | if ((_st)) \ | |
6d0f6bcf | 503 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \ |
04a85b3b | 504 | else \ |
6d0f6bcf | 505 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ |
04a85b3b WD |
506 | } while(0) |
507 | ||
508 | #define __led_init(msk, st) __led_set(msk, st) | |
509 | ||
510 | #endif | |
511 | ||
512 | /*********************************************************************************************************** | |
513 | ||
c26e454d WD |
514 | ---------------------------------------------------------------------------------------------- |
515 | ||
516 | (V1) version 1 of the board | |
517 | (V2) version 2 of the board | |
518 | ||
519 | ---------------------------------------------------------------------------------------------- | |
520 | ||
04a85b3b WD |
521 | Pin definitions: |
522 | ||
523 | +------+----------------+--------+------------------------------------------------------------ | |
524 | | # | Name | Type | Comment | |
525 | +------+----------------+--------+------------------------------------------------------------ | |
526 | | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select | |
527 | | PA7 | DSP_INT | Output | DSP interrupt | |
528 | | PA10 | DSP_RESET | Output | DSP reset | |
529 | | PA14 | USBOE | Output | USB (1) | |
530 | | PA15 | USBRXD | Output | USB (1) | |
531 | | PB19 | BT_RTS | Output | Bluetooth (0) | |
532 | | PB23 | BT_CTS | Output | Bluetooth (0) | |
533 | | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select | |
534 | | PB27 | SPICS_DISP | Output | Display chip select | |
535 | | PB28 | SPI_RXD_3V | Input | SPI Data Rx | |
536 | | PB29 | SPI_TXD | Output | SPI Data Tx | |
537 | | PB30 | SPI_CLK | Output | SPI Clock | |
538 | | PC10 | DISPA0 | Output | Display A0 | |
539 | | PC11 | BACKLIGHT | Output | Display backlit | |
c26e454d WD |
540 | | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD |
541 | | | IO_RESET | Output | (V2) General I/O reset | |
542 | | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) | |
543 | | | HOOK | Input | (V2) Hook input interrupt | |
544 | | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK | |
545 | | | F_RY_BY | Input | (V2) NAND F_RY_BY | |
04a85b3b WD |
546 | | PE17 | F_ALE | Output | NAND F_ALE |
547 | | PE18 | F_CLE | Output | NAND F_CLE | |
548 | | PE20 | F_CE | Output | NAND F_CE | |
c26e454d WD |
549 | | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select |
550 | | | LED | Output | (V2) LED | |
04a85b3b | 551 | | PE27 | SPICS_ER | Output | External serial register CS |
c26e454d WD |
552 | | PE28 | LEDIO1 | Output | (V1) LED |
553 | | | BKBR1 | Input | (V2) Keyboard input scan | |
554 | | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) | |
555 | | | BKBR2 | Input | (V2) Keyboard input scan | |
556 | | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) | |
557 | | | BKBR3 | Input | (V2) Keyboard input scan | |
558 | | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY | |
559 | | | BKBR4 | Input | (V2) Keyboard input scan | |
04a85b3b WD |
560 | +------+----------------+--------+--------------------------------------------------- |
561 | ||
c26e454d WD |
562 | ---------------------------------------------------------------------------------------------- |
563 | ||
564 | Serial register input: | |
565 | ||
566 | +------+----------------+------------------------------------------------------------ | |
567 | | # | Name | Comment | |
568 | +------+----------------+------------------------------------------------------------ | |
6e592385 WD |
569 | | 0 | BKBR1 | (V1) Keyboard input scan |
570 | | 1 | BKBR3 | (V1) Keyboard input scan | |
571 | | 2 | BKBR4 | (V1) Keyboard input scan | |
572 | | 3 | BKBR2 | (V1) Keyboard input scan | |
573 | | 4 | HOOK | (V1) Hook switch | |
c26e454d WD |
574 | | 5 | BT_LINK | (V1) Bluetooth link status |
575 | | 6 | HOST_WAKE | (V1) Bluetooth host wake up | |
576 | | 7 | OK_ETH | (V1) Cisco inline power OK status | |
577 | +------+----------------+------------------------------------------------------------ | |
578 | ||
579 | ---------------------------------------------------------------------------------------------- | |
580 | ||
581 | Serial register output: | |
582 | ||
583 | +------+----------------+------------------------------------------------------------ | |
584 | | # | Name | Comment | |
585 | +------+----------------+------------------------------------------------------------ | |
6e592385 WD |
586 | | 0 | KEY1 | Keyboard output scan |
587 | | 1 | KEY2 | Keyboard output scan | |
588 | | 2 | KEY3 | Keyboard output scan | |
589 | | 3 | KEY4 | Keyboard output scan | |
590 | | 4 | KEY5 | Keyboard output scan | |
591 | | 5 | KEY6 | Keyboard output scan | |
592 | | 6 | KEY7 | Keyboard output scan | |
c26e454d WD |
593 | | 7 | BT_WAKE | Bluetooth wake up |
594 | +------+----------------+------------------------------------------------------------ | |
595 | ||
596 | ---------------------------------------------------------------------------------------------- | |
597 | ||
04a85b3b WD |
598 | Chip selects: |
599 | ||
600 | +------+----------------+------------------------------------------------------------ | |
601 | | # | Name | Comment | |
602 | +------+----------------+------------------------------------------------------------ | |
603 | | CS0 | CS0 | Boot flash | |
604 | | CS1 | CS_FLASH | NAND flash | |
605 | | CS2 | CS_DSP | DSP | |
606 | | CS3 | DCS_DRAM | DRAM | |
c26e454d | 607 | | CS4 | CS_FLASH2 | (V2) 2nd flash |
04a85b3b WD |
608 | +------+----------------+------------------------------------------------------------ |
609 | ||
c26e454d WD |
610 | ---------------------------------------------------------------------------------------------- |
611 | ||
04a85b3b WD |
612 | Interrupts: |
613 | ||
614 | +------+----------------+------------------------------------------------------------ | |
615 | | # | Name | Comment | |
616 | +------+----------------+------------------------------------------------------------ | |
617 | | IRQ1 | IRQ_DSP | DSP interrupt | |
618 | | IRQ3 | S_INTER | DUSLIC ??? | |
619 | | IRQ4 | F_RY_BY | NAND | |
620 | | IRQ7 | IRQ_MAX | MAX 3100 interrupt | |
621 | +------+----------------+------------------------------------------------------------ | |
622 | ||
c26e454d WD |
623 | ---------------------------------------------------------------------------------------------- |
624 | ||
04a85b3b WD |
625 | Interrupts on PCMCIA pins: |
626 | ||
627 | +------+----------------+------------------------------------------------------------ | |
628 | | # | Name | Comment | |
629 | +------+----------------+------------------------------------------------------------ | |
630 | | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface | |
631 | | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface | |
632 | | IP_A2| RMII1_MDINT | PHY interrupt for #1 | |
633 | | IP_A3| RMII2_MDINT | PHY interrupt for #2 | |
c26e454d WD |
634 | | IP_A5| HOST_WAKE | (V2) Bluetooth host wake |
635 | | IP_A6| OK_ETH | (V2) Cisco inline power OK | |
04a85b3b WD |
636 | +------+----------------+------------------------------------------------------------ |
637 | ||
638 | *************************************************************************************************/ | |
639 | ||
640 | #define CONFIG_SED156X 1 /* use SED156X */ | |
641 | #define CONFIG_SED156X_PG12864Q 1 /* type of display used */ | |
642 | ||
643 | /* serial interfacing macros */ | |
644 | ||
6d0f6bcf | 645 | #define SED156X_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
04a85b3b WD |
646 | #define SED156X_SPI_RXD_MASK 0x00000008 |
647 | ||
6d0f6bcf | 648 | #define SED156X_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
04a85b3b WD |
649 | #define SED156X_SPI_TXD_MASK 0x00000004 |
650 | ||
6d0f6bcf | 651 | #define SED156X_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
04a85b3b WD |
652 | #define SED156X_SPI_CLK_MASK 0x00000002 |
653 | ||
6d0f6bcf | 654 | #define SED156X_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
04a85b3b WD |
655 | #define SED156X_CS_MASK 0x00000010 |
656 | ||
6d0f6bcf | 657 | #define SED156X_A0_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) |
04a85b3b WD |
658 | #define SED156X_A0_MASK 0x0020 |
659 | ||
660 | /*************************************************************************************************/ | |
661 | ||
6d0f6bcf JCPV |
662 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
663 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 | |
664 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 | |
04a85b3b WD |
665 | |
666 | /*************************************************************************************************/ | |
667 | ||
668 | /* use board specific hardware */ | |
669 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
670 | #define CONFIG_HW_WATCHDOG | |
671 | #define CONFIG_SHOW_ACTIVITY | |
672 | ||
673 | /*************************************************************************************************/ | |
674 | ||
675 | /* phone console configuration */ | |
676 | ||
6d0f6bcf | 677 | #define PHONE_CONSOLE_POLL_HZ (CONFIG_SYS_HZ/200) /* poll every 5ms */ |
04a85b3b WD |
678 | |
679 | /*************************************************************************************************/ | |
680 | ||
681 | #define CONFIG_CDP_DEVICE_ID 20 | |
682 | #define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */ | |
683 | #define CONFIG_CDP_PORT_ID "eth%d" | |
684 | #define CONFIG_CDP_CAPABILITIES 0x00000010 | |
561858ee | 685 | #define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME |
04a85b3b WD |
686 | #define CONFIG_CDP_PLATFORM "Intracom NetPhone" |
687 | #define CONFIG_CDP_TRIGGER 0x20020001 | |
688 | #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ | |
689 | #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */ | |
690 | ||
691 | /*************************************************************************************************/ | |
692 | ||
693 | #define CONFIG_AUTO_COMPLETE 1 | |
694 | ||
695 | /*************************************************************************************************/ | |
696 | ||
c26e454d WD |
697 | #define CONFIG_CRC32_VERIFY 1 |
698 | ||
699 | /*************************************************************************************************/ | |
700 | ||
701 | #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 | |
702 | ||
703 | /*************************************************************************************************/ | |
04a85b3b | 704 | #endif /* __CONFIG_H */ |