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04a85b3b WD |
1 | /* |
2 | * (C) Copyright 2000-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * Pantelis Antoniou, Intracom S.A., panto@intracom.gr | |
26 | * U-Boot port on NetTA4 board | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
c26e454d WD |
32 | #if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2 |
33 | #error Unsupported CONFIG_NETPHONE version | |
34 | #endif | |
35 | ||
04a85b3b WD |
36 | /* |
37 | * High Level Configuration Options | |
38 | * (easy to change) | |
39 | */ | |
40 | ||
41 | #define CONFIG_MPC870 1 /* This is a MPC885 CPU */ | |
42 | #define CONFIG_NETPHONE 1 /* ...on a NetPhone board */ | |
43 | ||
44 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
45 | #undef CONFIG_8xx_CONS_SMC2 | |
46 | #undef CONFIG_8xx_CONS_NONE | |
47 | ||
48 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
49 | ||
50 | /* #define CONFIG_XIN 10000000 */ | |
51 | #define CONFIG_XIN 50000000 | |
79fa88f3 WD |
52 | /* #define MPC8XX_HZ 120000000 */ |
53 | #define MPC8XX_HZ 66666666 | |
04a85b3b WD |
54 | |
55 | #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ | |
56 | ||
57 | #if 0 | |
58 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
59 | #else | |
60 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
61 | #endif | |
62 | ||
63 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ | |
64 | ||
65 | #define CONFIG_PREBOOT "echo;" | |
66 | ||
67 | #undef CONFIG_BOOTARGS | |
68 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 | 69 | "tftpboot; " \ |
79fa88f3 WD |
70 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
71 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
04a85b3b WD |
72 | "bootm" |
73 | ||
74 | #define CONFIG_AUTOSCRIPT | |
75 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
6d0f6bcf | 76 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
04a85b3b WD |
77 | |
78 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
79 | ||
80 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
81 | ||
82 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
83 | #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ | |
84 | ||
7be044e4 JL |
85 | /* |
86 | * BOOTP options | |
87 | */ | |
88 | #define CONFIG_BOOTP_SUBNETMASK | |
89 | #define CONFIG_BOOTP_GATEWAY | |
90 | #define CONFIG_BOOTP_HOSTNAME | |
91 | #define CONFIG_BOOTP_BOOTPATH | |
92 | #define CONFIG_BOOTP_BOOTFILESIZE | |
93 | #define CONFIG_BOOTP_NISDOMAIN | |
04a85b3b WD |
94 | |
95 | #undef CONFIG_MAC_PARTITION | |
96 | #undef CONFIG_DOS_PARTITION | |
97 | ||
98 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
99 | ||
53677ef1 | 100 | #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ |
04a85b3b | 101 | #define FEC_ENET 1 /* eth.c needs it that way... */ |
6d0f6bcf | 102 | #undef CONFIG_SYS_DISCOVER_PHY |
04a85b3b | 103 | #define CONFIG_MII 1 |
0f3ba7e9 | 104 | #define CONFIG_MII_INIT 1 |
04a85b3b WD |
105 | #define CONFIG_RMII 1 /* use RMII interface */ |
106 | ||
107 | #define CONFIG_ETHER_ON_FEC1 1 | |
53677ef1 | 108 | #define CONFIG_FEC1_PHY 8 /* phy address of FEC */ |
04a85b3b WD |
109 | #define CONFIG_FEC1_PHY_NORXERR 1 |
110 | ||
111 | #define CONFIG_ETHER_ON_FEC2 1 | |
112 | #define CONFIG_FEC2_PHY 4 | |
113 | #define CONFIG_FEC2_PHY_NORXERR 1 | |
114 | ||
115 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
116 | ||
e18a1061 JL |
117 | |
118 | /* | |
119 | * Command line configuration. | |
120 | */ | |
121 | #include <config_cmd_default.h> | |
122 | ||
123 | #define CONFIG_CMD_NAND | |
124 | #define CONFIG_CMD_DHCP | |
125 | #define CONFIG_CMD_PING | |
126 | #define CONFIG_CMD_MII | |
127 | #define CONFIG_CMD_CDP | |
128 | ||
04a85b3b WD |
129 | |
130 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
131 | #define CONFIG_MISC_INIT_R | |
132 | ||
04a85b3b WD |
133 | /* |
134 | * Miscellaneous configurable options | |
135 | */ | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
137 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
04a85b3b | 138 | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_HUSH_PARSER 1 |
140 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
04a85b3b | 141 | |
e18a1061 | 142 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 143 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
04a85b3b | 144 | #else |
6d0f6bcf | 145 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
04a85b3b | 146 | #endif |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
148 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
149 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
04a85b3b | 150 | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
152 | #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ | |
04a85b3b | 153 | |
6d0f6bcf | 154 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
04a85b3b | 155 | |
6d0f6bcf | 156 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
04a85b3b | 157 | |
6d0f6bcf | 158 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
04a85b3b WD |
159 | |
160 | /* | |
161 | * Low Level Configuration Settings | |
162 | * (address mappings, register initial values, etc.) | |
163 | * You should know what you are doing if you make changes here. | |
164 | */ | |
165 | /*----------------------------------------------------------------------- | |
166 | * Internal Memory Mapped Register | |
167 | */ | |
6d0f6bcf | 168 | #define CONFIG_SYS_IMMR 0xFF000000 |
04a85b3b WD |
169 | |
170 | /*----------------------------------------------------------------------- | |
171 | * Definitions for initial stack pointer and data area (in DPRAM) | |
172 | */ | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
174 | #define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ | |
175 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
176 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
177 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
04a85b3b WD |
178 | |
179 | /*----------------------------------------------------------------------- | |
180 | * Start addresses for the final memory configuration | |
181 | * (Set up by the startup code) | |
6d0f6bcf | 182 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
04a85b3b | 183 | */ |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
185 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
04a85b3b | 186 | #if defined(DEBUG) |
6d0f6bcf | 187 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
04a85b3b | 188 | #else |
6d0f6bcf | 189 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
04a85b3b | 190 | #endif |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
192 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
c26e454d | 193 | #if CONFIG_NETPHONE_VERSION == 2 |
6d0f6bcf | 194 | #define CONFIG_SYS_FLASH_BASE4 0x40080000 |
c26e454d WD |
195 | #endif |
196 | ||
6d0f6bcf | 197 | #define CONFIG_SYS_RESET_ADDRESS 0x80000000 |
04a85b3b WD |
198 | |
199 | /* | |
200 | * For booting Linux, the board info and command line data | |
201 | * have to be in the first 8 MB of memory, since this is | |
202 | * the maximum mapped by the Linux kernel during initialization. | |
203 | */ | |
6d0f6bcf | 204 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
04a85b3b WD |
205 | |
206 | /*----------------------------------------------------------------------- | |
207 | * FLASH organization | |
208 | */ | |
c26e454d | 209 | #if CONFIG_NETPHONE_VERSION == 1 |
6d0f6bcf | 210 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
c26e454d | 211 | #elif CONFIG_NETPHONE_VERSION == 2 |
6d0f6bcf | 212 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
c26e454d | 213 | #endif |
6d0f6bcf | 214 | #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
04a85b3b | 215 | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
217 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
04a85b3b | 218 | |
5a1aceb0 | 219 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 220 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
04a85b3b | 221 | |
6d0f6bcf | 222 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) |
0e8d1586 JCPV |
223 | #define CONFIG_ENV_OFFSET 0 |
224 | #define CONFIG_ENV_SIZE 0x4000 | |
04a85b3b | 225 | |
6d0f6bcf | 226 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) |
0e8d1586 JCPV |
227 | #define CONFIG_ENV_OFFSET_REDUND 0 |
228 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
04a85b3b WD |
229 | |
230 | /*----------------------------------------------------------------------- | |
231 | * Cache Configuration | |
232 | */ | |
6d0f6bcf | 233 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
e18a1061 | 234 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 235 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
04a85b3b WD |
236 | #endif |
237 | ||
238 | /*----------------------------------------------------------------------- | |
239 | * SYPCR - System Protection Control 11-9 | |
240 | * SYPCR can only be written once after reset! | |
241 | *----------------------------------------------------------------------- | |
242 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
243 | */ | |
244 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 245 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
04a85b3b WD |
246 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
247 | #else | |
6d0f6bcf | 248 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
04a85b3b WD |
249 | #endif |
250 | ||
251 | /*----------------------------------------------------------------------- | |
252 | * SIUMCR - SIU Module Configuration 11-6 | |
253 | *----------------------------------------------------------------------- | |
254 | * PCMCIA config., multi-function pin tri-state | |
255 | */ | |
256 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 257 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
04a85b3b | 258 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 259 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
04a85b3b WD |
260 | #endif /* CONFIG_CAN_DRIVER */ |
261 | ||
262 | /*----------------------------------------------------------------------- | |
263 | * TBSCR - Time Base Status and Control 11-26 | |
264 | *----------------------------------------------------------------------- | |
265 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
266 | */ | |
6d0f6bcf | 267 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
04a85b3b WD |
268 | |
269 | /*----------------------------------------------------------------------- | |
270 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
271 | *----------------------------------------------------------------------- | |
272 | */ | |
6d0f6bcf | 273 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
04a85b3b WD |
274 | |
275 | /*----------------------------------------------------------------------- | |
276 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
277 | *----------------------------------------------------------------------- | |
278 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
279 | */ | |
6d0f6bcf | 280 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
04a85b3b WD |
281 | |
282 | /*----------------------------------------------------------------------- | |
283 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
284 | *----------------------------------------------------------------------- | |
285 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
286 | * interrupt status bit | |
287 | * | |
288 | */ | |
289 | ||
290 | #if CONFIG_XIN == 10000000 | |
291 | ||
292 | #if MPC8XX_HZ == 120000000 | |
6d0f6bcf | 293 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 294 | (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 295 | PLPRCR_TEXPS) |
04a85b3b | 296 | #elif MPC8XX_HZ == 100000000 |
6d0f6bcf | 297 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 298 | (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 299 | PLPRCR_TEXPS) |
04a85b3b | 300 | #elif MPC8XX_HZ == 50000000 |
6d0f6bcf | 301 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 302 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 303 | PLPRCR_TEXPS) |
04a85b3b | 304 | #elif MPC8XX_HZ == 25000000 |
6d0f6bcf | 305 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 306 | (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 307 | PLPRCR_TEXPS) |
04a85b3b | 308 | #elif MPC8XX_HZ == 40000000 |
6d0f6bcf | 309 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 310 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 311 | PLPRCR_TEXPS) |
04a85b3b | 312 | #elif MPC8XX_HZ == 75000000 |
6d0f6bcf | 313 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 314 | (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 315 | PLPRCR_TEXPS) |
04a85b3b WD |
316 | #else |
317 | #error unsupported CPU freq for XIN = 10MHz | |
318 | #endif | |
319 | ||
320 | #elif CONFIG_XIN == 50000000 | |
321 | ||
322 | #if MPC8XX_HZ == 120000000 | |
6d0f6bcf | 323 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 324 | (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 325 | PLPRCR_TEXPS) |
04a85b3b | 326 | #elif MPC8XX_HZ == 100000000 |
6d0f6bcf | 327 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
04a85b3b | 328 | (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 329 | PLPRCR_TEXPS) |
c26e454d | 330 | #elif MPC8XX_HZ == 66666666 |
6d0f6bcf | 331 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
c26e454d | 332 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 333 | PLPRCR_TEXPS) |
04a85b3b WD |
334 | #else |
335 | #error unsupported CPU freq for XIN = 50MHz | |
336 | #endif | |
337 | ||
338 | #else | |
339 | ||
340 | #error unsupported XIN freq | |
341 | #endif | |
342 | ||
343 | ||
344 | /* | |
345 | *----------------------------------------------------------------------- | |
346 | * SCCR - System Clock and reset Control Register 15-27 | |
347 | *----------------------------------------------------------------------- | |
348 | * Set clock output, timebase and RTC source and divider, | |
349 | * power management and some other internal clocks | |
79fa88f3 WD |
350 | * |
351 | * Note: When TBS == 0 the timebase is independent of current cpu clock. | |
04a85b3b WD |
352 | */ |
353 | ||
354 | #define SCCR_MASK SCCR_EBDF11 | |
355 | #if MPC8XX_HZ > 66666666 | |
6d0f6bcf | 356 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
04a85b3b WD |
357 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
358 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
359 | SCCR_DFALCD00 | SCCR_EBDF01) | |
360 | #else | |
6d0f6bcf | 361 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
04a85b3b WD |
362 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
363 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
364 | SCCR_DFALCD00) | |
365 | #endif | |
366 | ||
367 | /*----------------------------------------------------------------------- | |
368 | * | |
369 | *----------------------------------------------------------------------- | |
370 | * | |
371 | */ | |
6d0f6bcf JCPV |
372 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
373 | #define CONFIG_SYS_DER 0 | |
04a85b3b WD |
374 | |
375 | /* | |
376 | * Init Memory Controller: | |
377 | * | |
378 | * BR0/1 and OR0/1 (FLASH) | |
379 | */ | |
380 | ||
381 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
382 | ||
383 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
384 | * restrict access enough to keep SRAM working (if any) | |
385 | * but not too much to meddle with FLASH accesses | |
386 | */ | |
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
388 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
04a85b3b WD |
389 | |
390 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
6d0f6bcf | 391 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
04a85b3b | 392 | |
6d0f6bcf JCPV |
393 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
394 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
395 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
04a85b3b | 396 | |
c26e454d WD |
397 | #if CONFIG_NETPHONE_VERSION == 2 |
398 | ||
399 | #define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ | |
400 | ||
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
402 | #define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
403 | #define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
c26e454d WD |
404 | |
405 | #endif | |
406 | ||
04a85b3b WD |
407 | /* |
408 | * BR3 and OR3 (SDRAM) | |
409 | * | |
410 | */ | |
411 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
412 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ | |
413 | ||
414 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 415 | #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
04a85b3b | 416 | |
6d0f6bcf JCPV |
417 | #define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
418 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) | |
04a85b3b WD |
419 | |
420 | /* | |
421 | * Memory Periodic Timer Prescaler | |
422 | */ | |
423 | ||
424 | /* | |
425 | * Memory Periodic Timer Prescaler | |
426 | * | |
427 | * The Divider for PTA (refresh timer) configuration is based on an | |
428 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
429 | * the number of chip selects (NCS) and the actually needed refresh | |
430 | * rate is done by setting MPTPR. | |
431 | * | |
432 | * PTA is calculated from | |
433 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
434 | * | |
435 | * gclk CPU clock (not bus clock!) | |
436 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
437 | * | |
438 | * 4096 Rows from SDRAM example configuration | |
439 | * 1000 factor s -> ms | |
440 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
441 | * 4 Number of refresh cycles per period | |
442 | * 64 Refresh cycle in ms per number of rows | |
443 | * -------------------------------------------- | |
444 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
445 | * | |
446 | * 50 MHz => 50.000.000 / Divider = 98 | |
447 | * 66 Mhz => 66.000.000 / Divider = 129 | |
448 | * 80 Mhz => 80.000.000 / Divider = 156 | |
449 | */ | |
450 | ||
6d0f6bcf | 451 | #define CONFIG_SYS_MAMR_PTA 234 |
04a85b3b WD |
452 | |
453 | /* | |
454 | * For 16 MBit, refresh rates could be 31.3 us | |
455 | * (= 64 ms / 2K = 125 / quad bursts). | |
456 | * For a simpler initialization, 15.6 us is used instead. | |
457 | * | |
6d0f6bcf JCPV |
458 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
459 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
04a85b3b | 460 | */ |
6d0f6bcf JCPV |
461 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
462 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
04a85b3b WD |
463 | |
464 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
465 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
466 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
04a85b3b WD |
467 | |
468 | /* | |
469 | * MAMR settings for SDRAM | |
470 | */ | |
471 | ||
472 | /* 8 column SDRAM */ | |
6d0f6bcf | 473 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
04a85b3b WD |
474 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
475 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
476 | ||
477 | /* 9 column SDRAM */ | |
6d0f6bcf | 478 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
04a85b3b WD |
479 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
480 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
481 | ||
482 | /* | |
483 | * Internal Definitions | |
484 | * | |
485 | * Boot Flags | |
486 | */ | |
487 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
488 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
489 | ||
04a85b3b WD |
490 | #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ |
491 | ||
492 | /****************************************************************/ | |
493 | ||
494 | #define DSP_SIZE 0x00010000 /* 64K */ | |
495 | #define NAND_SIZE 0x00010000 /* 64K */ | |
04a85b3b WD |
496 | |
497 | #define DSP_BASE 0xF1000000 | |
498 | #define NAND_BASE 0xF1010000 | |
04a85b3b WD |
499 | |
500 | /****************************************************************/ | |
501 | ||
502 | /* NAND */ | |
cc4a0cee | 503 | #define CONFIG_NAND_LEGACY |
6d0f6bcf | 504 | #define CONFIG_SYS_NAND_BASE NAND_BASE |
04a85b3b | 505 | #define CONFIG_MTD_NAND_ECC_JFFS2 |
79fa88f3 WD |
506 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
507 | #define CONFIG_MTD_NAND_UNSAFE | |
04a85b3b | 508 | |
6d0f6bcf | 509 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
04a85b3b WD |
510 | |
511 | #define SECTORSIZE 512 | |
512 | #define ADDR_COLUMN 1 | |
513 | #define ADDR_PAGE 2 | |
514 | #define ADDR_COLUMN_PAGE 3 | |
53677ef1 | 515 | #define NAND_ChipID_UNKNOWN 0x00 |
04a85b3b WD |
516 | #define NAND_MAX_FLOORS 1 |
517 | #define NAND_MAX_CHIPS 1 | |
518 | ||
519 | /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ | |
520 | #define NAND_DISABLE_CE(nand) \ | |
521 | do { \ | |
6d0f6bcf | 522 | (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \ |
04a85b3b WD |
523 | } while(0) |
524 | ||
525 | #define NAND_ENABLE_CE(nand) \ | |
526 | do { \ | |
6d0f6bcf | 527 | (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \ |
04a85b3b WD |
528 | } while(0) |
529 | ||
530 | #define NAND_CTL_CLRALE(nandptr) \ | |
531 | do { \ | |
6d0f6bcf | 532 | (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \ |
04a85b3b WD |
533 | } while(0) |
534 | ||
535 | #define NAND_CTL_SETALE(nandptr) \ | |
536 | do { \ | |
6d0f6bcf | 537 | (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \ |
04a85b3b WD |
538 | } while(0) |
539 | ||
540 | #define NAND_CTL_CLRCLE(nandptr) \ | |
541 | do { \ | |
6d0f6bcf | 542 | (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \ |
04a85b3b WD |
543 | } while(0) |
544 | ||
545 | #define NAND_CTL_SETCLE(nandptr) \ | |
546 | do { \ | |
6d0f6bcf | 547 | (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \ |
04a85b3b WD |
548 | } while(0) |
549 | ||
c26e454d | 550 | #if CONFIG_NETPHONE_VERSION == 1 |
04a85b3b WD |
551 | #define NAND_WAIT_READY(nand) \ |
552 | do { \ | |
c26e454d | 553 | int _tries = 0; \ |
6d0f6bcf | 554 | while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \ |
c26e454d WD |
555 | if (++_tries > 100000) \ |
556 | break; \ | |
557 | } while (0) | |
558 | #elif CONFIG_NETPHONE_VERSION == 2 | |
559 | #define NAND_WAIT_READY(nand) \ | |
560 | do { \ | |
561 | int _tries = 0; \ | |
6d0f6bcf | 562 | while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \ |
c26e454d WD |
563 | if (++_tries > 100000) \ |
564 | break; \ | |
04a85b3b | 565 | } while (0) |
c26e454d | 566 | #endif |
04a85b3b WD |
567 | |
568 | #define WRITE_NAND_COMMAND(d, adr) \ | |
569 | do { \ | |
570 | *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ | |
571 | } while(0) | |
572 | ||
573 | #define WRITE_NAND_ADDRESS(d, adr) \ | |
574 | do { \ | |
575 | *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ | |
576 | } while(0) | |
577 | ||
578 | #define WRITE_NAND(d, adr) \ | |
579 | do { \ | |
580 | *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ | |
581 | } while(0) | |
582 | ||
583 | #define READ_NAND(adr) \ | |
584 | ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) | |
585 | ||
586 | /*****************************************************************************/ | |
587 | ||
6d0f6bcf JCPV |
588 | #define CONFIG_SYS_DIRECT_FLASH_TFTP |
589 | #define CONFIG_SYS_DIRECT_NAND_TFTP | |
79fa88f3 WD |
590 | |
591 | /*****************************************************************************/ | |
592 | ||
c26e454d | 593 | #if CONFIG_NETPHONE_VERSION == 1 |
04a85b3b | 594 | #define STATUS_LED_BIT 0x00000008 /* bit 28 */ |
c26e454d WD |
595 | #elif CONFIG_NETPHONE_VERSION == 2 |
596 | #define STATUS_LED_BIT 0x00000080 /* bit 24 */ | |
597 | #endif | |
598 | ||
6d0f6bcf | 599 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
04a85b3b WD |
600 | #define STATUS_LED_STATE STATUS_LED_BLINKING |
601 | ||
602 | #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ | |
603 | #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ | |
604 | ||
605 | #ifndef __ASSEMBLY__ | |
606 | ||
607 | /* LEDs */ | |
608 | ||
609 | /* led_id_t is unsigned int mask */ | |
610 | typedef unsigned int led_id_t; | |
611 | ||
612 | #define __led_toggle(_msk) \ | |
613 | do { \ | |
6d0f6bcf | 614 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \ |
04a85b3b WD |
615 | } while(0) |
616 | ||
617 | #define __led_set(_msk, _st) \ | |
618 | do { \ | |
619 | if ((_st)) \ | |
6d0f6bcf | 620 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \ |
04a85b3b | 621 | else \ |
6d0f6bcf | 622 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ |
04a85b3b WD |
623 | } while(0) |
624 | ||
625 | #define __led_init(msk, st) __led_set(msk, st) | |
626 | ||
627 | #endif | |
628 | ||
629 | /*********************************************************************************************************** | |
630 | ||
c26e454d WD |
631 | ---------------------------------------------------------------------------------------------- |
632 | ||
633 | (V1) version 1 of the board | |
634 | (V2) version 2 of the board | |
635 | ||
636 | ---------------------------------------------------------------------------------------------- | |
637 | ||
04a85b3b WD |
638 | Pin definitions: |
639 | ||
640 | +------+----------------+--------+------------------------------------------------------------ | |
641 | | # | Name | Type | Comment | |
642 | +------+----------------+--------+------------------------------------------------------------ | |
643 | | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select | |
644 | | PA7 | DSP_INT | Output | DSP interrupt | |
645 | | PA10 | DSP_RESET | Output | DSP reset | |
646 | | PA14 | USBOE | Output | USB (1) | |
647 | | PA15 | USBRXD | Output | USB (1) | |
648 | | PB19 | BT_RTS | Output | Bluetooth (0) | |
649 | | PB23 | BT_CTS | Output | Bluetooth (0) | |
650 | | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select | |
651 | | PB27 | SPICS_DISP | Output | Display chip select | |
652 | | PB28 | SPI_RXD_3V | Input | SPI Data Rx | |
653 | | PB29 | SPI_TXD | Output | SPI Data Tx | |
654 | | PB30 | SPI_CLK | Output | SPI Clock | |
655 | | PC10 | DISPA0 | Output | Display A0 | |
656 | | PC11 | BACKLIGHT | Output | Display backlit | |
c26e454d WD |
657 | | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD |
658 | | | IO_RESET | Output | (V2) General I/O reset | |
659 | | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) | |
660 | | | HOOK | Input | (V2) Hook input interrupt | |
661 | | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK | |
662 | | | F_RY_BY | Input | (V2) NAND F_RY_BY | |
04a85b3b WD |
663 | | PE17 | F_ALE | Output | NAND F_ALE |
664 | | PE18 | F_CLE | Output | NAND F_CLE | |
665 | | PE20 | F_CE | Output | NAND F_CE | |
c26e454d WD |
666 | | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select |
667 | | | LED | Output | (V2) LED | |
04a85b3b | 668 | | PE27 | SPICS_ER | Output | External serial register CS |
c26e454d WD |
669 | | PE28 | LEDIO1 | Output | (V1) LED |
670 | | | BKBR1 | Input | (V2) Keyboard input scan | |
671 | | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) | |
672 | | | BKBR2 | Input | (V2) Keyboard input scan | |
673 | | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) | |
674 | | | BKBR3 | Input | (V2) Keyboard input scan | |
675 | | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY | |
676 | | | BKBR4 | Input | (V2) Keyboard input scan | |
04a85b3b WD |
677 | +------+----------------+--------+--------------------------------------------------- |
678 | ||
c26e454d WD |
679 | ---------------------------------------------------------------------------------------------- |
680 | ||
681 | Serial register input: | |
682 | ||
683 | +------+----------------+------------------------------------------------------------ | |
684 | | # | Name | Comment | |
685 | +------+----------------+------------------------------------------------------------ | |
6e592385 WD |
686 | | 0 | BKBR1 | (V1) Keyboard input scan |
687 | | 1 | BKBR3 | (V1) Keyboard input scan | |
688 | | 2 | BKBR4 | (V1) Keyboard input scan | |
689 | | 3 | BKBR2 | (V1) Keyboard input scan | |
690 | | 4 | HOOK | (V1) Hook switch | |
c26e454d WD |
691 | | 5 | BT_LINK | (V1) Bluetooth link status |
692 | | 6 | HOST_WAKE | (V1) Bluetooth host wake up | |
693 | | 7 | OK_ETH | (V1) Cisco inline power OK status | |
694 | +------+----------------+------------------------------------------------------------ | |
695 | ||
696 | ---------------------------------------------------------------------------------------------- | |
697 | ||
698 | Serial register output: | |
699 | ||
700 | +------+----------------+------------------------------------------------------------ | |
701 | | # | Name | Comment | |
702 | +------+----------------+------------------------------------------------------------ | |
6e592385 WD |
703 | | 0 | KEY1 | Keyboard output scan |
704 | | 1 | KEY2 | Keyboard output scan | |
705 | | 2 | KEY3 | Keyboard output scan | |
706 | | 3 | KEY4 | Keyboard output scan | |
707 | | 4 | KEY5 | Keyboard output scan | |
708 | | 5 | KEY6 | Keyboard output scan | |
709 | | 6 | KEY7 | Keyboard output scan | |
c26e454d WD |
710 | | 7 | BT_WAKE | Bluetooth wake up |
711 | +------+----------------+------------------------------------------------------------ | |
712 | ||
713 | ---------------------------------------------------------------------------------------------- | |
714 | ||
04a85b3b WD |
715 | Chip selects: |
716 | ||
717 | +------+----------------+------------------------------------------------------------ | |
718 | | # | Name | Comment | |
719 | +------+----------------+------------------------------------------------------------ | |
720 | | CS0 | CS0 | Boot flash | |
721 | | CS1 | CS_FLASH | NAND flash | |
722 | | CS2 | CS_DSP | DSP | |
723 | | CS3 | DCS_DRAM | DRAM | |
c26e454d | 724 | | CS4 | CS_FLASH2 | (V2) 2nd flash |
04a85b3b WD |
725 | +------+----------------+------------------------------------------------------------ |
726 | ||
c26e454d WD |
727 | ---------------------------------------------------------------------------------------------- |
728 | ||
04a85b3b WD |
729 | Interrupts: |
730 | ||
731 | +------+----------------+------------------------------------------------------------ | |
732 | | # | Name | Comment | |
733 | +------+----------------+------------------------------------------------------------ | |
734 | | IRQ1 | IRQ_DSP | DSP interrupt | |
735 | | IRQ3 | S_INTER | DUSLIC ??? | |
736 | | IRQ4 | F_RY_BY | NAND | |
737 | | IRQ7 | IRQ_MAX | MAX 3100 interrupt | |
738 | +------+----------------+------------------------------------------------------------ | |
739 | ||
c26e454d WD |
740 | ---------------------------------------------------------------------------------------------- |
741 | ||
04a85b3b WD |
742 | Interrupts on PCMCIA pins: |
743 | ||
744 | +------+----------------+------------------------------------------------------------ | |
745 | | # | Name | Comment | |
746 | +------+----------------+------------------------------------------------------------ | |
747 | | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface | |
748 | | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface | |
749 | | IP_A2| RMII1_MDINT | PHY interrupt for #1 | |
750 | | IP_A3| RMII2_MDINT | PHY interrupt for #2 | |
c26e454d WD |
751 | | IP_A5| HOST_WAKE | (V2) Bluetooth host wake |
752 | | IP_A6| OK_ETH | (V2) Cisco inline power OK | |
04a85b3b WD |
753 | +------+----------------+------------------------------------------------------------ |
754 | ||
755 | *************************************************************************************************/ | |
756 | ||
757 | #define CONFIG_SED156X 1 /* use SED156X */ | |
758 | #define CONFIG_SED156X_PG12864Q 1 /* type of display used */ | |
759 | ||
760 | /* serial interfacing macros */ | |
761 | ||
6d0f6bcf | 762 | #define SED156X_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
04a85b3b WD |
763 | #define SED156X_SPI_RXD_MASK 0x00000008 |
764 | ||
6d0f6bcf | 765 | #define SED156X_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
04a85b3b WD |
766 | #define SED156X_SPI_TXD_MASK 0x00000004 |
767 | ||
6d0f6bcf | 768 | #define SED156X_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
04a85b3b WD |
769 | #define SED156X_SPI_CLK_MASK 0x00000002 |
770 | ||
6d0f6bcf | 771 | #define SED156X_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
04a85b3b WD |
772 | #define SED156X_CS_MASK 0x00000010 |
773 | ||
6d0f6bcf | 774 | #define SED156X_A0_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) |
04a85b3b WD |
775 | #define SED156X_A0_MASK 0x0020 |
776 | ||
777 | /*************************************************************************************************/ | |
778 | ||
6d0f6bcf JCPV |
779 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
780 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 | |
781 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 | |
04a85b3b WD |
782 | |
783 | /*************************************************************************************************/ | |
784 | ||
785 | /* use board specific hardware */ | |
786 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
787 | #define CONFIG_HW_WATCHDOG | |
788 | #define CONFIG_SHOW_ACTIVITY | |
789 | ||
790 | /*************************************************************************************************/ | |
791 | ||
792 | /* phone console configuration */ | |
793 | ||
6d0f6bcf | 794 | #define PHONE_CONSOLE_POLL_HZ (CONFIG_SYS_HZ/200) /* poll every 5ms */ |
04a85b3b WD |
795 | |
796 | /*************************************************************************************************/ | |
797 | ||
798 | #define CONFIG_CDP_DEVICE_ID 20 | |
799 | #define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */ | |
800 | #define CONFIG_CDP_PORT_ID "eth%d" | |
801 | #define CONFIG_CDP_CAPABILITIES 0x00000010 | |
802 | #define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__ | |
803 | #define CONFIG_CDP_PLATFORM "Intracom NetPhone" | |
804 | #define CONFIG_CDP_TRIGGER 0x20020001 | |
805 | #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ | |
806 | #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */ | |
807 | ||
808 | /*************************************************************************************************/ | |
809 | ||
810 | #define CONFIG_AUTO_COMPLETE 1 | |
811 | ||
812 | /*************************************************************************************************/ | |
813 | ||
c26e454d WD |
814 | #define CONFIG_CRC32_VERIFY 1 |
815 | ||
816 | /*************************************************************************************************/ | |
817 | ||
818 | #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 | |
819 | ||
820 | /*************************************************************************************************/ | |
04a85b3b | 821 | #endif /* __CONFIG_H */ |