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feb7838f | 1 | /* |
28a096e7 | 2 | * Copyright 2007-2011 Freescale Semiconductor, Inc. |
feb7838f SS |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * p2020ds board configuration file | |
25 | * | |
26 | */ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
ebf9d526 KG |
30 | #include "../board/freescale/common/ics307_clk.h" |
31 | ||
d24f2d32 | 32 | #ifdef CONFIG_36BIT |
a0f9e0e0 KG |
33 | #define CONFIG_PHYS_64BIT |
34 | #endif | |
35 | ||
1ac63e40 JH |
36 | #ifdef CONFIG_SDCARD |
37 | #define CONFIG_SYS_RAMBOOT | |
38 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
39 | #define CONFIG_SYS_TEXT_BASE 0xf8f80000 | |
40 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc | |
41 | #endif | |
42 | ||
21dd9af3 JH |
43 | #ifdef CONFIG_SPIFLASH |
44 | #define CONFIG_SYS_RAMBOOT | |
45 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
46 | #define CONFIG_SYS_TEXT_BASE 0xf8f80000 | |
47 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc | |
48 | #endif | |
49 | ||
feb7838f SS |
50 | /* High Level Configuration Options */ |
51 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
52 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
53 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
54 | #define CONFIG_P2020 1 | |
55 | #define CONFIG_P2020DS 1 | |
56 | #define CONFIG_MP 1 /* support multiple processors */ | |
feb7838f | 57 | |
2ae18241 WD |
58 | #ifndef CONFIG_SYS_TEXT_BASE |
59 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
60 | #endif | |
61 | ||
7a577fda KG |
62 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
63 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
64 | #endif | |
65 | ||
28a096e7 LY |
66 | #define CONFIG_SYS_SRIO |
67 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
68 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
69 | ||
feb7838f SS |
70 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
71 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ | |
72 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
73 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
74 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
75 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
76 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
77 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
78 | ||
79 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
29c35182 | 80 | #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ |
feb7838f SS |
81 | |
82 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
83 | #define CONFIG_ENV_OVERWRITE | |
84 | ||
ebf9d526 KG |
85 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
86 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ | |
feb7838f | 87 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
feb7838f SS |
88 | |
89 | /* | |
90 | * These can be toggled for performance analysis, otherwise use default. | |
91 | */ | |
92 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
93 | #define CONFIG_BTB /* toggle branch predition */ | |
94 | ||
9c4d8767 JH |
95 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ |
96 | ||
feb7838f SS |
97 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
98 | ||
99 | #ifdef CONFIG_PHYS_64BIT | |
100 | #define CONFIG_ADDR_MAP 1 | |
101 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
102 | #endif | |
103 | ||
84bc0030 YS |
104 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
105 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
106 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
feb7838f SS |
107 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
108 | ||
1ac63e40 JH |
109 | /* |
110 | * Config the L2 Cache | |
111 | */ | |
112 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
113 | #ifdef CONFIG_PHYS_64BIT | |
114 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
115 | #else | |
116 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
117 | #endif | |
118 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
119 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
120 | ||
e46fedfe TT |
121 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
122 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
feb7838f | 123 | |
feb7838f | 124 | /* DDR Setup */ |
feb7838f | 125 | #define CONFIG_VERY_BIG_RAM |
d24f2d32 | 126 | #ifdef CONFIG_DDR2 |
394c46ca YS |
127 | #define CONFIG_FSL_DDR2 |
128 | #else | |
feb7838f | 129 | #define CONFIG_FSL_DDR3 1 |
394c46ca | 130 | #endif |
feb7838f SS |
131 | #undef CONFIG_FSL_DDR_INTERACTIVE |
132 | ||
8e5e9b94 WD |
133 | /* ECC will be enabled based on perf_mode environment variable */ |
134 | /* #define CONFIG_DDR_ECC */ | |
135 | ||
feb7838f SS |
136 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
137 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
138 | ||
139 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
140 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
141 | ||
142 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
143 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
144 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
145 | ||
146 | /* I2C addresses of SPD EEPROMs */ | |
394c46ca | 147 | #define CONFIG_DDR_SPD |
feb7838f | 148 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ |
c39f44dc | 149 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
feb7838f SS |
150 | |
151 | /* These are used when DDR doesn't use SPD. */ | |
feb7838f SS |
152 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ |
153 | ||
154 | /* Default settings for "stable" mode */ | |
155 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
156 | #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 | |
157 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
158 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 | |
159 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
160 | #define CONFIG_SYS_DDR_TIMING_0 0x00330804 | |
161 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 | |
162 | #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 | |
163 | #define CONFIG_SYS_DDR_MODE_1 0x00421422 | |
164 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
165 | #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 | |
166 | #define CONFIG_SYS_DDR_INTERVAL 0x61800100 | |
167 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
168 | #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 | |
169 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
170 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
171 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 | |
172 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 | |
173 | #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ | |
174 | #define CONFIG_SYS_DDR_CONTROL2 0x24400011 | |
175 | #define CONFIG_SYS_DDR_CDR1 0x00040000 | |
176 | #define CONFIG_SYS_DDR_CDR2 0x00000000 | |
177 | ||
178 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
179 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
180 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
181 | ||
182 | /* Settings that differ for "performance" mode */ | |
183 | #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ | |
184 | #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ | |
185 | #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 | |
186 | #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 | |
187 | #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce | |
188 | #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ | |
189 | ||
190 | /* | |
191 | * The following set of values were tested for DDR2 | |
192 | * with a DDR3 to DDR2 interposer | |
193 | * | |
194 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
195 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
196 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 | |
197 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
198 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
199 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
200 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 | |
201 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
202 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
203 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
204 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
205 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 | |
206 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 | |
207 | * | |
208 | */ | |
209 | ||
210 | #undef CONFIG_CLOCKS_IN_MHZ | |
211 | ||
212 | /* | |
213 | * Memory map | |
214 | * | |
215 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
216 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
217 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
218 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
219 | * | |
220 | * Localbus cacheable (TBD) | |
221 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
222 | * | |
223 | * Localbus non-cacheable | |
224 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
225 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
226 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable | |
227 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 | |
228 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
229 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
230 | */ | |
231 | ||
232 | /* | |
233 | * Local Bus Definitions | |
234 | */ | |
235 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ | |
236 | #ifdef CONFIG_PHYS_64BIT | |
237 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
238 | #else | |
239 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
240 | #endif | |
241 | ||
242 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) | |
243 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 | |
244 | ||
245 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
246 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
247 | ||
248 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
249 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
250 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
251 | ||
252 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
253 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
254 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
255 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
256 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
257 | ||
14d0a02a | 258 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
feb7838f SS |
259 | |
260 | #define CONFIG_FLASH_CFI_DRIVER | |
261 | #define CONFIG_SYS_FLASH_CFI | |
262 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
263 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
264 | ||
265 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
266 | ||
394c46ca | 267 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
5a469608 TT |
268 | #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ |
269 | ||
270 | #ifdef CONFIG_FSL_NGPIXIS | |
feb7838f SS |
271 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
272 | #ifdef CONFIG_PHYS_64BIT | |
273 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
274 | #else | |
275 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
276 | #endif | |
277 | ||
278 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
279 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
280 | ||
5a469608 TT |
281 | #define PIXIS_LBMAP_SWITCH 7 |
282 | #define PIXIS_LBMAP_MASK 0xf0 | |
283 | #define PIXIS_LBMAP_SHIFT 4 | |
284 | #define PIXIS_LBMAP_ALTBANK 0x20 | |
285 | #endif | |
feb7838f SS |
286 | |
287 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
288 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
d51cc7a0 YS |
289 | #ifdef CONFIG_PHYS_64BIT |
290 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
291 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
292 | /* The assembler doesn't like typecast */ | |
293 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
294 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
295 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
296 | #else | |
297 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
298 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
299 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
300 | #endif | |
553f0982 | 301 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
feb7838f | 302 | |
25ddd1fb | 303 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
feb7838f SS |
304 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
305 | ||
306 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
307 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
308 | ||
309 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
310 | #ifdef CONFIG_PHYS_64BIT | |
311 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
312 | #else | |
313 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
314 | #endif | |
315 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ | |
316 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
317 | CONFIG_SYS_NAND_BASE + 0x80000,\ | |
318 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
319 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
320 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
321 | #define CONFIG_CMD_NAND 1 | |
322 | #define CONFIG_NAND_FSL_ELBC 1 | |
323 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
324 | ||
325 | /* NAND flash config */ | |
a3055c58 | 326 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
feb7838f SS |
327 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
328 | | BR_PS_8 /* Port Size = 8bit */ \ | |
329 | | BR_MS_FCM /* MSEL = FCM */ \ | |
330 | | BR_V) /* valid */ | |
a3055c58 | 331 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
feb7838f SS |
332 | | OR_FCM_PGS /* Large Page*/ \ |
333 | | OR_FCM_CSCT \ | |
334 | | OR_FCM_CST \ | |
335 | | OR_FCM_CHT \ | |
336 | | OR_FCM_SCY_1 \ | |
337 | | OR_FCM_TRLX \ | |
338 | | OR_FCM_EHTR) | |
339 | ||
340 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
341 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
a3055c58 MM |
342 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
343 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
feb7838f SS |
344 | |
345 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | |
346 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
347 | | BR_PS_8 /* Port Size = 8bit */ \ | |
348 | | BR_MS_FCM /* MSEL = FCM */ \ | |
349 | | BR_V) /* valid */ | |
a3055c58 | 350 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
feb7838f SS |
351 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ |
352 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
353 | | BR_PS_8 /* Port Size = 8bit */ \ | |
354 | | BR_MS_FCM /* MSEL = FCM */ \ | |
355 | | BR_V) /* valid */ | |
a3055c58 | 356 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
feb7838f SS |
357 | |
358 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | |
359 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
360 | | BR_PS_8 /* Port Size = 8bit */ \ | |
361 | | BR_MS_FCM /* MSEL = FCM */ \ | |
362 | | BR_V) /* valid */ | |
a3055c58 | 363 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
feb7838f SS |
364 | |
365 | /* Serial Port - controlled on board with jumper J8 | |
366 | * open - index 2 | |
367 | * shorted - index 1 | |
368 | */ | |
369 | #define CONFIG_CONS_INDEX 1 | |
feb7838f SS |
370 | #define CONFIG_SYS_NS16550 |
371 | #define CONFIG_SYS_NS16550_SERIAL | |
372 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
373 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
374 | ||
375 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
376 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
377 | ||
378 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
379 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
380 | ||
381 | /* Use the HUSH parser */ | |
382 | #define CONFIG_SYS_HUSH_PARSER | |
383 | #ifdef CONFIG_SYS_HUSH_PARSER | |
384 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
385 | #endif | |
386 | ||
387 | /* | |
388 | * Pass open firmware flat tree | |
389 | */ | |
390 | #define CONFIG_OF_LIBFDT 1 | |
391 | #define CONFIG_OF_BOARD_SETUP 1 | |
392 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
393 | ||
feb7838f SS |
394 | /* I2C */ |
395 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
396 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
397 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
398 | #define CONFIG_I2C_MULTI_BUS | |
feb7838f SS |
399 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
400 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
401 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
402 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ | |
403 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
404 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
405 | ||
406 | /* | |
407 | * I2C2 EEPROM | |
408 | */ | |
409 | #define CONFIG_ID_EEPROM | |
410 | #ifdef CONFIG_ID_EEPROM | |
411 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
412 | #endif | |
413 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
414 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
415 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
416 | ||
21dd9af3 JH |
417 | /* |
418 | * eSPI - Enhanced SPI | |
419 | */ | |
420 | #define CONFIG_FSL_ESPI | |
421 | ||
422 | #define CONFIG_SPI_FLASH | |
423 | #define CONFIG_SPI_FLASH_SPANSION | |
424 | ||
425 | #define CONFIG_CMD_SF | |
426 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
427 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
428 | ||
feb7838f SS |
429 | /* |
430 | * General PCI | |
431 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
432 | */ | |
433 | ||
434 | /* controller 3, Slot 1, tgtid 3, Base address b000 */ | |
4d5723da | 435 | #define CONFIG_SYS_PCIE3_NAME "Slot 1" |
feb7838f SS |
436 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
437 | #ifdef CONFIG_PHYS_64BIT | |
156984a3 | 438 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
feb7838f SS |
439 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
440 | #else | |
441 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 | |
442 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 | |
443 | #endif | |
444 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
445 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 | |
446 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
447 | #ifdef CONFIG_PHYS_64BIT | |
448 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull | |
449 | #else | |
450 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 | |
451 | #endif | |
452 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
453 | ||
454 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
4d5723da | 455 | #define CONFIG_SYS_PCIE2_NAME "ULI" |
feb7838f SS |
456 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
457 | #ifdef CONFIG_PHYS_64BIT | |
156984a3 | 458 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
feb7838f SS |
459 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
460 | #else | |
461 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
462 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
463 | #endif | |
464 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
465 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
466 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
467 | #ifdef CONFIG_PHYS_64BIT | |
468 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
469 | #else | |
470 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
471 | #endif | |
472 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
473 | ||
474 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
4d5723da | 475 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
feb7838f SS |
476 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
477 | #ifdef CONFIG_PHYS_64BIT | |
156984a3 | 478 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
feb7838f SS |
479 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
480 | #else | |
481 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 | |
482 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 | |
483 | #endif | |
484 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
485 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 | |
486 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
487 | #ifdef CONFIG_PHYS_64BIT | |
488 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull | |
489 | #else | |
490 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 | |
491 | #endif | |
492 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
493 | ||
494 | #if defined(CONFIG_PCI) | |
495 | ||
496 | /*PCIE video card used*/ | |
497 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT | |
498 | ||
499 | /* video */ | |
500 | #define CONFIG_VIDEO | |
501 | ||
502 | #if defined(CONFIG_VIDEO) | |
503 | #define CONFIG_BIOSEMU | |
504 | #define CONFIG_CFB_CONSOLE | |
505 | #define CONFIG_VIDEO_SW_CURSOR | |
506 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
507 | #define CONFIG_ATI_RADEON_FB | |
508 | #define CONFIG_VIDEO_LOGO | |
509 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
510 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
511 | #endif | |
512 | ||
28a096e7 LY |
513 | /* SRIO1 uses the same window as PCIE2 mem window */ |
514 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
515 | #ifdef CONFIG_PHYS_64BIT | |
516 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull | |
517 | #else | |
518 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 | |
519 | #endif | |
520 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ | |
521 | ||
522 | /* SRIO2 uses the same window as PCIE1 mem window */ | |
523 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000 | |
524 | #ifdef CONFIG_PHYS_64BIT | |
525 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull | |
526 | #else | |
527 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000 | |
528 | #endif | |
529 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */ | |
530 | ||
feb7838f SS |
531 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
532 | ||
533 | #undef CONFIG_EEPRO100 | |
534 | #undef CONFIG_TULIP | |
535 | #define CONFIG_RTL8139 | |
536 | ||
feb7838f SS |
537 | #ifndef CONFIG_PCI_PNP |
538 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS | |
539 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS | |
540 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ | |
541 | #endif | |
542 | ||
543 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
544 | #define CONFIG_DOS_PARTITION | |
545 | #define CONFIG_SCSI_AHCI | |
546 | ||
547 | #ifdef CONFIG_SCSI_AHCI | |
548 | #define CONFIG_SATA_ULI5288 | |
549 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 | |
550 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
551 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
552 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
553 | #endif /* SCSI */ | |
554 | ||
555 | #endif /* CONFIG_PCI */ | |
556 | ||
557 | ||
558 | #if defined(CONFIG_TSEC_ENET) | |
559 | ||
feb7838f SS |
560 | #define CONFIG_MII 1 /* MII PHY management */ |
561 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
562 | #define CONFIG_TSEC1 1 | |
563 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
564 | #define CONFIG_TSEC2 1 | |
565 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
566 | #define CONFIG_TSEC3 1 | |
567 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
568 | ||
569 | #define CONFIG_PIXIS_SGMII_CMD | |
570 | #define CONFIG_FSL_SGMII_RISER 1 | |
571 | #define SGMII_RISER_PHY_OFFSET 0x1b | |
572 | ||
573 | #ifdef CONFIG_FSL_SGMII_RISER | |
574 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ | |
575 | #endif | |
576 | ||
577 | #define TSEC1_PHY_ADDR 0 | |
578 | #define TSEC2_PHY_ADDR 1 | |
579 | #define TSEC3_PHY_ADDR 2 | |
580 | ||
581 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
582 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
583 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
584 | ||
585 | #define TSEC1_PHYIDX 0 | |
586 | #define TSEC2_PHYIDX 0 | |
587 | #define TSEC3_PHYIDX 0 | |
588 | ||
589 | #define CONFIG_ETHPRIME "eTSEC1" | |
590 | ||
591 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
592 | #endif /* CONFIG_TSEC_ENET */ | |
593 | ||
594 | /* | |
595 | * Environment | |
596 | */ | |
1ac63e40 JH |
597 | #if defined(CONFIG_SDCARD) |
598 | #define CONFIG_ENV_IS_IN_MMC | |
599 | #define CONFIG_ENV_SIZE 0x2000 | |
600 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
21dd9af3 JH |
601 | #elif defined(CONFIG_SPIFLASH) |
602 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
603 | #define CONFIG_ENV_SPI_BUS 0 | |
604 | #define CONFIG_ENV_SPI_CS 0 | |
605 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
606 | #define CONFIG_ENV_SPI_MODE 0 | |
607 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
608 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
609 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
1ac63e40 | 610 | #else |
feb7838f SS |
611 | #define CONFIG_ENV_IS_IN_FLASH 1 |
612 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
613 | #define CONFIG_ENV_ADDR 0xfff80000 | |
614 | #else | |
615 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
616 | #endif | |
617 | #define CONFIG_ENV_SIZE 0x2000 | |
618 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
1ac63e40 | 619 | #endif |
feb7838f SS |
620 | |
621 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
622 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
623 | ||
624 | /* | |
625 | * Command line configuration. | |
626 | */ | |
627 | #include <config_cmd_default.h> | |
628 | ||
629 | #define CONFIG_CMD_IRQ | |
630 | #define CONFIG_CMD_PING | |
631 | #define CONFIG_CMD_I2C | |
632 | #define CONFIG_CMD_MII | |
633 | #define CONFIG_CMD_ELF | |
634 | #define CONFIG_CMD_IRQ | |
635 | #define CONFIG_CMD_SETEXPR | |
199e262e | 636 | #define CONFIG_CMD_REGINFO |
feb7838f SS |
637 | |
638 | #if defined(CONFIG_PCI) | |
639 | #define CONFIG_CMD_PCI | |
feb7838f SS |
640 | #define CONFIG_CMD_NET |
641 | #define CONFIG_CMD_SCSI | |
642 | #define CONFIG_CMD_EXT2 | |
643 | #endif | |
644 | ||
0ead6f2e RZ |
645 | /* |
646 | * USB | |
647 | */ | |
9c4d8767 JH |
648 | #define CONFIG_USB_EHCI |
649 | ||
650 | #ifdef CONFIG_USB_EHCI | |
0ead6f2e RZ |
651 | #define CONFIG_CMD_USB |
652 | #define CONFIG_USB_STORAGE | |
0ead6f2e RZ |
653 | #define CONFIG_USB_EHCI_FSL |
654 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
9c4d8767 | 655 | #endif |
0ead6f2e | 656 | |
feb7838f SS |
657 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
658 | ||
9c4d8767 JH |
659 | /* |
660 | * SDHC/MMC | |
661 | */ | |
662 | #define CONFIG_MMC | |
663 | ||
664 | #ifdef CONFIG_MMC | |
665 | #define CONFIG_FSL_ESDHC | |
666 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
667 | #define CONFIG_CMD_MMC | |
668 | #define CONFIG_GENERIC_MMC | |
669 | #endif | |
670 | ||
671 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
672 | #define CONFIG_CMD_EXT2 | |
673 | #define CONFIG_CMD_FAT | |
674 | #define CONFIG_DOS_PARTITION | |
675 | #endif | |
676 | ||
feb7838f SS |
677 | /* |
678 | * Miscellaneous configurable options | |
679 | */ | |
680 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
5be58f5f KP |
681 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
682 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
feb7838f SS |
683 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
684 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
685 | #if defined(CONFIG_CMD_KGDB) | |
686 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
687 | #else | |
688 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
689 | #endif | |
690 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
691 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
692 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
693 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
694 | ||
695 | /* | |
696 | * For booting Linux, the board info and command line data | |
a832ac41 | 697 | * have to be in the first 64 MB of memory, since this is |
feb7838f SS |
698 | * the maximum mapped by the Linux kernel during initialization. |
699 | */ | |
a832ac41 KG |
700 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
701 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
feb7838f | 702 | |
feb7838f SS |
703 | #if defined(CONFIG_CMD_KGDB) |
704 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
705 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
706 | #endif | |
707 | ||
708 | /* | |
709 | * Environment Configuration | |
710 | */ | |
711 | ||
712 | /* The mac addresses for all ethernet interface */ | |
713 | #if defined(CONFIG_TSEC_ENET) | |
714 | #define CONFIG_HAS_ETH0 | |
feb7838f | 715 | #define CONFIG_HAS_ETH1 |
feb7838f | 716 | #define CONFIG_HAS_ETH2 |
feb7838f SS |
717 | #endif |
718 | ||
719 | #define CONFIG_IPADDR 192.168.1.254 | |
720 | ||
721 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 722 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 723 | #define CONFIG_BOOTFILE "uImage" |
feb7838f SS |
724 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
725 | ||
726 | #define CONFIG_SERVERIP 192.168.1.1 | |
727 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
728 | #define CONFIG_NETMASK 255.255.255.0 | |
729 | ||
730 | /* default location for tftp and bootm */ | |
731 | #define CONFIG_LOADADDR 1000000 | |
732 | ||
733 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
734 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
735 | ||
736 | #define CONFIG_BAUDRATE 115200 | |
737 | ||
738 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
ccc4a8d8 | 739 | "perf_mode=performance\0" \ |
68d4230c RM |
740 | "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ |
741 | "usb1:dr_mode=host,phy_type=ulpi\0" \ | |
feb7838f SS |
742 | "netdev=eth0\0" \ |
743 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
744 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
14d0a02a WD |
745 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
746 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
747 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
748 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
749 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
ccc4a8d8 LY |
750 | "satabootcmd=setenv bootargs root=/dev/$bdev rw " \ |
751 | "console=$consoledev,$baudrate $othbootargs;" \ | |
752 | "tftp $loadaddr $bootfile;" \ | |
753 | "tftp $fdtaddr $fdtfile;" \ | |
754 | "bootm $loadaddr - $fdtaddr" \ | |
feb7838f SS |
755 | "consoledev=ttyS0\0" \ |
756 | "ramdiskaddr=2000000\0" \ | |
757 | "ramdiskfile=p2020ds/ramdisk.uboot\0" \ | |
758 | "fdtaddr=c00000\0" \ | |
ccc4a8d8 | 759 | "othbootargs=cache-sram-size=0x10000\0" \ |
feb7838f | 760 | "fdtfile=p2020ds/p2020ds.dtb\0" \ |
ccc4a8d8 LY |
761 | "bdev=sda3\0" \ |
762 | "partition=scsi 0:0\0" | |
feb7838f SS |
763 | |
764 | #define CONFIG_HDBOOT \ | |
765 | "setenv bootargs root=/dev/$bdev rw " \ | |
766 | "console=$consoledev,$baudrate $othbootargs;" \ | |
ccc4a8d8 LY |
767 | "ext2load $partition $loadaddr $bootfile;" \ |
768 | "ext2load $partition $fdtaddr $fdtfile;" \ | |
feb7838f SS |
769 | "bootm $loadaddr - $fdtaddr" |
770 | ||
771 | #define CONFIG_NFSBOOTCOMMAND \ | |
772 | "setenv bootargs root=/dev/nfs rw " \ | |
773 | "nfsroot=$serverip:$rootpath " \ | |
774 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
775 | "console=$consoledev,$baudrate $othbootargs;" \ | |
776 | "tftp $loadaddr $bootfile;" \ | |
777 | "tftp $fdtaddr $fdtfile;" \ | |
778 | "bootm $loadaddr - $fdtaddr" | |
779 | ||
780 | #define CONFIG_RAMBOOTCOMMAND \ | |
781 | "setenv bootargs root=/dev/ram rw " \ | |
782 | "console=$consoledev,$baudrate $othbootargs;" \ | |
783 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
784 | "tftp $loadaddr $bootfile;" \ | |
785 | "tftp $fdtaddr $fdtfile;" \ | |
786 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
787 | ||
788 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
789 | ||
790 | #endif /* __CONFIG_H */ |