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Commit | Line | Data |
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4f1d1b7d | 1 | /* |
3d7506fa | 2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. |
4f1d1b7d | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
4f1d1b7d MH |
5 | */ |
6 | ||
7 | /* | |
8 | * P2041 RDB board configuration file | |
3e978f5d | 9 | * Also supports P2040 RDB |
4f1d1b7d MH |
10 | */ |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
4f1d1b7d MH |
14 | #ifdef CONFIG_RAMBOOT_PBL |
15 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
16 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
e4536f8e MY |
17 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg |
18 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg | |
4f1d1b7d MH |
19 | #endif |
20 | ||
461632bd | 21 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
ff65f126 | 22 | /* Set 1M boot space */ |
461632bd LG |
23 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) |
24 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
25 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
ff65f126 LG |
26 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
27 | #define CONFIG_SYS_NO_FLASH | |
28 | #endif | |
29 | ||
4f1d1b7d | 30 | /* High Level Configuration Options */ |
4f1d1b7d | 31 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
4f1d1b7d MH |
32 | #define CONFIG_MP /* support multiple processors */ |
33 | ||
34 | #ifndef CONFIG_SYS_TEXT_BASE | |
e222b1f3 | 35 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
4f1d1b7d MH |
36 | #endif |
37 | ||
38 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
39 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
40 | #endif | |
41 | ||
42 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
51370d56 | 43 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
4f1d1b7d | 44 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ |
737537ef | 45 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
b38eaec5 RD |
46 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
47 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
48 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
4f1d1b7d MH |
49 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
50 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
51 | ||
52 | #define CONFIG_SYS_SRIO | |
53 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
54 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
c8b28152 | 55 | #define CONFIG_SRIO_PCIE_BOOT_MASTER |
4d28db8a | 56 | #define CONFIG_SYS_DPAA_RMAN /* RMan */ |
4f1d1b7d | 57 | |
4f1d1b7d MH |
58 | #define CONFIG_ENV_OVERWRITE |
59 | ||
60 | #ifdef CONFIG_SYS_NO_FLASH | |
461632bd | 61 | #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
4f1d1b7d | 62 | #define CONFIG_ENV_IS_NOWHERE |
0f57f6a3 | 63 | #endif |
4f1d1b7d MH |
64 | #else |
65 | #define CONFIG_FLASH_CFI_DRIVER | |
66 | #define CONFIG_SYS_FLASH_CFI | |
0f57f6a3 | 67 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
4f1d1b7d MH |
68 | #endif |
69 | ||
70 | #if defined(CONFIG_SPIFLASH) | |
71 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
72 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
73 | #define CONFIG_ENV_SPI_BUS 0 | |
74 | #define CONFIG_ENV_SPI_CS 0 | |
75 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
76 | #define CONFIG_ENV_SPI_MODE 0 | |
77 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
78 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
79 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
80 | #elif defined(CONFIG_SDCARD) | |
81 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
82 | #define CONFIG_ENV_IS_IN_MMC | |
4394d0c2 | 83 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
4f1d1b7d MH |
84 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
85 | #define CONFIG_ENV_SIZE 0x2000 | |
e222b1f3 | 86 | #define CONFIG_ENV_OFFSET (512 * 1658) |
15c8c6c2 SX |
87 | #elif defined(CONFIG_NAND) |
88 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
89 | #define CONFIG_ENV_IS_IN_NAND | |
90 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
e222b1f3 | 91 | #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) |
461632bd | 92 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
ff65f126 LG |
93 | #define CONFIG_ENV_IS_IN_REMOTE |
94 | #define CONFIG_ENV_ADDR 0xffe20000 | |
95 | #define CONFIG_ENV_SIZE 0x2000 | |
0f57f6a3 | 96 | #elif defined(CONFIG_ENV_IS_NOWHERE) |
ff65f126 | 97 | #define CONFIG_ENV_SIZE 0x2000 |
4f1d1b7d MH |
98 | #else |
99 | #define CONFIG_ENV_IS_IN_FLASH | |
100 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ | |
101 | - CONFIG_ENV_SECT_SIZE) | |
102 | #define CONFIG_ENV_SIZE 0x2000 | |
103 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
104 | #endif | |
105 | ||
44d50f0b SX |
106 | #ifndef __ASSEMBLY__ |
107 | unsigned long get_board_sys_clk(unsigned long dummy); | |
108 | #endif | |
109 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
4f1d1b7d MH |
110 | |
111 | /* | |
112 | * These can be toggled for performance analysis, otherwise use default. | |
113 | */ | |
114 | #define CONFIG_SYS_CACHE_STASHING | |
cd420e0b MH |
115 | #define CONFIG_BACKSIDE_L2_CACHE |
116 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
4f1d1b7d MH |
117 | #define CONFIG_BTB /* toggle branch predition */ |
118 | ||
119 | #define CONFIG_ENABLE_36BIT_PHYS | |
120 | ||
121 | #ifdef CONFIG_PHYS_64BIT | |
122 | #define CONFIG_ADDR_MAP | |
123 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
124 | #endif | |
125 | ||
126 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ | |
127 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
128 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
129 | #define CONFIG_SYS_ALT_MEMTEST | |
130 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
131 | ||
132 | /* | |
133 | * Config the L3 Cache as L3 SRAM | |
134 | */ | |
135 | #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
136 | #ifdef CONFIG_PHYS_64BIT | |
137 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ | |
138 | CONFIG_RAMBOOT_TEXT_BASE) | |
139 | #else | |
140 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR | |
141 | #endif | |
142 | #define CONFIG_SYS_L3_SIZE (1024 << 10) | |
143 | #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) | |
144 | ||
4f1d1b7d MH |
145 | #ifdef CONFIG_PHYS_64BIT |
146 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
147 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
148 | #endif | |
149 | ||
150 | /* EEPROM */ | |
151 | #define CONFIG_ID_EEPROM | |
152 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
153 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
154 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
155 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
156 | ||
157 | /* | |
158 | * DDR Setup | |
159 | */ | |
160 | #define CONFIG_VERY_BIG_RAM | |
161 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
162 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
163 | ||
164 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
165 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
166 | ||
167 | #define CONFIG_DDR_SPD | |
4f1d1b7d MH |
168 | |
169 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
170 | #define SPD_EEPROM_ADDRESS 0x52 | |
171 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
172 | ||
173 | /* | |
174 | * Local Bus Definitions | |
175 | */ | |
176 | ||
177 | /* Set the local bus clock 1/8 of platform clock */ | |
178 | #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 | |
179 | ||
ca1b0b89 YS |
180 | /* |
181 | * This board doesn't have a promjet connector. | |
182 | * However, it uses commone corenet board LAW and TLB. | |
183 | * It is necessary to use the same start address with proper offset. | |
184 | */ | |
185 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 | |
4f1d1b7d | 186 | #ifdef CONFIG_PHYS_64BIT |
ca1b0b89 | 187 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull |
4f1d1b7d MH |
188 | #else |
189 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
190 | #endif | |
191 | ||
c9b2feaf | 192 | #define CONFIG_SYS_FLASH_BR_PRELIM \ |
ca1b0b89 YS |
193 | (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ |
194 | BR_PS_16 | BR_V) | |
c9b2feaf SX |
195 | #define CONFIG_SYS_FLASH_OR_PRELIM \ |
196 | ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | |
197 | | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) | |
4f1d1b7d MH |
198 | |
199 | #define CONFIG_FSL_CPLD | |
200 | #define CPLD_BASE 0xffdf0000 /* CPLD registers */ | |
201 | #ifdef CONFIG_PHYS_64BIT | |
202 | #define CPLD_BASE_PHYS 0xfffdf0000ull | |
203 | #else | |
204 | #define CPLD_BASE_PHYS CPLD_BASE | |
205 | #endif | |
206 | ||
207 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) | |
208 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
209 | ||
210 | #define PIXIS_LBMAP_SWITCH 7 | |
211 | #define PIXIS_LBMAP_MASK 0xf0 | |
212 | #define PIXIS_LBMAP_SHIFT 4 | |
213 | #define PIXIS_LBMAP_ALTBANK 0x40 | |
214 | ||
215 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
216 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
217 | ||
218 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
219 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
220 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ | |
221 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ | |
222 | ||
223 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
224 | ||
225 | #if defined(CONFIG_RAMBOOT_PBL) | |
226 | #define CONFIG_SYS_RAMBOOT | |
227 | #endif | |
228 | ||
c9b2feaf SX |
229 | #define CONFIG_NAND_FSL_ELBC |
230 | /* Nand Flash */ | |
231 | #ifdef CONFIG_NAND_FSL_ELBC | |
232 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
233 | #ifdef CONFIG_PHYS_64BIT | |
234 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
235 | #else | |
236 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
237 | #endif | |
238 | ||
239 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
240 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
c9b2feaf SX |
241 | #define CONFIG_CMD_NAND |
242 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
243 | ||
244 | /* NAND flash config */ | |
245 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
246 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
247 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
248 | | BR_MS_FCM /* MSEL = FCM */ \ | |
249 | | BR_V) /* valid */ | |
250 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
251 | | OR_FCM_PGS /* Large Page*/ \ | |
252 | | OR_FCM_CSCT \ | |
253 | | OR_FCM_CST \ | |
254 | | OR_FCM_CHT \ | |
255 | | OR_FCM_SCY_1 \ | |
256 | | OR_FCM_TRLX \ | |
257 | | OR_FCM_EHTR) | |
258 | ||
259 | #ifdef CONFIG_NAND | |
260 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
261 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
262 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
263 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
264 | #else | |
265 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
266 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
267 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
268 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
269 | #endif | |
270 | #else | |
271 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
272 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
273 | #endif /* CONFIG_NAND_FSL_ELBC */ | |
274 | ||
4f1d1b7d MH |
275 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
276 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
ca1b0b89 | 277 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} |
4f1d1b7d | 278 | |
4f1d1b7d MH |
279 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
280 | #define CONFIG_MISC_INIT_R | |
281 | ||
282 | #define CONFIG_HWCONFIG | |
283 | ||
284 | /* define to use L1 as initial stack */ | |
285 | #define CONFIG_L1_INIT_RAM | |
286 | #define CONFIG_SYS_INIT_RAM_LOCK | |
287 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
288 | #ifdef CONFIG_PHYS_64BIT | |
289 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
290 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
291 | /* The assembler doesn't like typecast */ | |
292 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
293 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
294 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
295 | #else | |
296 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR | |
297 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
298 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
299 | #endif | |
300 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
301 | ||
302 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
303 | GENERATED_GBL_DATA_SIZE) | |
304 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
305 | ||
9307cbab | 306 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
4f1d1b7d MH |
307 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
308 | ||
309 | /* Serial Port - controlled on board with jumper J8 | |
310 | * open - index 2 | |
311 | * shorted - index 1 | |
312 | */ | |
313 | #define CONFIG_CONS_INDEX 1 | |
4f1d1b7d MH |
314 | #define CONFIG_SYS_NS16550_SERIAL |
315 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
316 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
317 | ||
318 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
319 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
320 | ||
321 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
322 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
323 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
324 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
325 | ||
4f1d1b7d | 326 | /* I2C */ |
00f792e0 HS |
327 | #define CONFIG_SYS_I2C |
328 | #define CONFIG_SYS_I2C_FSL | |
329 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
330 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
2bd1aab0 | 331 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
00f792e0 HS |
332 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
333 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
2bd1aab0 | 334 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
4f1d1b7d MH |
335 | |
336 | /* | |
337 | * RapidIO | |
338 | */ | |
339 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
340 | #ifdef CONFIG_PHYS_64BIT | |
341 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull | |
342 | #else | |
343 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 | |
344 | #endif | |
345 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ | |
346 | ||
347 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 | |
348 | #ifdef CONFIG_PHYS_64BIT | |
349 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull | |
350 | #else | |
351 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 | |
352 | #endif | |
353 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ | |
354 | ||
ff65f126 LG |
355 | /* |
356 | * for slave u-boot IMAGE instored in master memory space, | |
357 | * PHYS must be aligned based on the SIZE | |
358 | */ | |
e4911815 LG |
359 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
360 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
361 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
362 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
ff65f126 LG |
363 | /* |
364 | * for slave UCODE and ENV instored in master memory space, | |
365 | * PHYS must be aligned based on the SIZE | |
366 | */ | |
e4911815 | 367 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
b5f7c873 LG |
368 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
369 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
ff65f126 LG |
370 | |
371 | /* slave core release by master*/ | |
b5f7c873 LG |
372 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 |
373 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
ff65f126 LG |
374 | |
375 | /* | |
461632bd | 376 | * SRIO_PCIE_BOOT - SLAVE |
ff65f126 | 377 | */ |
461632bd LG |
378 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
379 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
380 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
381 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
ff65f126 LG |
382 | #endif |
383 | ||
4f1d1b7d MH |
384 | /* |
385 | * eSPI - Enhanced SPI | |
386 | */ | |
4f1d1b7d MH |
387 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
388 | #define CONFIG_SF_DEFAULT_MODE 0 | |
389 | ||
390 | /* | |
391 | * General PCI | |
392 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
393 | */ | |
394 | ||
395 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
396 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
397 | #ifdef CONFIG_PHYS_64BIT | |
398 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
399 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
400 | #else | |
401 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
402 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
403 | #endif | |
404 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
405 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
406 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
407 | #ifdef CONFIG_PHYS_64BIT | |
408 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
409 | #else | |
410 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 | |
411 | #endif | |
412 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
413 | ||
414 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
415 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
416 | #ifdef CONFIG_PHYS_64BIT | |
417 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
418 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
419 | #else | |
420 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
421 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
422 | #endif | |
423 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
424 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
425 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
426 | #ifdef CONFIG_PHYS_64BIT | |
427 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
428 | #else | |
429 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 | |
430 | #endif | |
431 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
432 | ||
433 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
434 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 | |
435 | #ifdef CONFIG_PHYS_64BIT | |
436 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
437 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
438 | #else | |
439 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 | |
440 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 | |
441 | #endif | |
442 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
443 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
444 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
445 | #ifdef CONFIG_PHYS_64BIT | |
446 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
447 | #else | |
448 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 | |
449 | #endif | |
450 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
451 | ||
452 | /* Qman/Bman */ | |
453 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
454 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 | |
455 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
456 | #ifdef CONFIG_PHYS_64BIT | |
457 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
458 | #else | |
459 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
460 | #endif | |
461 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
3fa66db4 JL |
462 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
463 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
464 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
465 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
466 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
467 | CONFIG_SYS_BMAN_CENA_SIZE) | |
468 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
469 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
4f1d1b7d MH |
470 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
471 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
472 | #ifdef CONFIG_PHYS_64BIT | |
473 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
474 | #else | |
475 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
476 | #endif | |
477 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
3fa66db4 JL |
478 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
479 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
480 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
481 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
482 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
483 | CONFIG_SYS_QMAN_CENA_SIZE) | |
484 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
485 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
4f1d1b7d MH |
486 | |
487 | #define CONFIG_SYS_DPAA_FMAN | |
488 | #define CONFIG_SYS_DPAA_PME | |
489 | /* Default address of microcode for the Linux Fman driver */ | |
4f1d1b7d MH |
490 | #if defined(CONFIG_SPIFLASH) |
491 | /* | |
492 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
493 | * env, so we got 0x110000. | |
494 | */ | |
f2717b47 | 495 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH |
dcf1d774 | 496 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
4f1d1b7d MH |
497 | #elif defined(CONFIG_SDCARD) |
498 | /* | |
499 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
e222b1f3 PK |
500 | * about 825KB (1650 blocks), Env is stored after the image, and the env size is |
501 | * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. | |
4f1d1b7d | 502 | */ |
f2717b47 | 503 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
dcf1d774 | 504 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) |
4f1d1b7d | 505 | #elif defined(CONFIG_NAND) |
f2717b47 | 506 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
dcf1d774 | 507 | #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) |
461632bd | 508 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
ff65f126 LG |
509 | /* |
510 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
511 | * in two corenet boards, slave's ucode could be stored in master's memory | |
512 | * space, the address can be mapped from slave TLB->slave LAW-> | |
461632bd LG |
513 | * slave SRIO or PCIE outbound window->master inbound window-> |
514 | * master LAW->the ucode address in master's memory space. | |
ff65f126 LG |
515 | */ |
516 | #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE | |
dcf1d774 | 517 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
4f1d1b7d | 518 | #else |
f2717b47 | 519 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
dcf1d774 | 520 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
4f1d1b7d | 521 | #endif |
f2717b47 TT |
522 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
523 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
4f1d1b7d MH |
524 | |
525 | #ifdef CONFIG_SYS_DPAA_FMAN | |
526 | #define CONFIG_FMAN_ENET | |
0787ecc0 MH |
527 | #define CONFIG_PHYLIB_10G |
528 | #define CONFIG_PHY_VITESSE | |
529 | #define CONFIG_PHY_TERANETICS | |
4f1d1b7d MH |
530 | #endif |
531 | ||
532 | #ifdef CONFIG_PCI | |
842033e6 | 533 | #define CONFIG_PCI_INDIRECT_BRIDGE |
4f1d1b7d MH |
534 | |
535 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
4f1d1b7d MH |
536 | #endif /* CONFIG_PCI */ |
537 | ||
aa7f281c | 538 | /* SATA */ |
9760b274 ZRR |
539 | #define CONFIG_FSL_SATA_V2 |
540 | ||
541 | #ifdef CONFIG_FSL_SATA_V2 | |
aa7f281c | 542 | #define CONFIG_FSL_SATA |
3e0529f7 | 543 | #define CONFIG_LIBATA |
aa7f281c MH |
544 | |
545 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
546 | #define CONFIG_SATA1 | |
547 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
548 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
549 | #define CONFIG_SATA2 | |
550 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
551 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
552 | ||
553 | #define CONFIG_LBA48 | |
554 | #define CONFIG_CMD_SATA | |
aa7f281c MH |
555 | #endif |
556 | ||
4f1d1b7d MH |
557 | #ifdef CONFIG_FMAN_ENET |
558 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 | |
559 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 | |
560 | #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 | |
561 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 | |
562 | #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 | |
563 | ||
564 | #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c | |
565 | #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d | |
566 | #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e | |
567 | #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f | |
568 | ||
0787ecc0 MH |
569 | #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 |
570 | ||
4f1d1b7d MH |
571 | #define CONFIG_SYS_TBIPA_VALUE 8 |
572 | #define CONFIG_MII /* MII PHY management */ | |
573 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
574 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
575 | #endif | |
576 | ||
577 | /* | |
578 | * Environment | |
579 | */ | |
580 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
581 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
582 | ||
583 | /* | |
584 | * Command line configuration. | |
585 | */ | |
4f1d1b7d | 586 | #define CONFIG_CMD_ERRATA |
4f1d1b7d | 587 | #define CONFIG_CMD_IRQ |
4f1d1b7d MH |
588 | |
589 | #ifdef CONFIG_PCI | |
590 | #define CONFIG_CMD_PCI | |
4f1d1b7d MH |
591 | #endif |
592 | ||
593 | /* | |
594 | * USB | |
595 | */ | |
3d7506fa | 596 | #define CONFIG_HAS_FSL_DR_USB |
597 | #define CONFIG_HAS_FSL_MPH_USB | |
598 | ||
599 | #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) | |
4f1d1b7d MH |
600 | #define CONFIG_USB_EHCI |
601 | #define CONFIG_USB_EHCI_FSL | |
602 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
3d7506fa | 603 | #endif |
604 | ||
4f1d1b7d MH |
605 | #ifdef CONFIG_MMC |
606 | #define CONFIG_FSL_ESDHC | |
607 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
608 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
4f1d1b7d | 609 | #define CONFIG_GENERIC_MMC |
4f1d1b7d MH |
610 | #endif |
611 | ||
737537ef RG |
612 | /* Hash command with SHA acceleration supported in hardware */ |
613 | #ifdef CONFIG_FSL_CAAM | |
614 | #define CONFIG_CMD_HASH | |
615 | #define CONFIG_SHA_HW_ACCEL | |
616 | #endif | |
617 | ||
4f1d1b7d MH |
618 | /* |
619 | * Miscellaneous configurable options | |
620 | */ | |
621 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
622 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
623 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
624 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
4f1d1b7d MH |
625 | #ifdef CONFIG_CMD_KGDB |
626 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
627 | #else | |
628 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
629 | #endif | |
630 | /* Print Buffer Size */ | |
631 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
632 | sizeof(CONFIG_SYS_PROMPT)+16) | |
633 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
634 | /* Boot Argument Buffer Size */ | |
635 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
4f1d1b7d MH |
636 | |
637 | /* | |
638 | * For booting Linux, the board info and command line data | |
639 | * have to be in the first 64 MB of memory, since this is | |
640 | * the maximum mapped by the Linux kernel during initialization. | |
641 | */ | |
642 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ | |
643 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
644 | ||
645 | #ifdef CONFIG_CMD_KGDB | |
646 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
4f1d1b7d MH |
647 | #endif |
648 | ||
649 | /* | |
650 | * Environment Configuration | |
651 | */ | |
8b3637c6 | 652 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 653 | #define CONFIG_BOOTFILE "uImage" |
4f1d1b7d MH |
654 | #define CONFIG_UBOOTPATH u-boot.bin |
655 | ||
656 | /* default location for tftp and bootm */ | |
657 | #define CONFIG_LOADADDR 1000000 | |
658 | ||
4f1d1b7d MH |
659 | |
660 | #define CONFIG_BAUDRATE 115200 | |
661 | ||
662 | #define __USB_PHY_TYPE utmi | |
663 | ||
664 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
665 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ | |
666 | "bank_intlv=cs0_cs1\0" \ | |
667 | "netdev=eth0\0" \ | |
5368c55d MV |
668 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
669 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
4f1d1b7d MH |
670 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
671 | "protect off $ubootaddr +$filesize && " \ | |
672 | "erase $ubootaddr +$filesize && " \ | |
673 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
674 | "protect on $ubootaddr +$filesize && " \ | |
675 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
676 | "consoledev=ttyS0\0" \ | |
5368c55d | 677 | "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ |
4f1d1b7d MH |
678 | "usb_dr_mode=host\0" \ |
679 | "ramdiskaddr=2000000\0" \ | |
680 | "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ | |
b24a4f62 | 681 | "fdtaddr=1e00000\0" \ |
4f1d1b7d | 682 | "fdtfile=p2041rdb/p2041rdb.dtb\0" \ |
3246584d | 683 | "bdev=sda3\0" |
4f1d1b7d MH |
684 | |
685 | #define CONFIG_HDBOOT \ | |
686 | "setenv bootargs root=/dev/$bdev rw " \ | |
687 | "console=$consoledev,$baudrate $othbootargs;" \ | |
688 | "tftp $loadaddr $bootfile;" \ | |
689 | "tftp $fdtaddr $fdtfile;" \ | |
690 | "bootm $loadaddr - $fdtaddr" | |
691 | ||
692 | #define CONFIG_NFSBOOTCOMMAND \ | |
693 | "setenv bootargs root=/dev/nfs rw " \ | |
694 | "nfsroot=$serverip:$rootpath " \ | |
695 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
696 | "console=$consoledev,$baudrate $othbootargs;" \ | |
697 | "tftp $loadaddr $bootfile;" \ | |
698 | "tftp $fdtaddr $fdtfile;" \ | |
699 | "bootm $loadaddr - $fdtaddr" | |
700 | ||
701 | #define CONFIG_RAMBOOTCOMMAND \ | |
702 | "setenv bootargs root=/dev/ram rw " \ | |
703 | "console=$consoledev,$baudrate $othbootargs;" \ | |
704 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
705 | "tftp $loadaddr $bootfile;" \ | |
706 | "tftp $fdtaddr $fdtfile;" \ | |
707 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
708 | ||
709 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
710 | ||
4f1d1b7d | 711 | #include <asm/fsl_secure_boot.h> |
4f1d1b7d MH |
712 | |
713 | #endif /* __CONFIG_H */ |