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c609719b | 1 | /* |
76d1466f MF |
2 | * (C) Copyright 2007 |
3 | * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com | |
4 | * | |
a20b27a3 | 5 | * (C) Copyright 2001-2004 |
76d1466f | 6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
c609719b WD |
7 | * |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
28 | * board/config.h - configuration options, board specific | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
34 | /* | |
35 | * High Level Configuration Options | |
36 | * (easy to change) | |
37 | */ | |
c609719b | 38 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
c837dcb1 WD |
39 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
40 | #define CONFIG_PCI405 1 /* ...on a PCI405 board */ | |
c609719b | 41 | |
2ae18241 WD |
42 | #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 |
43 | ||
c837dcb1 | 44 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
c609719b WD |
45 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ |
46 | ||
c837dcb1 | 47 | #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ |
c609719b | 48 | |
a20b27a3 SR |
49 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
50 | ||
d69b100e | 51 | #define CONFIG_BAUDRATE 115200 |
a20b27a3 | 52 | #define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */ |
c609719b WD |
53 | |
54 | #undef CONFIG_BOOTARGS | |
a20b27a3 SR |
55 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
56 | "mem_linux=14336k\0" \ | |
57 | "optargs=panic=0\0" \ | |
58 | "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \ | |
76d1466f | 59 | "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ |
a20b27a3 | 60 | "" |
76d1466f | 61 | #define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci" |
a20b27a3 SR |
62 | |
63 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
c609719b | 64 | |
acf02697 JL |
65 | /* |
66 | * Command line configuration. | |
67 | */ | |
68 | #include <config_cmd_default.h> | |
69 | ||
24eea623 MF |
70 | #undef CONFIG_CMD_IMLS |
71 | #undef CONFIG_CMD_ITEST | |
72 | #undef CONFIG_CMD_LOADB | |
73 | #undef CONFIG_CMD_LOADS | |
74 | #undef CONFIG_CMD_NET | |
75 | #undef CONFIG_CMD_NFS | |
76 | ||
acf02697 | 77 | #define CONFIG_CMD_PCI |
acf02697 | 78 | #define CONFIG_CMD_ELF |
acf02697 JL |
79 | #define CONFIG_CMD_I2C |
80 | #define CONFIG_CMD_BSP | |
81 | #define CONFIG_CMD_EEPROM | |
82 | ||
c837dcb1 | 83 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
c609719b | 84 | |
c837dcb1 | 85 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
c609719b | 86 | |
c837dcb1 | 87 | #define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ |
d69b100e | 88 | |
c609719b WD |
89 | /* |
90 | * Miscellaneous configurable options | |
91 | */ | |
6d0f6bcf | 92 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
c609719b | 93 | |
6d0f6bcf | 94 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
c609719b | 95 | |
acf02697 | 96 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 97 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c609719b | 98 | #else |
6d0f6bcf | 99 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c609719b | 100 | #endif |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
102 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
103 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c609719b | 104 | |
6d0f6bcf | 105 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
c609719b | 106 | |
6d0f6bcf | 107 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
c609719b | 108 | |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
110 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
c609719b | 111 | |
550650dd SR |
112 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
113 | #define CONFIG_SYS_NS16550 | |
114 | #define CONFIG_SYS_NS16550_SERIAL | |
115 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
116 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
117 | ||
6d0f6bcf | 118 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 119 | #define CONFIG_SYS_BASE_BAUD 691200 |
c609719b WD |
120 | |
121 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 122 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8bde7f77 WD |
123 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
124 | 57600, 115200, 230400, 460800, 921600 } | |
c609719b | 125 | |
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
127 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
c609719b | 128 | |
6d0f6bcf | 129 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
c609719b | 130 | |
d69b100e | 131 | #undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
c609719b | 132 | |
c837dcb1 | 133 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
2853d29b | 134 | |
c609719b WD |
135 | /*----------------------------------------------------------------------- |
136 | * PCI stuff | |
137 | *----------------------------------------------------------------------- | |
138 | */ | |
c837dcb1 WD |
139 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
140 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
141 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
c609719b | 142 | |
c837dcb1 | 143 | #define CONFIG_PCI /* include pci support */ |
842033e6 | 144 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
c837dcb1 WD |
145 | #define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */ |
146 | #undef CONFIG_PCI_PNP /* no pci plug-and-play */ | |
147 | /* resource configuration */ | |
c609719b | 148 | |
c837dcb1 | 149 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
c609719b | 150 | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
152 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */ | |
153 | #define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ | |
154 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
155 | #define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ | |
156 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
c609719b | 157 | |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_PCI_PTM2LA 0xef600000 /* point to internal regs */ |
159 | #define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ | |
160 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
c609719b WD |
161 | |
162 | /*----------------------------------------------------------------------- | |
163 | * Start addresses for the final memory configuration | |
164 | * (Set up by the startup code) | |
6d0f6bcf | 165 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 166 | */ |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
168 | #define CONFIG_SYS_FLASH_BASE 0xFFFD0000 | |
169 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
170 | #define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ | |
171 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
c609719b WD |
172 | |
173 | /* | |
174 | * For booting Linux, the board info and command line data | |
175 | * have to be in the first 8 MB of memory, since this is | |
176 | * the maximum mapped by the Linux kernel during initialization. | |
177 | */ | |
6d0f6bcf | 178 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
179 | /*----------------------------------------------------------------------- |
180 | * FLASH organization | |
181 | */ | |
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
183 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
c609719b | 184 | |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
186 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b | 187 | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
189 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
190 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
c609719b WD |
191 | /* |
192 | * The following defines are added for buggy IOP480 byte interface. | |
193 | * All other boards should use the standard values (CPCI405 etc.) | |
194 | */ | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
196 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
197 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
c609719b | 198 | |
6d0f6bcf | 199 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
c609719b | 200 | |
bb1f8b4f | 201 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
202 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
203 | #define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/ | |
8bde7f77 | 204 | /* total size of a CAT24WC08 is 1024 bytes */ |
c609719b | 205 | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
207 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
c609719b WD |
208 | |
209 | /*----------------------------------------------------------------------- | |
210 | * I2C EEPROM (CAT24WC16) for environment | |
211 | */ | |
880540de DE |
212 | #define CONFIG_SYS_I2C |
213 | #define CONFIG_SYS_I2C_PPC4XX | |
214 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
215 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
216 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
c609719b | 217 | |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
219 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
c837dcb1 | 220 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
222 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
c609719b | 223 | /* 16 byte page write mode using*/ |
c837dcb1 | 224 | /* last 4 bits of the address */ |
6d0f6bcf | 225 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
c609719b | 226 | |
c609719b WD |
227 | /* |
228 | * Init Memory Controller: | |
229 | * | |
230 | * BR0/1 and OR0/1 (FLASH) | |
231 | */ | |
232 | ||
233 | #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ | |
234 | ||
235 | /*----------------------------------------------------------------------- | |
236 | * External Bus Controller (EBC) Setup | |
237 | */ | |
238 | ||
c837dcb1 | 239 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
241 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 242 | |
c837dcb1 | 243 | /* Memory Bank 1 (NVRAM/RTC) initialization */ |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ |
245 | #define CONFIG_SYS_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ | |
c609719b | 246 | |
c837dcb1 | 247 | /* Memory Bank 2 (CAN0, 1) initialization */ |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
249 | /*#define CONFIG_SYS_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
250 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
c609719b | 251 | |
c837dcb1 | 252 | /* Memory Bank 3 (FPGA internal) initialization */ |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
254 | #define CONFIG_SYS_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ | |
255 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 | |
c609719b WD |
256 | |
257 | /*----------------------------------------------------------------------- | |
258 | * FPGA stuff | |
259 | */ | |
260 | /* FPGA internal regs */ | |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_FPGA_MODE 0x00 |
262 | #define CONFIG_SYS_FPGA_STATUS 0x02 | |
263 | #define CONFIG_SYS_FPGA_TS 0x04 | |
264 | #define CONFIG_SYS_FPGA_TS_LOW 0x06 | |
265 | #define CONFIG_SYS_FPGA_TS_CAP0 0x10 | |
266 | #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 | |
267 | #define CONFIG_SYS_FPGA_TS_CAP1 0x14 | |
268 | #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 | |
269 | #define CONFIG_SYS_FPGA_TS_CAP2 0x18 | |
270 | #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a | |
271 | #define CONFIG_SYS_FPGA_TS_CAP3 0x1c | |
272 | #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e | |
c609719b WD |
273 | |
274 | /* FPGA Mode Reg */ | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 |
276 | #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 | |
277 | #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 | |
278 | #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 | |
c609719b WD |
279 | |
280 | /* FPGA Status Reg */ | |
6d0f6bcf JCPV |
281 | #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 |
282 | #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 | |
283 | #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 | |
284 | #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 | |
285 | #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 | |
c609719b | 286 | |
6d0f6bcf JCPV |
287 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
288 | #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ | |
c609719b WD |
289 | |
290 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
292 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
293 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
294 | #define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ | |
295 | #define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ | |
a20b27a3 | 296 | /* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */ |
6d0f6bcf JCPV |
297 | #define CONFIG_SYS_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */ |
298 | #define CONFIG_SYS_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */ | |
c609719b WD |
299 | |
300 | /*----------------------------------------------------------------------- | |
301 | * Definitions for initial stack pointer and data area (in data cache) | |
302 | */ | |
a20b27a3 | 303 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
6d0f6bcf | 304 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
a20b27a3 | 305 | /* On Chip Memory location */ |
6d0f6bcf JCPV |
306 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
307 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
308 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 309 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
6d0f6bcf | 310 | |
25ddd1fb | 311 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 312 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c609719b | 313 | |
c609719b | 314 | #endif /* __CONFIG_H */ |