[people/ms/u-boot.git] / include / configs / PCI405.h

/*
 * (C) Copyright 2007
 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
 *
 * (C) Copyright 2001-2004
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_PCI405		1	/* ...on a PCI405 board		*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFD0000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r() on init	*/

#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTDELAY	0	/* autoboot after 0 seconds	*/

#undef	CONFIG_BOOTARGS
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"mem_linux=14336k\0"					        \
	"optargs=panic=0\0"					        \
	"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"	\
	"addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
	""
#define	CONFIG_BOOTCOMMAND      "run ramargs;run addcons;loadpci"

#define CONFIG_PREBOOT                  /* enable preboot variable      */

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_ITEST
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS

#define CONFIG_CMD_PCI
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

#define CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM" */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/

#define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function	*/
#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407	/* PCI Device ID: PCI-405	*/
#define CONFIG_SYS_PCI_CLASSCODE	0x0280	/* PCI Class Code: Network/Other*/
#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CONFIG_SYS_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/

#define CONFIG_SYS_PCI_PTM2LA	0xef600000	/* point to internal regs	*/
#define CONFIG_SYS_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars*/
				   /* total size of a CAT24WC08 is 1024 bytes */

#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (NVRAM/RTC) initialization					*/
#define CONFIG_SYS_EBC_PB1AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
#define CONFIG_SYS_EBC_PB1CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (CAN0, 1) initialization					*/
#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
/*#define CONFIG_SYS_EBC_PB2AP		  0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (FPGA internal) initialization					*/
#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB3CR		0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
/* FPGA internal regs */
#define CONFIG_SYS_FPGA_MODE		0x00
#define CONFIG_SYS_FPGA_STATUS		0x02
#define CONFIG_SYS_FPGA_TS		0x04
#define CONFIG_SYS_FPGA_TS_LOW		0x06
#define CONFIG_SYS_FPGA_TS_CAP0	0x10
#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
#define CONFIG_SYS_FPGA_TS_CAP1	0x14
#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
#define CONFIG_SYS_FPGA_TS_CAP2	0x18
#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e

/* FPGA Mode Reg */
#define CONFIG_SYS_FPGA_MODE_CF_RESET	0x0001
#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	0x2000

/* FPGA Status Reg */
#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000

#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */

/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CONFIG_SYS_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
#define CONFIG_SYS_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
#define CONFIG_SYS_FPGA_INIT_V12	0x00008000  /* FPGA init pin (ppc input)     */
#define CONFIG_SYS_FPGA_DONE_V12	0x00010000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM	  1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b	1	/*
76d1466f MF	2	* (C) Copyright 2007
	3	* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
	4	*
a20b27a3	5	* (C) Copyright 2001-2004
76d1466f	6	* Stefan Roese, DENX Software Engineering, sr@denx.de.
c609719b	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	9	*/
	10
	11	/*
	12	* board/config.h - configuration options, board specific
	13	*/
	14
	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
	17
	18	/*
	19	* High Level Configuration Options
	20	* (easy to change)
	21	*/
c609719b	22	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1 WD	23	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	24	#define CONFIG_PCI405 1 /* ...on a PCI405 board */
c609719b	25
2ae18241 WD	26	#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
2ae18241 WD	27
c837dcb1	28	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c609719b WD	29	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
c609719b WD	30
c837dcb1	31	#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
c609719b	32
a20b27a3 SR	33	#define CONFIG_BOARD_TYPES 1 /* support board types */
a20b27a3 SR	34
d69b100e	35	#define CONFIG_BAUDRATE 115200
a20b27a3	36	#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */
c609719b WD	37
c609719b WD	38	#undef CONFIG_BOOTARGS
a20b27a3 SR	39	#define CONFIG_EXTRA_ENV_SETTINGS \
	40	"mem_linux=14336k\0" \
	41	"optargs=panic=0\0" \
	42	"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
76d1466f	43	"addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
a20b27a3	44	""
76d1466f	45	#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci"
a20b27a3 SR	46
a20b27a3 SR	47	#define CONFIG_PREBOOT /* enable preboot variable */
c609719b	48
acf02697 JL	49	/*
	50	* Command line configuration.
	51	*/
	52	#include <config_cmd_default.h>
	53
24eea623 MF	54	#undef CONFIG_CMD_IMLS
	55	#undef CONFIG_CMD_ITEST
	56	#undef CONFIG_CMD_LOADB
	57	#undef CONFIG_CMD_LOADS
	58	#undef CONFIG_CMD_NET
	59	#undef CONFIG_CMD_NFS
	60
acf02697	61	#define CONFIG_CMD_PCI
acf02697	62	#define CONFIG_CMD_ELF
acf02697 JL	63	#define CONFIG_CMD_I2C
	64	#define CONFIG_CMD_BSP
	65	#define CONFIG_CMD_EEPROM
	66
c837dcb1	67	#undef CONFIG_WATCHDOG /* watchdog disabled */
c609719b	68
c837dcb1	69	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b	70
c837dcb1	71	#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
d69b100e	72
c609719b WD	73	/*
	74	* Miscellaneous configurable options
	75	*/
6d0f6bcf	76	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
c609719b	77
6d0f6bcf	78	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
c609719b	79
acf02697	80	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	81	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	82	#else
6d0f6bcf	83	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b	84	#endif
6d0f6bcf JCPV	85	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	86	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	87	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b	88
6d0f6bcf	89	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
c609719b	90
6d0f6bcf	91	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b	92
6d0f6bcf JCPV	93	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	94	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c609719b	95
550650dd SR	96	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	97	#define CONFIG_SYS_NS16550
	98	#define CONFIG_SYS_NS16550_SERIAL
	99	#define CONFIG_SYS_NS16550_REG_SIZE 1
	100	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	101
6d0f6bcf	102	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf	103	#define CONFIG_SYS_BASE_BAUD 691200
c609719b WD	104
c609719b WD	105	/* The following table includes the supported baudrates */
6d0f6bcf	106	#define CONFIG_SYS_BAUDRATE_TABLE \
8bde7f77 WD	107	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	108	57600, 115200, 230400, 460800, 921600 }
c609719b	109
6d0f6bcf JCPV	110	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	111	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
c609719b	112
6d0f6bcf	113	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b	114
d69b100e	115	#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
c609719b	116
c837dcb1	117	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
2853d29b	118
c609719b WD	119	/*-----------------------------------------------------------------------
	120	* PCI stuff
	121	*-----------------------------------------------------------------------
	122	*/
c837dcb1 WD	123	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	124	#define PCI_HOST_FORCE 1 /* configure as pci host */
	125	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
c609719b	126
c837dcb1	127	#define CONFIG_PCI /* include pci support */
842033e6	128	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c837dcb1 WD	129	#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */
	130	#undef CONFIG_PCI_PNP /* no pci plug-and-play */
	131	/* resource configuration */
c609719b	132
c837dcb1	133	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
c609719b	134
6d0f6bcf JCPV	135	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	136	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */
	137	#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
	138	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	139	#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
	140	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
c609719b	141
6d0f6bcf JCPV	142	#define CONFIG_SYS_PCI_PTM2LA 0xef600000 /* point to internal regs */
	143	#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
	144	#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
c609719b WD	145
	146	/*-----------------------------------------------------------------------
	147	* Start addresses for the final memory configuration
	148	* (Set up by the startup code)
6d0f6bcf	149	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	150	*/
6d0f6bcf JCPV	151	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	152	#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
	153	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	154	#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
	155	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
c609719b WD	156
	157	/*
	158	* For booting Linux, the board info and command line data
	159	* have to be in the first 8 MB of memory, since this is
	160	* the maximum mapped by the Linux kernel during initialization.
	161	*/
6d0f6bcf	162	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	163	/*-----------------------------------------------------------------------
	164	* FLASH organization
	165	*/
6d0f6bcf JCPV	166	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	167	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
c609719b	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	170	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b	171
6d0f6bcf JCPV	172	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	173	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	174	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	175	/*
	176	* The following defines are added for buggy IOP480 byte interface.
	177	* All other boards should use the standard values (CPCI405 etc.)
	178	*/
6d0f6bcf JCPV	179	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	180	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	181	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	182
6d0f6bcf	183	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b	184
bb1f8b4f	185	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	186	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	187	#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
8bde7f77	188	/* total size of a CAT24WC08 is 1024 bytes */
c609719b	189
6d0f6bcf JCPV	190	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
6d0f6bcf JCPV	191	#define CONFIG_SYS_NVRAM_SIZE (321024) / NVRAM size */
c609719b WD	192
	193	/*-----------------------------------------------------------------------
	194	* I2C EEPROM (CAT24WC16) for environment
	195	*/
880540de DE	196	#define CONFIG_SYS_I2C
	197	#define CONFIG_SYS_I2C_PPC4XX
	198	#define CONFIG_SYS_I2C_PPC4XX_CH0
	199	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	200	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
c609719b	201
6d0f6bcf JCPV	202	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
6d0f6bcf JCPV	203	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1	204	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	205	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	206	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
c609719b	207	/* 16 byte page write mode using*/
c837dcb1	208	/* last 4 bits of the address */
6d0f6bcf	209	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c609719b	210
c609719b WD	211	/*
	212	* Init Memory Controller:
	213	*
	214	* BR0/1 and OR0/1 (FLASH)
	215	*/
	216
	217	#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
	218
	219	/*-----------------------------------------------------------------------
	220	* External Bus Controller (EBC) Setup
	221	*/
	222
c837dcb1	223	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	224	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	225	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	226
c837dcb1	227	/* Memory Bank 1 (NVRAM/RTC) initialization */
6d0f6bcf JCPV	228	#define CONFIG_SYS_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
6d0f6bcf JCPV	229	#define CONFIG_SYS_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
c609719b	230
c837dcb1	231	/* Memory Bank 2 (CAN0, 1) initialization */
6d0f6bcf JCPV	232	#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	233	/#define CONFIG_SYS_EBC_PB2AP 0x038056C0 / BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	234	#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c609719b	235
c837dcb1	236	/* Memory Bank 3 (FPGA internal) initialization */
6d0f6bcf JCPV	237	#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	238	#define CONFIG_SYS_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
	239	#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
c609719b WD	240
	241	/*-----------------------------------------------------------------------
	242	* FPGA stuff
	243	*/
	244	/* FPGA internal regs */
6d0f6bcf JCPV	245	#define CONFIG_SYS_FPGA_MODE 0x00
	246	#define CONFIG_SYS_FPGA_STATUS 0x02
	247	#define CONFIG_SYS_FPGA_TS 0x04
	248	#define CONFIG_SYS_FPGA_TS_LOW 0x06
	249	#define CONFIG_SYS_FPGA_TS_CAP0 0x10
	250	#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
	251	#define CONFIG_SYS_FPGA_TS_CAP1 0x14
	252	#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
	253	#define CONFIG_SYS_FPGA_TS_CAP2 0x18
	254	#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
	255	#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
	256	#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
c609719b WD	257
c609719b WD	258	/* FPGA Mode Reg */
6d0f6bcf JCPV	259	#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
	260	#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
	261	#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
	262	#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
c609719b WD	263
c609719b WD	264	/* FPGA Status Reg */
6d0f6bcf JCPV	265	#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
	266	#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
	267	#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
	268	#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
	269	#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
c609719b	270
6d0f6bcf JCPV	271	#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
6d0f6bcf JCPV	272	#define CONFIG_SYS_FPGA_MAX_SIZE 321024 / 32kByte is enough for XC2S15 */
c609719b WD	273
c609719b WD	274	/* FPGA program pin configuration */
6d0f6bcf JCPV	275	#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	276	#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	277	#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	278	#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
	279	#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
a20b27a3	280	/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */
6d0f6bcf JCPV	281	#define CONFIG_SYS_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */
6d0f6bcf JCPV	282	#define CONFIG_SYS_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */
c609719b WD	283
	284	/*-----------------------------------------------------------------------
	285	* Definitions for initial stack pointer and data area (in data cache)
	286	*/
a20b27a3	287	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
6d0f6bcf	288	#define CONFIG_SYS_TEMP_STACK_OCM 1
a20b27a3	289	/* On Chip Memory location */
6d0f6bcf JCPV	290	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	291	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	292	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
553f0982	293	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
6d0f6bcf	294
25ddd1fb	295	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	296	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b	297
c609719b	298	#endif /* __CONFIG_H */