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e2211743 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2002-2005 |
e2211743 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * | |
26 | * Configuration settings for the PCIPPC-6 board. | |
27 | * | |
28 | */ | |
29 | ||
30 | /* ------------------------------------------------------------------------- */ | |
31 | ||
32 | /* | |
33 | * board/config.h - configuration options, board specific | |
34 | */ | |
35 | ||
36 | #ifndef __CONFIG_H | |
37 | #define __CONFIG_H | |
38 | ||
39 | /* | |
40 | * High Level Configuration Options | |
41 | * (easy to change) | |
42 | */ | |
43 | ||
44 | #define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ | |
45 | ||
2ae18241 WD |
46 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
47 | ||
c837dcb1 | 48 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
e2211743 WD |
49 | #define CONFIG_MISC_INIT_R 1 |
50 | ||
51 | #define CONFIG_CONS_INDEX 1 | |
52 | #define CONFIG_BAUDRATE 9600 | |
6d0f6bcf | 53 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
e2211743 | 54 | |
e2211743 WD |
55 | #define CONFIG_PREBOOT "" |
56 | #define CONFIG_BOOTDELAY 5 | |
57 | ||
18225e8d JL |
58 | /* |
59 | * BOOTP options | |
60 | */ | |
61 | #define CONFIG_BOOTP_SUBNETMASK | |
62 | #define CONFIG_BOOTP_GATEWAY | |
63 | #define CONFIG_BOOTP_HOSTNAME | |
64 | #define CONFIG_BOOTP_BOOTPATH | |
65 | #define CONFIG_BOOTP_BOOTFILESIZE | |
e2211743 WD |
66 | |
67 | #define CONFIG_MAC_PARTITION | |
68 | #define CONFIG_DOS_PARTITION | |
69 | ||
acf02697 JL |
70 | |
71 | /* | |
72 | * Command line configuration. | |
73 | */ | |
74 | #include <config_cmd_default.h> | |
75 | ||
76 | #define CONFIG_CMD_ASKENV | |
77 | #define CONFIG_CMD_BSP | |
78 | #define CONFIG_CMD_DATE | |
79 | #define CONFIG_CMD_DHCP | |
acf02697 JL |
80 | #define CONFIG_CMD_ELF |
81 | #define CONFIG_CMD_NFS | |
82 | #define CONFIG_CMD_PCI | |
83 | #define CONFIG_CMD_SCSI | |
84 | #define CONFIG_CMD_SNTP | |
e2211743 WD |
85 | |
86 | ||
87 | #define CONFIG_PCI 1 | |
88 | #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ | |
89 | ||
e2211743 WD |
90 | /* |
91 | * Miscellaneous configurable options | |
92 | */ | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
94 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
e2211743 | 95 | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
97 | #ifdef CONFIG_SYS_HUSH_PARSER | |
98 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
e2211743 | 99 | #endif |
6d0f6bcf | 100 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e2211743 WD |
101 | |
102 | /* Print Buffer Size | |
103 | */ | |
6d0f6bcf | 104 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
e2211743 | 105 | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_MAXARGS 64 /* max number of command args */ |
107 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
108 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ | |
e2211743 WD |
109 | |
110 | /*----------------------------------------------------------------------- | |
111 | * Start addresses for the final memory configuration | |
112 | * (Set up by the startup code) | |
6d0f6bcf | 113 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
e2211743 | 114 | */ |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
116 | #define CONFIG_SYS_FLASH_BASE 0xFFF00000 | |
117 | #define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000 | |
e2211743 WD |
118 | /* Maximum amount of RAM. |
119 | */ | |
6d0f6bcf | 120 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */ |
e2211743 | 121 | |
6d0f6bcf | 122 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
e2211743 | 123 | |
14d0a02a | 124 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
e2211743 | 125 | |
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
127 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
e2211743 | 128 | |
6d0f6bcf JCPV |
129 | #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \ |
130 | CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE | |
131 | #define CONFIG_SYS_RAMBOOT | |
e2211743 | 132 | #else |
6d0f6bcf | 133 | #undef CONFIG_SYS_RAMBOOT |
e2211743 WD |
134 | #endif |
135 | ||
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ |
137 | #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ | |
e2211743 WD |
138 | |
139 | /*----------------------------------------------------------------------- | |
140 | * Definitions for initial stack pointer and data area | |
141 | */ | |
142 | ||
143 | /* Size in bytes reserved for initial data | |
144 | */ | |
e2211743 | 145 | |
6d0f6bcf | 146 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
553f0982 | 147 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 |
25ddd1fb | 148 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 149 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e2211743 | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_INIT_RAM_LOCK |
e2211743 WD |
152 | |
153 | /* | |
154 | * Temporary buffer for serial data until the real serial driver | |
155 | * is initialised (memtest will destroy this buffer) | |
156 | */ | |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR |
158 | #define CONFIG_SYS_SCONSOLE_SIZE 0x0002000 | |
e2211743 WD |
159 | |
160 | /* SDRAM 0 - 256MB | |
161 | */ | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
163 | #define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \ | |
e2211743 WD |
164 | BATU_BL_256M | BATU_VS | BATU_VP) |
165 | /* SDRAM 1 - 256MB | |
166 | */ | |
6d0f6bcf | 167 | #define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ |
e2211743 | 168 | BATL_PP_10 | BATL_MEMCOHERENCE) |
6d0f6bcf | 169 | #define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ |
e2211743 WD |
170 | BATU_BL_256M | BATU_VS | BATU_VP) |
171 | ||
172 | /* Init RAM in the CPU DCache (no backing memory) | |
173 | */ | |
6d0f6bcf | 174 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \ |
e2211743 | 175 | BATL_PP_10 | BATL_MEMCOHERENCE) |
6d0f6bcf | 176 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \ |
e2211743 WD |
177 | BATU_BL_128K | BATU_VS | BATU_VP) |
178 | ||
179 | /* I/O and PCI memory at 0xf0000000 | |
180 | */ | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
182 | #define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
183 | ||
184 | #define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L | |
185 | #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U | |
186 | #define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L | |
187 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U | |
188 | #define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L | |
189 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
190 | #define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L | |
191 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U | |
e2211743 WD |
192 | |
193 | /* | |
194 | * Low Level Configuration Settings | |
195 | * (address mappings, register initial values, etc.) | |
196 | * You should know what you are doing if you make changes here. | |
197 | * For the detail description refer to the PCIPPC2 user's manual. | |
198 | */ | |
6d0f6bcf | 199 | #define CONFIG_SYS_HZ 1000 |
ee80fa7b | 200 | #define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ |
6d0f6bcf | 201 | #define CONFIG_SYS_CPU_CLK 300000000 |
e2211743 WD |
202 | |
203 | /* | |
204 | * For booting Linux, the board info and command line data | |
205 | * have to be in the first 8 MB of memory, since this is | |
206 | * the maximum mapped by the Linux kernel during initialization. | |
207 | */ | |
6d0f6bcf | 208 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
e2211743 WD |
209 | |
210 | /*----------------------------------------------------------------------- | |
211 | * FLASH organization | |
212 | */ | |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
214 | #define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ | |
e2211743 | 215 | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
217 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
e2211743 WD |
218 | |
219 | /* | |
220 | * Note: environment is not EMBEDDED in the U-Boot code. | |
221 | * It's stored in flash separately. | |
222 | */ | |
5a1aceb0 | 223 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 224 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000) |
0e8d1586 JCPV |
225 | #define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */ |
226 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ | |
e2211743 WD |
227 | |
228 | /*----------------------------------------------------------------------- | |
229 | * Cache Configuration | |
230 | */ | |
6d0f6bcf | 231 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
acf02697 | 232 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 233 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
e2211743 WD |
234 | #endif |
235 | ||
236 | /* | |
237 | * L2 cache | |
238 | */ | |
6d0f6bcf | 239 | #undef CONFIG_SYS_L2 |
e2211743 WD |
240 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
241 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) | |
242 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
243 | ||
e2211743 WD |
244 | /*----------------------------------------------------------------------- |
245 | RTC m48t59 | |
246 | */ | |
247 | #define CONFIG_RTC_MK48T59 | |
248 | ||
249 | #define CONFIG_WATCHDOG | |
250 | ||
251 | #define CONFIG_NET_MULTI /* Multi ethernet cards support */ | |
252 | ||
253 | #define CONFIG_EEPRO100 | |
6d0f6bcf | 254 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
e2211743 WD |
255 | #define CONFIG_TULIP |
256 | ||
257 | ||
258 | #define CONFIG_SCSI_SYM53C8XX | |
259 | #define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */ | |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */ |
261 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */ | |
262 | #define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */ | |
263 | #define CONFIG_SYS_SCSI_SPIN_UP_TIME 2 | |
264 | #define CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 0 | |
e2211743 WD |
265 | #define CONFIG_DOS_PARTITION |
266 | #define CONFIG_MAC_PARTITION | |
267 | #define CONFIG_ISO_PARTITION | |
268 | ||
e2211743 | 269 | #endif /* __CONFIG_H */ |