]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/PCIPPC6.h
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / include / configs / PCIPPC6.h
CommitLineData
e2211743 1/*
414eec35 2 * (C) Copyright 2002-2005
e2211743
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the PCIPPC-6 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
45
c837dcb1 46#define CONFIG_BOARD_EARLY_INIT_F 1
e2211743
WD
47#define CONFIG_MISC_INIT_R 1
48
49#define CONFIG_CONS_INDEX 1
50#define CONFIG_BAUDRATE 9600
6d0f6bcf 51#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
e2211743 52
e2211743
WD
53#define CONFIG_PREBOOT ""
54#define CONFIG_BOOTDELAY 5
55
18225e8d
JL
56/*
57 * BOOTP options
58 */
59#define CONFIG_BOOTP_SUBNETMASK
60#define CONFIG_BOOTP_GATEWAY
61#define CONFIG_BOOTP_HOSTNAME
62#define CONFIG_BOOTP_BOOTPATH
63#define CONFIG_BOOTP_BOOTFILESIZE
e2211743
WD
64
65#define CONFIG_MAC_PARTITION
66#define CONFIG_DOS_PARTITION
67
acf02697
JL
68
69/*
70 * Command line configuration.
71 */
72#include <config_cmd_default.h>
73
74#define CONFIG_CMD_ASKENV
75#define CONFIG_CMD_BSP
76#define CONFIG_CMD_DATE
77#define CONFIG_CMD_DHCP
78#define CONFIG_CMD_DOC
79#define CONFIG_CMD_ELF
80#define CONFIG_CMD_NFS
81#define CONFIG_CMD_PCI
82#define CONFIG_CMD_SCSI
83#define CONFIG_CMD_SNTP
e2211743
WD
84
85
86#define CONFIG_PCI 1
87#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
88
cc4a0cee 89#define CONFIG_NAND_LEGACY
e2211743
WD
90
91/*
92 * Miscellaneous configurable options
93 */
6d0f6bcf
JCPV
94#define CONFIG_SYS_LONGHELP /* undef to save memory */
95#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
e2211743 96
6d0f6bcf
JCPV
97#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
98#ifdef CONFIG_SYS_HUSH_PARSER
99#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
e2211743 100#endif
6d0f6bcf 101#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743
WD
102
103/* Print Buffer Size
104 */
6d0f6bcf 105#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
e2211743 106
6d0f6bcf
JCPV
107#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
108#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
109#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
e2211743
WD
110
111/*-----------------------------------------------------------------------
112 * Start addresses for the final memory configuration
113 * (Set up by the startup code)
6d0f6bcf 114 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743 115 */
6d0f6bcf
JCPV
116#define CONFIG_SYS_SDRAM_BASE 0x00000000
117#define CONFIG_SYS_FLASH_BASE 0xFFF00000
118#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000
e2211743
WD
119/* Maximum amount of RAM.
120 */
6d0f6bcf 121#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */
e2211743 122
6d0f6bcf 123#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
e2211743 124
6d0f6bcf 125#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
e2211743 126
6d0f6bcf
JCPV
127#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
128#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e2211743 129
6d0f6bcf
JCPV
130#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
131 CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
132#define CONFIG_SYS_RAMBOOT
e2211743 133#else
6d0f6bcf 134#undef CONFIG_SYS_RAMBOOT
e2211743
WD
135#endif
136
6d0f6bcf
JCPV
137#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
138#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
e2211743
WD
139
140/*-----------------------------------------------------------------------
141 * Definitions for initial stack pointer and data area
142 */
143
144/* Size in bytes reserved for initial data
145 */
6d0f6bcf 146#define CONFIG_SYS_GBL_DATA_SIZE 128
e2211743 147
6d0f6bcf
JCPV
148#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
149#define CONFIG_SYS_INIT_RAM_END 0x8000
150#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
151#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743 152
6d0f6bcf 153#define CONFIG_SYS_INIT_RAM_LOCK
e2211743
WD
154
155/*
156 * Temporary buffer for serial data until the real serial driver
157 * is initialised (memtest will destroy this buffer)
158 */
6d0f6bcf
JCPV
159#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR
160#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000
e2211743
WD
161
162/* SDRAM 0 - 256MB
163 */
6d0f6bcf
JCPV
164#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
165#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \
e2211743
WD
166 BATU_BL_256M | BATU_VS | BATU_VP)
167/* SDRAM 1 - 256MB
168 */
6d0f6bcf 169#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
e2211743 170 BATL_PP_10 | BATL_MEMCOHERENCE)
6d0f6bcf 171#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
e2211743
WD
172 BATU_BL_256M | BATU_VS | BATU_VP)
173
174/* Init RAM in the CPU DCache (no backing memory)
175 */
6d0f6bcf 176#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \
e2211743 177 BATL_PP_10 | BATL_MEMCOHERENCE)
6d0f6bcf 178#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \
e2211743
WD
179 BATU_BL_128K | BATU_VS | BATU_VP)
180
181/* I/O and PCI memory at 0xf0000000
182 */
6d0f6bcf
JCPV
183#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
184#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
185
186#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L
187#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
188#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L
189#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
190#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L
191#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
192#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L
193#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
e2211743
WD
194
195/*
196 * Low Level Configuration Settings
197 * (address mappings, register initial values, etc.)
198 * You should know what you are doing if you make changes here.
199 * For the detail description refer to the PCIPPC2 user's manual.
200 */
6d0f6bcf
JCPV
201#define CONFIG_SYS_HZ 1000
202#define CONFIG_SYS_BUS_HZ 100000000 /* bus speed - 100 mhz */
203#define CONFIG_SYS_CPU_CLK 300000000
204#define CONFIG_SYS_BUS_CLK 100000000
e2211743
WD
205
206/*
207 * For booting Linux, the board info and command line data
208 * have to be in the first 8 MB of memory, since this is
209 * the maximum mapped by the Linux kernel during initialization.
210 */
6d0f6bcf 211#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743
WD
212
213/*-----------------------------------------------------------------------
214 * FLASH organization
215 */
6d0f6bcf
JCPV
216#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
217#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
e2211743 218
6d0f6bcf
JCPV
219#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
220#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
e2211743
WD
221
222/*
223 * Note: environment is not EMBEDDED in the U-Boot code.
224 * It's stored in flash separately.
225 */
5a1aceb0 226#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf 227#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000)
0e8d1586
JCPV
228#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
229#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
e2211743
WD
230
231/*-----------------------------------------------------------------------
232 * Cache Configuration
233 */
6d0f6bcf 234#define CONFIG_SYS_CACHELINE_SIZE 32
acf02697 235#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 236# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
e2211743
WD
237#endif
238
239/*
240 * L2 cache
241 */
6d0f6bcf 242#undef CONFIG_SYS_L2
e2211743
WD
243#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
244 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
245#define L2_ENABLE (L2_INIT | L2CR_L2E)
246
247/*
248 * Internal Definitions
249 *
250 * Boot Flags
251 */
252#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
253#define BOOTFLAG_WARM 0x02 /* Software reboot */
254
255/*-----------------------------------------------------------------------
256 * Disk-On-Chip configuration
257 */
258
6d0f6bcf 259#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
e2211743 260
6d0f6bcf
JCPV
261#define CONFIG_SYS_DOC_SUPPORT_2000
262#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
e2211743
WD
263
264/*-----------------------------------------------------------------------
265 RTC m48t59
266*/
267#define CONFIG_RTC_MK48T59
268
269#define CONFIG_WATCHDOG
270
271#define CONFIG_NET_MULTI /* Multi ethernet cards support */
272
273#define CONFIG_EEPRO100
6d0f6bcf 274#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
e2211743
WD
275#define CONFIG_TULIP
276
277
278#define CONFIG_SCSI_SYM53C8XX
279#define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */
6d0f6bcf
JCPV
280#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
281#define CONFIG_SYS_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */
282#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
283#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
284#define CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 0
e2211743
WD
285#define CONFIG_DOS_PARTITION
286#define CONFIG_MAC_PARTITION
287#define CONFIG_ISO_PARTITION
288
e2211743 289#endif /* __CONFIG_H */