[people/ms/u-boot.git] / include / configs / PIP405.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/***********************************************************
 * High Level Configuration Options
 * (easy to change)
 ***********************************************************/
#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_PIP405		1	/* ...on a PIP405 board		*/
/***********************************************************
 * Clock
 ***********************************************************/
#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_IDE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_FDC
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_FAT
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_USB
#define CONFIG_CMD_MII
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_DOC
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_BSP


#define CFG_NAND_LEGACY

#define	 CFG_HUSH_PARSER
#define	 CFG_PROMPT_HUSH_PS2 "> "
/**************************************************************
 * I2C Stuff:
 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
 * 0x53.
 * Caution: on the same bus is the SPD (Serial Presens Detect
 * EEPROM of the SDRAM
 * The Atmel EEPROM uses 16Bit addressing.
 ***************************************************************/
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x53
#define CFG_I2C_EEPROM_ADDR_LEN	2
#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */

#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
					/* 64 byte page write mode using*/
					/* last	6 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* enable Page write */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */


/***************************************************************
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 ***************************************************************/
#define SPD_EEPROM_ADDRESS      0x50

#define CONFIG_BOARD_EARLY_INIT_F
/**************************************************************
 * Environment definitions
 **************************************************************/
#define CONFIG_BAUDRATE		9600	/* STD Baudrate */


#define CONFIG_BOOTDELAY	5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */


#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */

#define CONFIG_IPADDR		10.0.0.100
#define CONFIG_SERVERIP		10.0.0.1
#define CONFIG_PREBOOT
/***************************************************************
 * defines if the console is stored in the environment
 ***************************************************************/
#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
/***************************************************************
 * defines if an overwrite_console function exists
 *************************************************************/
#define CFG_CONSOLE_OVERWRITE_ROUTINE
#define CFG_CONSOLE_INFO_QUIET
/***************************************************************
 * defines if the overwrite_console should be stored in the
 * environment
 **************************************************************/
#undef CFG_CONSOLE_ENV_OVERWRITE

/**************************************************************
 * loads config
 *************************************************************/
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MISC_INIT_R
/***********************************************************
 * Miscellaneous configurable options
 **********************************************************/
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_BASE_BAUD       691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR		0x400000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
					/* resource configuration	*/
#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFF80000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Init Memory Controller:
 */
#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/

#define CONFIG_BOARD_EARLY_INIT_F

/* Configuration Port location */
#define CONFIG_PORT_ADDR	0xF4000000
#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in On Chip SRAM)
 */
#define CFG_TEMP_STACK_OCM	1
#define CFG_OCM_DATA_ADDR	0xF0000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/


/***********************************************************************
 * External peripheral base address
 ***********************************************************************/
#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000

/***********************************************************************
 * Last Stage Init
 ***********************************************************************/
#define CONFIG_LAST_STAGE_INIT
/************************************************************
 * Ethernet Stuff
 ***********************************************************/
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		1	/* PHY address			*/
#define CONFIG_CS8952_PHY	1	/* its a CS8952 PHY		*/
/************************************************************
 * RTC
 ***********************************************************/
#define CONFIG_RTC_MC146818
#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/************************************************************
 * IDE/ATA stuff
 ************************************************************/
#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	CFG_ISA_IO_BASE_ADDRESS /* base address */
#define CFG_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
#define CFG_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
#define CFG_ATA_REG_OFFSET	0	/* reg offset */
#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */

#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#define CONFIG_IDE_RESET		/* reset for ide supported...	*/
#define CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
#define CONFIG_SUPPORT_VFAT

/************************************************************
 * ATAPI support (experimental)
 ************************************************************/
#define CONFIG_ATAPI			/* enable ATAPI Support */

/************************************************************
 * SCSI support (experimental) only SYM53C8xx supported
 ************************************************************/
#define CONFIG_SCSI_SYM53C8XX
#define CFG_SCSI_MAX_LUN	8	/* number of supported LUNs */
#define CFG_SCSI_MAX_SCSI_ID	7	/* maximum SCSI ID (0..6) */
#define CFG_SCSI_MAX_DEVICE	CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
#define CFG_SCSI_SPIN_UP_TIME	2

/************************************************************
 * Disk-On-Chip configuration
 ************************************************************/
#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM

/************************************************************
 * DISK Partition support
 ************************************************************/
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */

/************************************************************
 * Keyboard support
 ************************************************************/
#define CONFIG_ISA_KEYBOARD

/************************************************************
 * Video support
 ************************************************************/
#define CONFIG_VIDEO			/*To enable video controller support */
#define CONFIG_VIDEO_CT69000
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_ONBOARD		/* Video controller is on-board */

/************************************************************
 * USB support
 ************************************************************/
#define CONFIG_USB_UHCI
#define CONFIG_USB_KEYBOARD
#define CONFIG_USB_STORAGE

/* Enable needed helper functions */
#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */

/************************************************************
 * Debug support
 ************************************************************/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/************************************************************
 * support BZIP2 compression
 ************************************************************/
#define CONFIG_BZIP2		1

/************************************************************
 * Ident
 ************************************************************/
#define VERSION_TAG "released"
#define CONFIG_ISO_STRING "MEV-10066-001"
#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG


#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/***********************************************************
	32	* High Level Configuration Options
	33	* (easy to change)
	34	***********************************************************/
	35	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	36	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	37	#define CONFIG_PIP405 1 /* ...on a PIP405 board */
	38	/***********************************************************
	39	* Clock
	40	***********************************************************/
	41	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	42
acf02697 JL	43
	44	/*
	45	* Command line configuration.
	46	*/
	47	#include <config_cmd_default.h>
	48
	49	#define CONFIG_CMD_IDE
	50	#define CONFIG_CMD_DHCP
	51	#define CONFIG_CMD_PCI
	52	#define CONFIG_CMD_CACHE
	53	#define CONFIG_CMD_IRQ
	54	#define CONFIG_CMD_EEPROM
	55	#define CONFIG_CMD_I2C
	56	#define CONFIG_CMD_REGINFO
	57	#define CONFIG_CMD_FDC
	58	#define CONFIG_CMD_SCSI
	59	#define CONFIG_CMD_FAT
	60	#define CONFIG_CMD_DATE
	61	#define CONFIG_CMD_ELF
	62	#define CONFIG_CMD_USB
	63	#define CONFIG_CMD_MII
	64	#define CONFIG_CMD_SDRAM
	65	#define CONFIG_CMD_DOC
	66	#define CONFIG_CMD_PING
	67	#define CONFIG_CMD_SAVES
	68	#define CONFIG_CMD_BSP
	69
c609719b	70
addb2e16 BS	71	#define CFG_NAND_LEGACY
addb2e16 BS	72
c609719b WD	73	#define CFG_HUSH_PARSER
	74	#define CFG_PROMPT_HUSH_PS2 "> "
	75	/**************************************************************
	76	* I2C Stuff:
	77	* the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
	78	* 0x53.
	79	* Caution: on the same bus is the SPD (Serial Presens Detect
	80	* EEPROM of the SDRAM
	81	* The Atmel EEPROM uses 16Bit addressing.
	82	***************************************************************/
	83	#define CONFIG_HARD_I2C /* I2c with hardware support */
	84	#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
	85	#define CFG_I2C_SLAVE 0x7F
	86
	87	#define CFG_I2C_EEPROM_ADDR 0x53
	88	#define CFG_I2C_EEPROM_ADDR_LEN 2
	89	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	90	#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
	91	#define CFG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
	92
	93	#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
	94	#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
	95	/* 64 byte page write mode using*/
	96	/* last 6 bits of the address */
	97	#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
	98	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	99
	100
	101	/***************************************************************
	102	* Definitions for Serial Presence Detect EEPROM address
	103	* (to get SDRAM settings)
	104	***************************************************************/
	105	#define SPD_EEPROM_ADDRESS 0x50
	106
c837dcb1	107	#define CONFIG_BOARD_EARLY_INIT_F
c609719b WD	108	/**************************************************************
	109	* Environment definitions
	110	**************************************************************/
	111	#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
	112
	113
	114	#define CONFIG_BOOTDELAY 5
	115	/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
2afbe4ed	116	/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
c609719b WD	117	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
	118
	119
3e38691e	120	#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
c609719b WD	121	#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
	122
	123	#define CONFIG_IPADDR 10.0.0.100
	124	#define CONFIG_SERVERIP 10.0.0.1
	125	#define CONFIG_PREBOOT
	126	/***************************************************************
	127	* defines if the console is stored in the environment
	128	***************************************************************/
	129	#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
	130	/***************************************************************
	131	* defines if an overwrite_console function exists
	132	*************************************************************/
	133	#define CFG_CONSOLE_OVERWRITE_ROUTINE
	134	#define CFG_CONSOLE_INFO_QUIET
	135	/***************************************************************
	136	* defines if the overwrite_console should be stored in the
	137	* environment
	138	**************************************************************/
	139	#undef CFG_CONSOLE_ENV_OVERWRITE
	140
	141	/**************************************************************
	142	* loads config
	143	*************************************************************/
	144	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	145	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	146
7205e407	147	#define CONFIG_MISC_INIT_R
c609719b WD	148	/***********************************************************
	149	* Miscellaneous configurable options
	150	**********************************************************/
	151	#define CFG_LONGHELP /* undef to save memory */
	152	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
acf02697	153	#if defined(CONFIG_CMD_KGDB)
c609719b WD	154	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	155	#else
	156	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	157	#endif
	158	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	159	#define CFG_MAXARGS 16 /* max number of command args */
	160	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	161
	162	#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
	163	#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
	164
	165	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	166	#define CFG_BASE_BAUD 691200
	167
	168	/* The following table includes the supported baudrates */
	169	#define CFG_BAUDRATE_TABLE \
	170	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	171	57600, 115200, 230400, 460800, 921600 }
	172
3e38691e	173	#define CFG_LOAD_ADDR 0x400000 /* default load address */
c609719b WD	174	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	175
	176	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	177
	178	/*-----------------------------------------------------------------------
	179	* PCI stuff
	180	*-----------------------------------------------------------------------
	181	*/
	182	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	183	#define PCI_HOST_FORCE 1 /* configure as pci host */
	184	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	185
	186	#define CONFIG_PCI /* include pci support */
	187	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
	188	#define CONFIG_PCI_PNP /* pci plug-and-play */
	189	/* resource configuration */
	190	#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
	191	#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
	192	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	193	#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	194	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	195	#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
	196	#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
	197	#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
	198
	199	/*-----------------------------------------------------------------------
	200	* Start addresses for the final memory configuration
	201	* (Set up by the startup code)
	202	* Please note that CFG_SDRAM_BASE _must_ start at 0
	203	*/
	204	#define CFG_SDRAM_BASE 0x00000000
	205	#define CFG_FLASH_BASE 0xFFF80000
	206	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	207	#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
a2663ea4	208	#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
c609719b WD	209
	210	/*
	211	* For booting Linux, the board info and command line data
	212	* have to be in the first 8 MB of memory, since this is
	213	* the maximum mapped by the Linux kernel during initialization.
	214	*/
	215	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	216	/*-----------------------------------------------------------------------
	217	* FLASH organization
	218	*/
	219	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	220	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	221
	222	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	223	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	224
	225	/*-----------------------------------------------------------------------
	226	* Cache Configuration
	227	*/
0c8721a4	228	#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
c609719b	229	#define CFG_CACHELINE_SIZE 32 /* ... */
acf02697	230	#if defined(CONFIG_CMD_KGDB)
c609719b WD	231	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	232	#endif
	233
	234	/*
	235	* Init Memory Controller:
	236	*/
7205e407 WD	237	#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
	238	#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
	239	/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
	240	#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
c609719b	241
c837dcb1	242	#define CONFIG_BOARD_EARLY_INIT_F
c609719b WD	243
	244	/* Configuration Port location */
	245	#define CONFIG_PORT_ADDR 0xF4000000
	246	#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
	247
	248
c609719b WD	249	/*-----------------------------------------------------------------------
	250	* Definitions for initial stack pointer and data area (in On Chip SRAM)
	251	*/
	252	#define CFG_TEMP_STACK_OCM 1
	253	#define CFG_OCM_DATA_ADDR 0xF0000000
	254	#define CFG_OCM_DATA_SIZE 0x1000
	255	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
	256	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
	257	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	258	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	259	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	260
	261	/*
	262	* Internal Definitions
	263	*
	264	* Boot Flags
	265	*/
	266	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	267	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	268
	269
	270	/***********************************************************************
	271	* External peripheral base address
	272	***********************************************************************/
	273	#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
	274
	275	/***********************************************************************
	276	* Last Stage Init
	277	***********************************************************************/
	278	#define CONFIG_LAST_STAGE_INIT
	279	/************************************************************
	280	* Ethernet Stuff
	281	***********************************************************/
	282	#define CONFIG_MII 1 /* MII PHY management */
	283	#define CONFIG_PHY_ADDR 1 /* PHY address */
	284	#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */
	285	/************************************************************
	286	* RTC
	287	***********************************************************/
	288	#define CONFIG_RTC_MC146818
	289	#undef CONFIG_WATCHDOG /* watchdog disabled */
	290
	291	/************************************************************
	292	* IDE/ATA stuff
	293	************************************************************/
	294	#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
	295	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS2) / max. 2 drives per IDE bus */
	296
	297	#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
	298	#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
	299	#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
	300	#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
	301	#define CFG_ATA_REG_OFFSET 0 /* reg offset */
	302	#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
	303
	304	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	305	#undef CONFIG_IDE_LED /* no led for ide supported */
	306	#define CONFIG_IDE_RESET /* reset for ide supported... */
	307	#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
7205e407	308	#define CONFIG_SUPPORT_VFAT
c609719b WD	309
	310	/************************************************************
	311	* ATAPI support (experimental)
	312	************************************************************/
	313	#define CONFIG_ATAPI /* enable ATAPI Support */
	314
	315	/************************************************************
	316	* SCSI support (experimental) only SYM53C8xx supported
	317	************************************************************/
	318	#define CONFIG_SCSI_SYM53C8XX
	319	#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
	320	#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
	321	#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
	322	#define CFG_SCSI_SPIN_UP_TIME 2
	323
	324	/************************************************************
	325	* Disk-On-Chip configuration
	326	************************************************************/
	327	#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
	328	#define CFG_DOC_SHORT_TIMEOUT
	329	#define CFG_DOC_SUPPORT_2000
	330	#define CFG_DOC_SUPPORT_MILLENNIUM
	331
	332	/************************************************************
	333	* DISK Partition support
	334	************************************************************/
	335	#define CONFIG_DOS_PARTITION
	336	#define CONFIG_MAC_PARTITION
	337	#define CONFIG_ISO_PARTITION /* Experimental */
	338
	339	/************************************************************
	340	* Keyboard support
	341	************************************************************/
	342	#define CONFIG_ISA_KEYBOARD
	343
	344	/************************************************************
	345	* Video support
	346	************************************************************/
	347	#define CONFIG_VIDEO /To enable video controller support /
	348	#define CONFIG_VIDEO_CT69000
	349	#define CONFIG_CFB_CONSOLE
	350	#define CONFIG_VIDEO_LOGO
	351	#define CONFIG_CONSOLE_EXTRA_INFO
	352	#define CONFIG_VGA_AS_SINGLE_DEVICE
	353	#define CONFIG_VIDEO_SW_CURSOR
	354	#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
	355
	356	/************************************************************
	357	* USB support
	358	************************************************************/
	359	#define CONFIG_USB_UHCI
	360	#define CONFIG_USB_KEYBOARD
	361	#define CONFIG_USB_STORAGE
	362
	363	/* Enable needed helper functions */
	364	#define CFG_DEVICE_DEREGISTER /* needs device_deregister */
	365
	366	/************************************************************
	367	* Debug support
	368	************************************************************/
acf02697	369	#if defined(CONFIG_CMD_KGDB)
c609719b WD	370	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	371	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	372	#endif
	373
a2663ea4 WD	374	/************************************************************
	375	* support BZIP2 compression
	376	************************************************************/
	377	#define CONFIG_BZIP2 1
	378
c609719b WD	379	/************************************************************
	380	* Ident
	381	************************************************************/
	382	#define VERSION_TAG "released"
f3e0de60 WD	383	#define CONFIG_ISO_STRING "MEV-10066-001"
f3e0de60 WD	384	#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
c609719b WD	385
	386
	387	#endif /* __CONFIG_H */