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Commit | Line | Data |
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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /*********************************************************** | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | ***********************************************************/ | |
19 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
c609719b | 20 | #define CONFIG_PIP405 1 /* ...on a PIP405 board */ |
2ae18241 WD |
21 | |
22 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 | |
23 | ||
c609719b WD |
24 | /*********************************************************** |
25 | * Clock | |
26 | ***********************************************************/ | |
27 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ | |
28 | ||
a1aa0bb5 JL |
29 | /* |
30 | * BOOTP options | |
31 | */ | |
32 | #define CONFIG_BOOTP_BOOTFILESIZE | |
33 | #define CONFIG_BOOTP_BOOTPATH | |
34 | #define CONFIG_BOOTP_GATEWAY | |
35 | #define CONFIG_BOOTP_HOSTNAME | |
36 | ||
acf02697 JL |
37 | /* |
38 | * Command line configuration. | |
39 | */ | |
acf02697 | 40 | #define CONFIG_CMD_IDE |
acf02697 | 41 | #define CONFIG_CMD_PCI |
acf02697 JL |
42 | #define CONFIG_CMD_IRQ |
43 | #define CONFIG_CMD_EEPROM | |
acf02697 JL |
44 | #define CONFIG_CMD_REGINFO |
45 | #define CONFIG_CMD_FDC | |
46 | #define CONFIG_CMD_SCSI | |
acf02697 | 47 | #define CONFIG_CMD_DATE |
acf02697 | 48 | #define CONFIG_CMD_SDRAM |
acf02697 JL |
49 | #define CONFIG_CMD_SAVES |
50 | #define CONFIG_CMD_BSP | |
51 | ||
c609719b WD |
52 | /************************************************************** |
53 | * I2C Stuff: | |
54 | * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address | |
55 | * 0x53. | |
56 | * Caution: on the same bus is the SPD (Serial Presens Detect | |
57 | * EEPROM of the SDRAM | |
58 | * The Atmel EEPROM uses 16Bit addressing. | |
59 | ***************************************************************/ | |
880540de DE |
60 | #define CONFIG_SYS_I2C |
61 | #define CONFIG_SYS_I2C_PPC4XX | |
62 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
63 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000 | |
64 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
c609719b | 65 | |
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 |
67 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
bb1f8b4f | 68 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
69 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
70 | #define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */ | |
c609719b | 71 | |
6d0f6bcf JCPV |
72 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
73 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ | |
c609719b WD |
74 | /* 64 byte page write mode using*/ |
75 | /* last 6 bits of the address */ | |
6d0f6bcf | 76 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
c609719b | 77 | |
c609719b WD |
78 | /*************************************************************** |
79 | * Definitions for Serial Presence Detect EEPROM address | |
80 | * (to get SDRAM settings) | |
81 | ***************************************************************/ | |
82 | #define SPD_EEPROM_ADDRESS 0x50 | |
83 | ||
c837dcb1 | 84 | #define CONFIG_BOARD_EARLY_INIT_F |
21be309b DM |
85 | #define CONFIG_BOARD_EARLY_INIT_R |
86 | ||
c609719b WD |
87 | /************************************************************** |
88 | * Environment definitions | |
89 | **************************************************************/ | |
90 | #define CONFIG_BAUDRATE 9600 /* STD Baudrate */ | |
91 | ||
c609719b WD |
92 | #define CONFIG_BOOTDELAY 5 |
93 | /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ | |
2afbe4ed | 94 | /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ |
53677ef1 | 95 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ |
c609719b | 96 | |
3e38691e | 97 | #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ |
c609719b WD |
98 | #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ |
99 | ||
100 | #define CONFIG_IPADDR 10.0.0.100 | |
101 | #define CONFIG_SERVERIP 10.0.0.1 | |
102 | #define CONFIG_PREBOOT | |
103 | /*************************************************************** | |
104 | * defines if the console is stored in the environment | |
105 | ***************************************************************/ | |
6d0f6bcf | 106 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ |
c609719b WD |
107 | /*************************************************************** |
108 | * defines if an overwrite_console function exists | |
109 | *************************************************************/ | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
111 | #define CONFIG_SYS_CONSOLE_INFO_QUIET | |
c609719b WD |
112 | /*************************************************************** |
113 | * defines if the overwrite_console should be stored in the | |
114 | * environment | |
115 | **************************************************************/ | |
6d0f6bcf | 116 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
c609719b WD |
117 | |
118 | /************************************************************** | |
119 | * loads config | |
120 | *************************************************************/ | |
121 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 122 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
c609719b | 123 | |
7205e407 | 124 | #define CONFIG_MISC_INIT_R |
c609719b WD |
125 | /*********************************************************** |
126 | * Miscellaneous configurable options | |
127 | **********************************************************/ | |
6d0f6bcf | 128 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
acf02697 | 129 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 130 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c609719b | 131 | #else |
6d0f6bcf | 132 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c609719b | 133 | #endif |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
135 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
136 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c609719b | 137 | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
139 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ | |
c609719b | 140 | |
550650dd | 141 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
550650dd SR |
142 | #define CONFIG_SYS_NS16550_SERIAL |
143 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
144 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
145 | ||
6d0f6bcf JCPV |
146 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
147 | #define CONFIG_SYS_BASE_BAUD 691200 | |
c609719b WD |
148 | |
149 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 150 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
c609719b WD |
151 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
152 | 57600, 115200, 230400, 460800, 921600 } | |
153 | ||
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
155 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
c609719b | 156 | |
c609719b WD |
157 | /*----------------------------------------------------------------------- |
158 | * PCI stuff | |
159 | *----------------------------------------------------------------------- | |
160 | */ | |
161 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ | |
162 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
163 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
164 | ||
165 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 166 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
c609719b WD |
167 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ |
168 | #define CONFIG_PCI_PNP /* pci plug-and-play */ | |
169 | /* resource configuration */ | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
171 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ | |
172 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
173 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
174 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
175 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
176 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
177 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
c609719b WD |
178 | |
179 | /*----------------------------------------------------------------------- | |
180 | * Start addresses for the final memory configuration | |
181 | * (Set up by the startup code) | |
6d0f6bcf | 182 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 183 | */ |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
185 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 | |
186 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
187 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
188 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ | |
c609719b WD |
189 | |
190 | /* | |
191 | * For booting Linux, the board info and command line data | |
192 | * have to be in the first 8 MB of memory, since this is | |
193 | * the maximum mapped by the Linux kernel during initialization. | |
194 | */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
196 | /*----------------------------------------------------------------------- |
197 | * FLASH organization | |
198 | */ | |
21be309b DM |
199 | #define CONFIG_SYS_UPDATE_FLASH_SIZE |
200 | #define CONFIG_SYS_FLASH_PROTECTION | |
201 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
202 | ||
203 | #define CONFIG_SYS_FLASH_CFI | |
204 | #define CONFIG_FLASH_CFI_DRIVER | |
205 | ||
206 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
c609719b | 207 | |
21be309b DM |
208 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
209 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
c609719b | 210 | |
c609719b WD |
211 | /* |
212 | * Init Memory Controller: | |
213 | */ | |
7205e407 WD |
214 | #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ |
215 | #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ | |
216 | /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ | |
217 | #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ | |
c609719b | 218 | |
c837dcb1 | 219 | #define CONFIG_BOARD_EARLY_INIT_F |
c609719b WD |
220 | |
221 | /* Configuration Port location */ | |
222 | #define CONFIG_PORT_ADDR 0xF4000000 | |
223 | #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 | |
224 | ||
c609719b WD |
225 | /*----------------------------------------------------------------------- |
226 | * Definitions for initial stack pointer and data area (in On Chip SRAM) | |
227 | */ | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
229 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 | |
230 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
231 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ | |
553f0982 | 232 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ |
25ddd1fb | 233 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 234 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c609719b | 235 | |
c609719b WD |
236 | /*********************************************************************** |
237 | * External peripheral base address | |
238 | ***********************************************************************/ | |
6d0f6bcf | 239 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 |
c609719b WD |
240 | |
241 | /*********************************************************************** | |
242 | * Last Stage Init | |
243 | ***********************************************************************/ | |
244 | #define CONFIG_LAST_STAGE_INIT | |
245 | /************************************************************ | |
246 | * Ethernet Stuff | |
247 | ***********************************************************/ | |
96e21f86 | 248 | #define CONFIG_PPC4xx_EMAC |
c609719b WD |
249 | #define CONFIG_MII 1 /* MII PHY management */ |
250 | #define CONFIG_PHY_ADDR 1 /* PHY address */ | |
c609719b WD |
251 | /************************************************************ |
252 | * RTC | |
253 | ***********************************************************/ | |
254 | #define CONFIG_RTC_MC146818 | |
255 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
256 | ||
257 | /************************************************************ | |
258 | * IDE/ATA stuff | |
259 | ************************************************************/ | |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
261 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
c609719b | 262 | |
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */ |
264 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ | |
265 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ | |
266 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ | |
267 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ | |
268 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ | |
c609719b WD |
269 | |
270 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
271 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
272 | #define CONFIG_IDE_RESET /* reset for ide supported... */ | |
273 | #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ | |
7205e407 | 274 | #define CONFIG_SUPPORT_VFAT |
c609719b WD |
275 | |
276 | /************************************************************ | |
277 | * ATAPI support (experimental) | |
278 | ************************************************************/ | |
279 | #define CONFIG_ATAPI /* enable ATAPI Support */ | |
280 | ||
281 | /************************************************************ | |
282 | * SCSI support (experimental) only SYM53C8xx supported | |
283 | ************************************************************/ | |
284 | #define CONFIG_SCSI_SYM53C8XX | |
6d0f6bcf JCPV |
285 | #define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */ |
286 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */ | |
287 | #define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */ | |
288 | #define CONFIG_SYS_SCSI_SPIN_UP_TIME 2 | |
c609719b WD |
289 | |
290 | /************************************************************ | |
291 | * Disk-On-Chip configuration | |
292 | ************************************************************/ | |
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ |
294 | #define CONFIG_SYS_DOC_SHORT_TIMEOUT | |
295 | #define CONFIG_SYS_DOC_SUPPORT_2000 | |
296 | #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM | |
c609719b WD |
297 | |
298 | /************************************************************ | |
299 | * DISK Partition support | |
300 | ************************************************************/ | |
301 | #define CONFIG_DOS_PARTITION | |
302 | #define CONFIG_MAC_PARTITION | |
303 | #define CONFIG_ISO_PARTITION /* Experimental */ | |
304 | ||
c609719b WD |
305 | /************************************************************ |
306 | * Video support | |
307 | ************************************************************/ | |
308 | #define CONFIG_VIDEO /*To enable video controller support */ | |
309 | #define CONFIG_VIDEO_CT69000 | |
310 | #define CONFIG_CFB_CONSOLE | |
311 | #define CONFIG_VIDEO_LOGO | |
312 | #define CONFIG_CONSOLE_EXTRA_INFO | |
313 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
314 | #define CONFIG_VIDEO_SW_CURSOR | |
315 | #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ | |
316 | ||
317 | /************************************************************ | |
318 | * USB support | |
319 | ************************************************************/ | |
320 | #define CONFIG_USB_UHCI | |
321 | #define CONFIG_USB_KEYBOARD | |
322 | #define CONFIG_USB_STORAGE | |
323 | ||
324 | /* Enable needed helper functions */ | |
52cb4d4f | 325 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
c609719b WD |
326 | |
327 | /************************************************************ | |
328 | * Debug support | |
329 | ************************************************************/ | |
acf02697 | 330 | #if defined(CONFIG_CMD_KGDB) |
c609719b | 331 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
c609719b WD |
332 | #endif |
333 | ||
a2663ea4 WD |
334 | /************************************************************ |
335 | * support BZIP2 compression | |
336 | ************************************************************/ | |
337 | #define CONFIG_BZIP2 1 | |
338 | ||
c609719b WD |
339 | /************************************************************ |
340 | * Ident | |
341 | ************************************************************/ | |
342 | #define VERSION_TAG "released" | |
f3e0de60 WD |
343 | #define CONFIG_ISO_STRING "MEV-10066-001" |
344 | #define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG | |
c609719b | 345 | |
c609719b | 346 | #endif /* __CONFIG_H */ |