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Commit | Line | Data |
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13fdf8a6 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
13fdf8a6 SR |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
c837dcb1 | 21 | #define CONFIG_PLU405 1 /* ...on a PLU405 board */ |
13fdf8a6 | 22 | |
2ae18241 | 23 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
a5ee5c69 | 24 | #define CONFIG_DISPLAY_BOARDINFO |
2ae18241 | 25 | |
c837dcb1 WD |
26 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
27 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
13fdf8a6 | 28 | |
a20b27a3 | 29 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ |
13fdf8a6 SR |
30 | |
31 | #define CONFIG_BAUDRATE 9600 | |
13fdf8a6 SR |
32 | |
33 | #undef CONFIG_BOOTARGS | |
a20b27a3 SR |
34 | #undef CONFIG_BOOTCOMMAND |
35 | ||
36 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
37 | ||
6d0f6bcf | 38 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
13fdf8a6 | 39 | |
f9fc6a58 | 40 | #undef CONFIG_HAS_ETH1 |
a20b27a3 | 41 | |
96e21f86 | 42 | #define CONFIG_PPC4xx_EMAC |
13fdf8a6 | 43 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 44 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 45 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
9ec367aa | 46 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ |
a20b27a3 SR |
47 | |
48 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
13fdf8a6 | 49 | |
acf02697 | 50 | |
a1aa0bb5 JL |
51 | /* |
52 | * BOOTP options | |
53 | */ | |
54 | #define CONFIG_BOOTP_BOOTFILESIZE | |
55 | #define CONFIG_BOOTP_BOOTPATH | |
56 | #define CONFIG_BOOTP_GATEWAY | |
57 | #define CONFIG_BOOTP_HOSTNAME | |
58 | ||
59 | ||
acf02697 JL |
60 | /* |
61 | * Command line configuration. | |
62 | */ | |
acf02697 JL |
63 | #define CONFIG_CMD_DHCP |
64 | #define CONFIG_CMD_PCI | |
65 | #define CONFIG_CMD_IRQ | |
66 | #define CONFIG_CMD_IDE | |
67 | #define CONFIG_CMD_FAT | |
acf02697 JL |
68 | #define CONFIG_CMD_NAND |
69 | #define CONFIG_CMD_DATE | |
70 | #define CONFIG_CMD_I2C | |
71 | #define CONFIG_CMD_MII | |
72 | #define CONFIG_CMD_PING | |
73 | #define CONFIG_CMD_EEPROM | |
17e65c21 | 74 | #define CONFIG_CMD_USB |
acf02697 | 75 | |
3bc1054c | 76 | #define CONFIG_OF_BOARD_SETUP |
13fdf8a6 SR |
77 | |
78 | #define CONFIG_MAC_PARTITION | |
79 | #define CONFIG_DOS_PARTITION | |
80 | ||
a20b27a3 SR |
81 | #define CONFIG_SUPPORT_VFAT |
82 | ||
c837dcb1 | 83 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
13fdf8a6 | 84 | |
c837dcb1 | 85 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ |
6d0f6bcf | 86 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
13fdf8a6 | 87 | |
c837dcb1 | 88 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
13fdf8a6 SR |
89 | |
90 | /* | |
91 | * Miscellaneous configurable options | |
92 | */ | |
6d0f6bcf | 93 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
13fdf8a6 | 94 | |
6d0f6bcf | 95 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
13fdf8a6 | 96 | |
acf02697 | 97 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 98 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
13fdf8a6 | 99 | #else |
6d0f6bcf | 100 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
13fdf8a6 | 101 | #endif |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
103 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
104 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
13fdf8a6 | 105 | |
6d0f6bcf | 106 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
13fdf8a6 | 107 | |
6d0f6bcf | 108 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
13fdf8a6 | 109 | |
a20b27a3 SR |
110 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
111 | ||
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
113 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
13fdf8a6 | 114 | |
550650dd | 115 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
550650dd SR |
116 | #define CONFIG_SYS_NS16550_SERIAL |
117 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
118 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
119 | ||
6d0f6bcf | 120 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 121 | #define CONFIG_SYS_BASE_BAUD 691200 |
13fdf8a6 SR |
122 | |
123 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 124 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
13fdf8a6 SR |
125 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
126 | 57600, 115200, 230400, 460800, 921600 } | |
127 | ||
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
129 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
13fdf8a6 | 130 | |
17e65c21 | 131 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
13fdf8a6 | 132 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
a20b27a3 SR |
133 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
134 | ||
c837dcb1 | 135 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
13fdf8a6 | 136 | |
6d0f6bcf | 137 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
13fdf8a6 | 138 | |
9ec367aa | 139 | /* |
13fdf8a6 | 140 | * NAND-FLASH stuff |
13fdf8a6 | 141 | */ |
6d0f6bcf | 142 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
6d0f6bcf | 143 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
bd84ee4c | 144 | #define NAND_BIG_DELAY_US 25 |
addb2e16 | 145 | |
6d0f6bcf JCPV |
146 | #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
147 | #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
148 | #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
149 | #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
13fdf8a6 | 150 | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
152 | #define CONFIG_SYS_NAND_QUIET 1 | |
a20b27a3 | 153 | |
9ec367aa | 154 | /* |
13fdf8a6 | 155 | * PCI stuff |
13fdf8a6 | 156 | */ |
a20b27a3 SR |
157 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
158 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
159 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
160 | ||
161 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 162 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
17e65c21 | 163 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
a20b27a3 SR |
164 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
165 | /* resource configuration */ | |
166 | ||
167 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
168 | ||
169 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
170 | ||
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
172 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
173 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
174 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
175 | #define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */ | |
176 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
177 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
178 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
179 | #define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */ | |
13fdf8a6 | 180 | |
9ec367aa | 181 | /* |
13fdf8a6 | 182 | * IDE/ATA stuff |
13fdf8a6 | 183 | */ |
c837dcb1 WD |
184 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
185 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
13fdf8a6 SR |
186 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
187 | ||
6d0f6bcf | 188 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
9ec367aa | 189 | /* max. 1 drives per IDE bus */ |
6d0f6bcf | 190 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) |
13fdf8a6 | 191 | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
193 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
13fdf8a6 | 194 | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
196 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */ | |
197 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
13fdf8a6 SR |
198 | |
199 | /* | |
200 | * For booting Linux, the board info and command line data | |
201 | * have to be in the first 8 MB of memory, since this is | |
202 | * the maximum mapped by the Linux kernel during initialization. | |
203 | */ | |
6d0f6bcf | 204 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
9ec367aa MF |
205 | |
206 | /* | |
13fdf8a6 SR |
207 | * FLASH organization |
208 | */ | |
9ec367aa | 209 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
13fdf8a6 | 210 | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
212 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
13fdf8a6 | 213 | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
215 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
13fdf8a6 | 216 | |
6d0f6bcf JCPV |
217 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
218 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */ | |
219 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */ | |
13fdf8a6 SR |
220 | /* |
221 | * The following defines are added for buggy IOP480 byte interface. | |
222 | * All other boards should use the standard values (CPCI405 etc.) | |
223 | */ | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
225 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
226 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
13fdf8a6 | 227 | |
6d0f6bcf | 228 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ |
13fdf8a6 | 229 | |
9ec367aa | 230 | /* |
13fdf8a6 SR |
231 | * Start addresses for the final memory configuration |
232 | * (Set up by the startup code) | |
6d0f6bcf | 233 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
13fdf8a6 | 234 | */ |
6d0f6bcf | 235 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
985edacc | 236 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
14d0a02a WD |
237 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
238 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) | |
985edacc | 239 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) |
13fdf8a6 | 240 | |
9ec367aa | 241 | /* |
13fdf8a6 SR |
242 | * Environment Variable setup |
243 | */ | |
bb1f8b4f | 244 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
245 | #define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */ |
246 | #define CONFIG_ENV_SIZE 0x700 | |
13fdf8a6 | 247 | |
9ec367aa MF |
248 | /* |
249 | * I2C EEPROM (24WC16) for environment | |
13fdf8a6 | 250 | */ |
880540de DE |
251 | #define CONFIG_SYS_I2C |
252 | #define CONFIG_SYS_I2C_PPC4XX | |
253 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
254 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
255 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
13fdf8a6 | 256 | |
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */ |
258 | #define CONFIG_SYS_EEPROM_WREN 1 | |
bd84ee4c | 259 | |
9ec367aa | 260 | /* 24WC16 */ |
6d0f6bcf | 261 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
9ec367aa | 262 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
264 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */ | |
9ec367aa MF |
265 | /* 16 byte page write mode using */ |
266 | /* last 4 bits of the address */ | |
6d0f6bcf | 267 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
13fdf8a6 | 268 | |
9ec367aa | 269 | /* |
13fdf8a6 SR |
270 | * External Bus Controller (EBC) Setup |
271 | */ | |
be0db3e3 MF |
272 | #define CAN0_BA 0xF0000000 /* CAN0 Base Address */ |
273 | #define CAN1_BA 0xF0000100 /* CAN1 Base Address */ | |
9ec367aa MF |
274 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ |
275 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ | |
276 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
277 | #define VGA_BA 0xF1000000 /* Epson VGA Base Address */ | |
6d0f6bcf | 278 | #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
9ec367aa MF |
279 | |
280 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
281 | /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ | |
6d0f6bcf | 282 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
9ec367aa | 283 | /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
6d0f6bcf | 284 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 |
13fdf8a6 | 285 | |
9ec367aa | 286 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
6d0f6bcf | 287 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
9ec367aa | 288 | /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ |
6d0f6bcf | 289 | #define CONFIG_SYS_EBC_PB1CR 0xF4018000 |
13fdf8a6 | 290 | |
9ec367aa MF |
291 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
292 | /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
6d0f6bcf | 293 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 |
9ec367aa | 294 | /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
6d0f6bcf | 295 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 |
13fdf8a6 | 296 | |
9ec367aa MF |
297 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ |
298 | /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
6d0f6bcf | 299 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 |
9ec367aa | 300 | /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
6d0f6bcf | 301 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 |
13fdf8a6 | 302 | |
9ec367aa | 303 | /* |
13fdf8a6 SR |
304 | * FPGA stuff |
305 | */ | |
6d0f6bcf | 306 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ |
13fdf8a6 SR |
307 | |
308 | /* FPGA internal regs */ | |
6d0f6bcf | 309 | #define CONFIG_SYS_FPGA_CTRL 0x000 |
13fdf8a6 SR |
310 | |
311 | /* FPGA Control Reg */ | |
6d0f6bcf JCPV |
312 | #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 |
313 | #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 | |
314 | #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 | |
13fdf8a6 | 315 | |
6d0f6bcf JCPV |
316 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
317 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
13fdf8a6 SR |
318 | |
319 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
320 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
321 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
322 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
323 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
324 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
13fdf8a6 | 325 | |
9ec367aa | 326 | /* |
13fdf8a6 SR |
327 | * Definitions for initial stack pointer and data area (in data cache) |
328 | */ | |
329 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 330 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
13fdf8a6 SR |
331 | |
332 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
333 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
334 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
335 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 336 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
13fdf8a6 | 337 | |
25ddd1fb | 338 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 339 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
13fdf8a6 | 340 | |
9ec367aa | 341 | /* |
13fdf8a6 SR |
342 | * Definitions for GPIO setup (PPC405EP specific) |
343 | * | |
c837dcb1 WD |
344 | * GPIO0[0] - External Bus Controller BLAST output |
345 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
13fdf8a6 SR |
346 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
347 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
348 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
349 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
350 | * GPIO0[28-29] - UART1 data signal input/output | |
351 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
352 | */ | |
afabb498 SR |
353 | #define CONFIG_SYS_GPIO0_OSRL 0x00000550 |
354 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 | |
355 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 | |
356 | #define CONFIG_SYS_GPIO0_ISR1H 0x15555445 | |
6d0f6bcf | 357 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 |
afabb498 | 358 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 |
6d0f6bcf | 359 | #define CONFIG_SYS_GPIO0_TCR 0x77FE0014 |
13fdf8a6 | 360 | |
6d0f6bcf JCPV |
361 | #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) |
362 | #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0) | |
13fdf8a6 | 363 | |
13fdf8a6 | 364 | /* |
9ec367aa | 365 | * Default speed selection (cpu_plb_opb_ebc) in MHz. |
13fdf8a6 SR |
366 | * This value will be set if iic boot eprom is disabled. |
367 | */ | |
17e65c21 | 368 | #if 1 |
c837dcb1 WD |
369 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
370 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
13fdf8a6 SR |
371 | #endif |
372 | #if 0 | |
c837dcb1 WD |
373 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
374 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
13fdf8a6 | 375 | #endif |
17e65c21 | 376 | #if 0 |
c837dcb1 WD |
377 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
378 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
13fdf8a6 SR |
379 | #endif |
380 | ||
17e65c21 MF |
381 | /* |
382 | * PCI OHCI controller | |
383 | */ | |
384 | #define CONFIG_USB_OHCI_NEW 1 | |
385 | #define CONFIG_PCI_OHCI 1 | |
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 |
387 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
388 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
17e65c21 MF |
389 | #define CONFIG_USB_STORAGE 1 |
390 | ||
985edacc MF |
391 | /* |
392 | * UBI | |
393 | */ | |
394 | #define CONFIG_CMD_UBI | |
395 | #define CONFIG_RBTREE | |
396 | #define CONFIG_MTD_DEVICE | |
397 | #define CONFIG_MTD_PARTITIONS | |
398 | #define CONFIG_CMD_MTDPARTS | |
399 | #define CONFIG_LZO | |
400 | ||
13fdf8a6 | 401 | #endif /* __CONFIG_H */ |