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13fdf8a6 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
c837dcb1 WD |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
38 | #define CONFIG_PLU405 1 /* ...on a PLU405 board */ | |
13fdf8a6 | 39 | |
c837dcb1 WD |
40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
41 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
13fdf8a6 | 42 | |
a20b27a3 | 43 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ |
13fdf8a6 SR |
44 | |
45 | #define CONFIG_BAUDRATE 9600 | |
13fdf8a6 SR |
46 | |
47 | #undef CONFIG_BOOTARGS | |
a20b27a3 SR |
48 | #undef CONFIG_BOOTCOMMAND |
49 | ||
50 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
51 | ||
6d0f6bcf | 52 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
13fdf8a6 | 53 | |
a20b27a3 | 54 | #define CONFIG_NET_MULTI 1 |
f9fc6a58 | 55 | #undef CONFIG_HAS_ETH1 |
a20b27a3 | 56 | |
13fdf8a6 | 57 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 58 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 59 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
9ec367aa | 60 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ |
a20b27a3 SR |
61 | |
62 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
13fdf8a6 | 63 | |
acf02697 | 64 | |
a1aa0bb5 JL |
65 | /* |
66 | * BOOTP options | |
67 | */ | |
68 | #define CONFIG_BOOTP_BOOTFILESIZE | |
69 | #define CONFIG_BOOTP_BOOTPATH | |
70 | #define CONFIG_BOOTP_GATEWAY | |
71 | #define CONFIG_BOOTP_HOSTNAME | |
72 | ||
73 | ||
acf02697 JL |
74 | /* |
75 | * Command line configuration. | |
76 | */ | |
77 | #include <config_cmd_default.h> | |
78 | ||
79 | #define CONFIG_CMD_DHCP | |
80 | #define CONFIG_CMD_PCI | |
81 | #define CONFIG_CMD_IRQ | |
82 | #define CONFIG_CMD_IDE | |
83 | #define CONFIG_CMD_FAT | |
84 | #define CONFIG_CMD_ELF | |
85 | #define CONFIG_CMD_NAND | |
86 | #define CONFIG_CMD_DATE | |
87 | #define CONFIG_CMD_I2C | |
88 | #define CONFIG_CMD_MII | |
89 | #define CONFIG_CMD_PING | |
90 | #define CONFIG_CMD_EEPROM | |
17e65c21 | 91 | #define CONFIG_CMD_USB |
acf02697 | 92 | |
3bc1054c MF |
93 | #define CONFIG_OF_LIBFDT |
94 | #define CONFIG_OF_BOARD_SETUP | |
13fdf8a6 SR |
95 | |
96 | #define CONFIG_MAC_PARTITION | |
97 | #define CONFIG_DOS_PARTITION | |
98 | ||
a20b27a3 SR |
99 | #define CONFIG_SUPPORT_VFAT |
100 | ||
101 | #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ | |
a20b27a3 | 102 | |
c837dcb1 | 103 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
13fdf8a6 | 104 | |
c837dcb1 | 105 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ |
6d0f6bcf | 106 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
13fdf8a6 | 107 | |
c837dcb1 | 108 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
13fdf8a6 SR |
109 | |
110 | /* | |
111 | * Miscellaneous configurable options | |
112 | */ | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
114 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
13fdf8a6 | 115 | |
6d0f6bcf JCPV |
116 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
117 | #ifdef CONFIG_SYS_HUSH_PARSER | |
118 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
13fdf8a6 SR |
119 | #endif |
120 | ||
acf02697 | 121 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 122 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
13fdf8a6 | 123 | #else |
6d0f6bcf | 124 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
13fdf8a6 | 125 | #endif |
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
127 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
128 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
13fdf8a6 | 129 | |
6d0f6bcf | 130 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
13fdf8a6 | 131 | |
6d0f6bcf | 132 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
13fdf8a6 | 133 | |
a20b27a3 SR |
134 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
135 | ||
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
137 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
13fdf8a6 | 138 | |
6d0f6bcf JCPV |
139 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
140 | #define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ | |
141 | #define CONFIG_SYS_BASE_BAUD 691200 | |
c837dcb1 | 142 | #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ |
13fdf8a6 SR |
143 | |
144 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 145 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
13fdf8a6 SR |
146 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
147 | 57600, 115200, 230400, 460800, 921600 } | |
148 | ||
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
150 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
13fdf8a6 | 151 | |
6d0f6bcf | 152 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
13fdf8a6 | 153 | |
17e65c21 | 154 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
13fdf8a6 | 155 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
a20b27a3 SR |
156 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
157 | ||
158 | /* Only interrupt boot if space is pressed */ | |
159 | /* If a long serial cable is connected but */ | |
160 | /* other end is dead, garbage will be read */ | |
f2302d44 SR |
161 | #define CONFIG_AUTOBOOT_KEYED 1 |
162 | #define CONFIG_AUTOBOOT_PROMPT \ | |
163 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
a20b27a3 SR |
164 | #undef CONFIG_AUTOBOOT_DELAY_STR |
165 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
13fdf8a6 | 166 | |
c837dcb1 | 167 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
13fdf8a6 | 168 | |
6d0f6bcf | 169 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
13fdf8a6 | 170 | |
9ec367aa | 171 | /* |
13fdf8a6 | 172 | * NAND-FLASH stuff |
13fdf8a6 | 173 | */ |
6d0f6bcf | 174 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
bd84ee4c | 175 | #define NAND_MAX_CHIPS 1 |
6d0f6bcf | 176 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
bd84ee4c | 177 | #define NAND_BIG_DELAY_US 25 |
addb2e16 | 178 | |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
180 | #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
181 | #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
182 | #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
13fdf8a6 | 183 | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
185 | #define CONFIG_SYS_NAND_QUIET 1 | |
a20b27a3 | 186 | |
9ec367aa | 187 | /* |
13fdf8a6 | 188 | * PCI stuff |
13fdf8a6 | 189 | */ |
a20b27a3 SR |
190 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
191 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
192 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
193 | ||
194 | #define CONFIG_PCI /* include pci support */ | |
17e65c21 | 195 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
a20b27a3 SR |
196 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
197 | /* resource configuration */ | |
198 | ||
199 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
200 | ||
201 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
202 | ||
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
204 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
205 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
206 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
207 | #define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */ | |
208 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
209 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
210 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
211 | #define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */ | |
13fdf8a6 | 212 | |
9ec367aa | 213 | /* |
13fdf8a6 | 214 | * IDE/ATA stuff |
13fdf8a6 | 215 | */ |
c837dcb1 WD |
216 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
217 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
13fdf8a6 SR |
218 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
219 | ||
6d0f6bcf | 220 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
9ec367aa | 221 | /* max. 1 drives per IDE bus */ |
6d0f6bcf | 222 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) |
13fdf8a6 | 223 | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
225 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
13fdf8a6 | 226 | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
228 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */ | |
229 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
13fdf8a6 SR |
230 | |
231 | /* | |
232 | * For booting Linux, the board info and command line data | |
233 | * have to be in the first 8 MB of memory, since this is | |
234 | * the maximum mapped by the Linux kernel during initialization. | |
235 | */ | |
6d0f6bcf | 236 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
9ec367aa MF |
237 | |
238 | /* | |
13fdf8a6 SR |
239 | * FLASH organization |
240 | */ | |
9ec367aa | 241 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
13fdf8a6 | 242 | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
244 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
13fdf8a6 | 245 | |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
247 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
13fdf8a6 | 248 | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
250 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */ | |
251 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */ | |
13fdf8a6 SR |
252 | /* |
253 | * The following defines are added for buggy IOP480 byte interface. | |
254 | * All other boards should use the standard values (CPCI405 etc.) | |
255 | */ | |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
257 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
258 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
13fdf8a6 | 259 | |
6d0f6bcf | 260 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ |
13fdf8a6 | 261 | |
9ec367aa | 262 | /* |
13fdf8a6 SR |
263 | * Start addresses for the final memory configuration |
264 | * (Set up by the startup code) | |
6d0f6bcf | 265 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
13fdf8a6 | 266 | */ |
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
268 | #define CONFIG_SYS_FLASH_BASE 0xFFFA0000 | |
269 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
270 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384kB for Monitor */ | |
271 | #define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserve 384kB for malloc() */ | |
13fdf8a6 | 272 | |
9ec367aa | 273 | /* |
13fdf8a6 SR |
274 | * Environment Variable setup |
275 | */ | |
bb1f8b4f | 276 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
277 | #define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */ |
278 | #define CONFIG_ENV_SIZE 0x700 | |
13fdf8a6 | 279 | |
9ec367aa MF |
280 | /* |
281 | * I2C EEPROM (24WC16) for environment | |
13fdf8a6 SR |
282 | */ |
283 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
285 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
13fdf8a6 | 286 | |
6d0f6bcf JCPV |
287 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */ |
288 | #define CONFIG_SYS_EEPROM_WREN 1 | |
bd84ee4c | 289 | |
9ec367aa | 290 | /* 24WC16 */ |
6d0f6bcf | 291 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
9ec367aa | 292 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
294 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */ | |
9ec367aa MF |
295 | /* 16 byte page write mode using */ |
296 | /* last 4 bits of the address */ | |
6d0f6bcf | 297 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
13fdf8a6 | 298 | |
9ec367aa | 299 | /* |
13fdf8a6 SR |
300 | * External Bus Controller (EBC) Setup |
301 | */ | |
9ec367aa MF |
302 | #define CAN_BA 0xF0000000 /* CAN Base Address */ |
303 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ | |
304 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ | |
305 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
306 | #define VGA_BA 0xF1000000 /* Epson VGA Base Address */ | |
6d0f6bcf | 307 | #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
9ec367aa MF |
308 | |
309 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
310 | /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
9ec367aa | 312 | /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
6d0f6bcf | 313 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 |
13fdf8a6 | 314 | |
9ec367aa | 315 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
6d0f6bcf | 316 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
9ec367aa | 317 | /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ |
6d0f6bcf | 318 | #define CONFIG_SYS_EBC_PB1CR 0xF4018000 |
13fdf8a6 | 319 | |
9ec367aa MF |
320 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
321 | /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
6d0f6bcf | 322 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 |
9ec367aa | 323 | /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
6d0f6bcf | 324 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 |
13fdf8a6 | 325 | |
9ec367aa MF |
326 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ |
327 | /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
6d0f6bcf | 328 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 |
9ec367aa | 329 | /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
6d0f6bcf | 330 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 |
13fdf8a6 | 331 | |
9ec367aa | 332 | /* |
13fdf8a6 SR |
333 | * FPGA stuff |
334 | */ | |
6d0f6bcf | 335 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ |
13fdf8a6 SR |
336 | |
337 | /* FPGA internal regs */ | |
6d0f6bcf | 338 | #define CONFIG_SYS_FPGA_CTRL 0x000 |
13fdf8a6 SR |
339 | |
340 | /* FPGA Control Reg */ | |
6d0f6bcf JCPV |
341 | #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 |
342 | #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 | |
343 | #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 | |
13fdf8a6 | 344 | |
6d0f6bcf JCPV |
345 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
346 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
13fdf8a6 SR |
347 | |
348 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
350 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
351 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
352 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
353 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
13fdf8a6 | 354 | |
9ec367aa | 355 | /* |
13fdf8a6 SR |
356 | * Definitions for initial stack pointer and data area (in data cache) |
357 | */ | |
358 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 359 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
13fdf8a6 SR |
360 | |
361 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
363 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
364 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
365 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ | |
13fdf8a6 | 366 | |
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
368 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
369 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
13fdf8a6 | 370 | |
9ec367aa | 371 | /* |
13fdf8a6 SR |
372 | * Definitions for GPIO setup (PPC405EP specific) |
373 | * | |
c837dcb1 WD |
374 | * GPIO0[0] - External Bus Controller BLAST output |
375 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
13fdf8a6 SR |
376 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
377 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
378 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
379 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
380 | * GPIO0[28-29] - UART1 data signal input/output | |
381 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
382 | */ | |
6d0f6bcf JCPV |
383 | #define CONFIG_SYS_GPIO0_OSRH 0x00000550 |
384 | #define CONFIG_SYS_GPIO0_OSRL 0x00000110 | |
385 | #define CONFIG_SYS_GPIO0_ISR1H 0x00000000 | |
386 | #define CONFIG_SYS_GPIO0_ISR1L 0x15555445 | |
387 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 | |
388 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 | |
389 | #define CONFIG_SYS_GPIO0_TCR 0x77FE0014 | |
13fdf8a6 | 390 | |
6d0f6bcf JCPV |
391 | #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) |
392 | #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0) | |
13fdf8a6 SR |
393 | |
394 | /* | |
395 | * Internal Definitions | |
396 | * | |
397 | * Boot Flags | |
398 | */ | |
9ec367aa MF |
399 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
400 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
13fdf8a6 SR |
401 | |
402 | /* | |
9ec367aa | 403 | * Default speed selection (cpu_plb_opb_ebc) in MHz. |
13fdf8a6 SR |
404 | * This value will be set if iic boot eprom is disabled. |
405 | */ | |
17e65c21 | 406 | #if 1 |
c837dcb1 WD |
407 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
408 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
13fdf8a6 SR |
409 | #endif |
410 | #if 0 | |
c837dcb1 WD |
411 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
412 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
13fdf8a6 | 413 | #endif |
17e65c21 | 414 | #if 0 |
c837dcb1 WD |
415 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
416 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
13fdf8a6 SR |
417 | #endif |
418 | ||
17e65c21 MF |
419 | /* |
420 | * PCI OHCI controller | |
421 | */ | |
422 | #define CONFIG_USB_OHCI_NEW 1 | |
423 | #define CONFIG_PCI_OHCI 1 | |
6d0f6bcf JCPV |
424 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 |
425 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
426 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
17e65c21 MF |
427 | #define CONFIG_USB_STORAGE 1 |
428 | ||
13fdf8a6 | 429 | #endif /* __CONFIG_H */ |