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efa329cb | 1 | /* |
414eec35 | 2 | * (C) Copyright 2003-2005 |
efa329cb WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | ||
32 | #define CONFIG_MPC5200 | |
62b4ac98 | 33 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
efa329cb WD |
34 | #define CONFIG_PM520 1 /* ... on PM520 board */ |
35 | ||
6d0f6bcf | 36 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ |
efa329cb | 37 | |
49822e23 WD |
38 | #define CONFIG_MISC_INIT_R |
39 | ||
efa329cb WD |
40 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
41 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
42 | ||
31d82672 BB |
43 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
44 | ||
efa329cb WD |
45 | /* |
46 | * Serial console configuration | |
47 | */ | |
48 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
49 | #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ | |
6d0f6bcf | 50 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
efa329cb WD |
51 | |
52 | ||
53 | #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ | |
54 | /* | |
55 | * PCI Mapping: | |
56 | * 0x40000000 - 0x4fffffff - PCI Memory | |
57 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
58 | */ | |
59 | #define CONFIG_PCI 1 | |
60 | #define CONFIG_PCI_PNP 1 | |
61 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 62 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
efa329cb WD |
63 | |
64 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
65 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
66 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
67 | ||
68 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
69 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
70 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
71 | ||
72 | #define CONFIG_NET_MULTI 1 | |
63ff004c | 73 | #define CONFIG_MII 1 |
efa329cb | 74 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 75 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
efa329cb WD |
76 | #undef CONFIG_NS8382X |
77 | ||
efa329cb WD |
78 | #endif |
79 | ||
49822e23 WD |
80 | /* Partitions */ |
81 | #define CONFIG_DOS_PARTITION | |
82 | ||
83 | /* USB */ | |
84 | #if 1 | |
85 | #define CONFIG_USB_OHCI | |
49822e23 | 86 | #define CONFIG_USB_STORAGE |
49822e23 WD |
87 | #endif |
88 | ||
acf02697 | 89 | #if !defined(CONFIG_BOOT_ROM) |
addb2e16 | 90 | /* DoC requires legacy NAND for now */ |
cc4a0cee | 91 | #define CONFIG_NAND_LEGACY |
49822e23 WD |
92 | #endif |
93 | ||
acf02697 | 94 | |
a1aa0bb5 JL |
95 | /* |
96 | * BOOTP options | |
97 | */ | |
98 | #define CONFIG_BOOTP_BOOTFILESIZE | |
99 | #define CONFIG_BOOTP_BOOTPATH | |
100 | #define CONFIG_BOOTP_GATEWAY | |
101 | #define CONFIG_BOOTP_HOSTNAME | |
102 | ||
103 | ||
efa329cb | 104 | /* |
acf02697 | 105 | * Command line configuration. |
efa329cb | 106 | */ |
acf02697 JL |
107 | #include <config_cmd_default.h> |
108 | ||
109 | #define CONFIG_CMD_BEDBUG | |
110 | #define CONFIG_CMD_DATE | |
111 | #define CONFIG_CMD_DHCP | |
112 | #define CONFIG_CMD_EEPROM | |
113 | #define CONFIG_CMD_FAT | |
114 | #define CONFIG_CMD_I2C | |
115 | #define CONFIG_CMD_IDE | |
116 | #define CONFIG_CMD_NFS | |
117 | #define CONFIG_CMD_SNTP | |
118 | #define CONFIG_CMD_USB | |
119 | ||
120 | #if !defined(CONFIG_BOOT_ROM) | |
121 | #define CONFIG_CMD_DOC | |
122 | #endif | |
123 | ||
124 | #if defined(CONFIG_MPC5200) | |
125 | #define CONFIG_CMD_PCI | |
126 | #endif | |
127 | ||
efa329cb WD |
128 | |
129 | /* | |
130 | * Autobooting | |
131 | */ | |
132 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
49822e23 WD |
133 | |
134 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 135 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
49822e23 WD |
136 | "echo" |
137 | ||
138 | #undef CONFIG_BOOTARGS | |
139 | ||
140 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
141 | "netdev=eth0\0" \ | |
142 | "hostname=pm520\0" \ | |
143 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 144 | "nfsroot=${serverip}:${rootpath}\0" \ |
49822e23 | 145 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
146 | "addip=setenv bootargs ${bootargs} " \ |
147 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
148 | ":${hostname}:${netdev}:off panic=1\0" \ | |
49822e23 | 149 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 150 | "bootm ${kernel_addr}\0" \ |
49822e23 | 151 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
152 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
153 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
49822e23 WD |
154 | "rootpath=/opt/eldk30/ppc_82xx\0" \ |
155 | "bootfile=/tftpboot/PM520/uImage\0" \ | |
156 | "" | |
157 | ||
158 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
efa329cb WD |
159 | |
160 | #if defined(CONFIG_MPC5200) | |
161 | /* | |
162 | * IPB Bus clocking configuration. | |
163 | */ | |
6d0f6bcf | 164 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
efa329cb WD |
165 | #endif |
166 | /* | |
167 | * I2C configuration | |
168 | */ | |
169 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 170 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
efa329cb | 171 | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
173 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
efa329cb WD |
174 | |
175 | /* | |
176 | * EEPROM configuration | |
177 | */ | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 |
179 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
180 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
181 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
efa329cb WD |
182 | |
183 | /* | |
184 | * RTC configuration | |
185 | */ | |
186 | #define CONFIG_RTC_PCF8563 | |
6d0f6bcf | 187 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
efa329cb WD |
188 | |
189 | /* | |
49822e23 WD |
190 | * Disk-On-Chip configuration |
191 | */ | |
192 | ||
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_DOC_SHORT_TIMEOUT |
194 | #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ | |
49822e23 | 195 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_DOC_SUPPORT_2000 |
197 | #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM | |
198 | #define CONFIG_SYS_DOC_BASE 0xE0000000 | |
199 | #define CONFIG_SYS_DOC_SIZE 0x00100000 | |
49822e23 WD |
200 | |
201 | #if defined(CONFIG_BOOT_ROM) | |
202 | /* | |
203 | * Flash configuration (8,16 or 32 MB) | |
204 | * TEXT base always at 0xFFF00000 | |
205 | * ENV_ADDR always at 0xFFF40000 | |
c7428d49 WD |
206 | * FLASH_BASE at 0xFA000000 for 64 MB |
207 | * 0xFC000000 for 32 MB | |
49822e23 WD |
208 | * 0xFD000000 for 16 MB |
209 | * 0xFD800000 for 8 MB | |
210 | */ | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_FLASH_BASE 0xFA000000 |
212 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 | |
213 | #define CONFIG_SYS_BOOTROM_BASE 0xFFF00000 | |
214 | #define CONFIG_SYS_BOOTROM_SIZE 0x00080000 | |
0e8d1586 | 215 | #define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000) |
49822e23 WD |
216 | #else |
217 | /* | |
218 | * Flash configuration (8,16 or 32 MB) | |
219 | * TEXT base always at 0xFFF00000 | |
220 | * ENV_ADDR always at 0xFFF40000 | |
c7428d49 WD |
221 | * FLASH_BASE at 0xFC000000 for 64 MB |
222 | * 0xFE000000 for 32 MB | |
49822e23 WD |
223 | * 0xFF000000 for 16 MB |
224 | * 0xFF800000 for 8 MB | |
efa329cb | 225 | */ |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 |
227 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 | |
0e8d1586 | 228 | #define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000) |
49822e23 | 229 | #endif |
6d0f6bcf | 230 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
efa329cb | 231 | |
6d0f6bcf | 232 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ |
efa329cb | 233 | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
235 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
236 | #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ | |
237 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ | |
238 | #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
efa329cb WD |
239 | |
240 | #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ | |
241 | ||
242 | #undef CONFIG_FLASH_16BIT /* Flash is 32-bit */ | |
243 | ||
244 | ||
245 | /* | |
246 | * Environment settings | |
247 | */ | |
5a1aceb0 | 248 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
249 | #define CONFIG_ENV_SIZE 0x10000 |
250 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
efa329cb WD |
251 | #define CONFIG_ENV_OVERWRITE 1 |
252 | ||
253 | /* | |
254 | * Memory map | |
255 | */ | |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_MBAR 0xf0000000 |
257 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
258 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
efa329cb WD |
259 | |
260 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
262 | #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ | |
efa329cb WD |
263 | |
264 | ||
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
266 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
267 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
efa329cb | 268 | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
270 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
271 | # define CONFIG_SYS_RAMBOOT 1 | |
efa329cb WD |
272 | #endif |
273 | ||
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
275 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
276 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
efa329cb WD |
277 | |
278 | /* | |
279 | * Ethernet configuration | |
280 | */ | |
62b4ac98 WD |
281 | #define CONFIG_MPC5xxx_FEC 1 |
282 | /* | |
283 | * Define CONFIG_FEC_10MBIT to force FEC at 10Mb | |
284 | */ | |
285 | /* #define CONFIG_FEC_10MBIT 1 */ | |
efa329cb WD |
286 | #define CONFIG_PHY_ADDR 0x00 |
287 | ||
288 | /* | |
289 | * GPIO configuration | |
290 | */ | |
6d0f6bcf | 291 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 |
efa329cb WD |
292 | |
293 | /* | |
294 | * Miscellaneous configurable options | |
295 | */ | |
6d0f6bcf JCPV |
296 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
297 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
acf02697 | 298 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 299 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
efa329cb | 300 | #else |
6d0f6bcf | 301 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
efa329cb | 302 | #endif |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
304 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
305 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
efa329cb | 306 | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
308 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
efa329cb | 309 | |
6d0f6bcf | 310 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
efa329cb | 311 | |
6d0f6bcf | 312 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
efa329cb | 313 | |
6d0f6bcf | 314 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
acf02697 | 315 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 316 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
acf02697 JL |
317 | #endif |
318 | ||
efa329cb WD |
319 | /* |
320 | * Various low-level settings | |
321 | */ | |
322 | #if defined(CONFIG_MPC5200) | |
6d0f6bcf JCPV |
323 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
324 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
efa329cb | 325 | #else |
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_HID0_INIT 0 |
327 | #define CONFIG_SYS_HID0_FINAL 0 | |
efa329cb WD |
328 | #endif |
329 | ||
49822e23 | 330 | #if defined(CONFIG_BOOT_ROM) |
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE |
332 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE | |
333 | #define CONFIG_SYS_BOOTCS_CFG 0x00047800 | |
334 | #define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE | |
335 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE | |
336 | #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE | |
337 | #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE | |
338 | #define CONFIG_SYS_CS1_CFG 0x0004FF00 | |
49822e23 | 339 | #else |
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
341 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
342 | #define CONFIG_SYS_BOOTCS_CFG 0x0004FF00 | |
343 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
344 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
345 | #define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE | |
346 | #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE | |
347 | #define CONFIG_SYS_CS1_CFG 0x00047800 | |
49822e23 | 348 | #endif |
efa329cb | 349 | |
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_CS_BURST 0x00000000 |
351 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
efa329cb | 352 | |
6d0f6bcf | 353 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
efa329cb | 354 | |
49822e23 WD |
355 | /*----------------------------------------------------------------------- |
356 | * USB stuff | |
357 | *----------------------------------------------------------------------- | |
358 | */ | |
359 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
360 | #define CONFIG_USB_CONFIG 0x00005000 | |
361 | ||
362 | /*----------------------------------------------------------------------- | |
363 | * IDE/ATA stuff Supports IDE harddisk | |
364 | *----------------------------------------------------------------------- | |
365 | */ | |
366 | ||
367 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
368 | ||
369 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
370 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
371 | ||
372 | #undef CONFIG_IDE_RESET /* reset for ide supported */ | |
373 | #define CONFIG_IDE_PREINIT | |
374 | ||
6d0f6bcf JCPV |
375 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
376 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */ | |
49822e23 | 377 | |
6d0f6bcf | 378 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
49822e23 | 379 | |
6d0f6bcf | 380 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
49822e23 WD |
381 | |
382 | /* Offset for data I/O */ | |
6d0f6bcf | 383 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
49822e23 WD |
384 | |
385 | /* Offset for normal register accesses */ | |
6d0f6bcf | 386 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
49822e23 WD |
387 | |
388 | /* Offset for alternate registers */ | |
6d0f6bcf | 389 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
49822e23 WD |
390 | |
391 | /* Interval between registers */ | |
6d0f6bcf | 392 | #define CONFIG_SYS_ATA_STRIDE 4 |
49822e23 | 393 | |
efa329cb | 394 | #endif /* __CONFIG_H */ |