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Commit | Line | Data |
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0f8c9768 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2001-2005 |
0f8c9768 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0f8c9768 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
6d0f6bcf | 15 | #undef CONFIG_SYS_RAMBOOT |
0f8c9768 WD |
16 | |
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
21 | ||
22 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ | |
23 | #define CONFIG_PM826 1 /* ...on a PM8260 module */ | |
9c4c5ae3 | 24 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
0f8c9768 | 25 | |
2ae18241 WD |
26 | #ifndef CONFIG_SYS_TEXT_BASE |
27 | #define CONFIG_SYS_TEXT_BASE 0xFF000000 /* Standard: boot 64-bit flash */ | |
28 | #endif | |
29 | ||
aacf9a49 WD |
30 | #undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ |
31 | ||
0f8c9768 WD |
32 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
33 | ||
32bf3d14 | 34 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
0f8c9768 WD |
35 | |
36 | #undef CONFIG_BOOTARGS | |
37 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 WD |
38 | "bootp; " \ |
39 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
40 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
0f8c9768 WD |
41 | "bootm" |
42 | ||
43 | /* enable I2C and select the hardware/software driver */ | |
44 | #undef CONFIG_HARD_I2C | |
45 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
6d0f6bcf JCPV |
46 | # define CONFIG_SYS_I2C_SPEED 50000 |
47 | # define CONFIG_SYS_I2C_SLAVE 0xFE | |
0f8c9768 WD |
48 | /* |
49 | * Software (bit-bang) I2C driver configuration | |
50 | */ | |
51 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
52 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
53 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
54 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
55 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
56 | else iop->pdat &= ~0x00010000 | |
57 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
58 | else iop->pdat &= ~0x00020000 | |
59 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
60 | ||
61 | ||
62 | #define CONFIG_RTC_PCF8563 | |
6d0f6bcf | 63 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
0f8c9768 WD |
64 | |
65 | /* | |
66 | * select serial console configuration | |
67 | * | |
68 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
69 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
70 | * for SCC). | |
71 | * | |
72 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
73 | * defined elsewhere (for example, on the cogent platform, there are serial | |
74 | * ports on the motherboard which are used for the serial console - see | |
75 | * cogent/cma101/serial.[ch]). | |
76 | */ | |
77 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
78 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
79 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
80 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
81 | ||
82 | /* | |
83 | * select ethernet configuration | |
84 | * | |
aacf9a49 WD |
85 | * if CONFIG_ETHER_ON_SCC is selected, then |
86 | * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) | |
aacf9a49 WD |
87 | * |
88 | * if CONFIG_ETHER_ON_FCC is selected, then | |
89 | * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected | |
0f8c9768 WD |
90 | * |
91 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 92 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
0f8c9768 | 93 | */ |
0f8c9768 | 94 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
0f8c9768 | 95 | |
aacf9a49 WD |
96 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
97 | #define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ | |
98 | ||
99 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
0f8c9768 WD |
100 | /* |
101 | * - Rx-CLK is CLK11 | |
102 | * - Tx-CLK is CLK10 | |
aacf9a49 WD |
103 | */ |
104 | #define CONFIG_ETHER_ON_FCC1 | |
6d0f6bcf | 105 | # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
aacf9a49 | 106 | #ifndef CONFIG_DB_CR826_J30x_ON |
6d0f6bcf | 107 | # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) |
aacf9a49 | 108 | #else |
6d0f6bcf | 109 | # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) |
aacf9a49 WD |
110 | #endif |
111 | /* | |
112 | * - Rx-CLK is CLK15 | |
113 | * - Tx-CLK is CLK14 | |
114 | */ | |
115 | #define CONFIG_ETHER_ON_FCC2 | |
6d0f6bcf JCPV |
116 | # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
117 | # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
aacf9a49 | 118 | /* |
0f8c9768 WD |
119 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
120 | * - Enable Full Duplex in FSMR | |
121 | */ | |
6d0f6bcf JCPV |
122 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
123 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
0f8c9768 | 124 | |
0f8c9768 WD |
125 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
126 | #define CONFIG_8260_CLKIN 64000000 /* in Hz */ | |
127 | ||
128 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) | |
129 | #define CONFIG_BAUDRATE 230400 | |
130 | #else | |
131 | #define CONFIG_BAUDRATE 9600 | |
132 | #endif | |
133 | ||
134 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 135 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
0f8c9768 WD |
136 | |
137 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
138 | ||
18225e8d JL |
139 | /* |
140 | * BOOTP options | |
141 | */ | |
142 | #define CONFIG_BOOTP_SUBNETMASK | |
143 | #define CONFIG_BOOTP_GATEWAY | |
144 | #define CONFIG_BOOTP_HOSTNAME | |
145 | #define CONFIG_BOOTP_BOOTPATH | |
146 | #define CONFIG_BOOTP_BOOTFILESIZE | |
0f8c9768 | 147 | |
acf02697 JL |
148 | |
149 | /* | |
150 | * Command line configuration. | |
151 | */ | |
152 | #include <config_cmd_default.h> | |
153 | ||
154 | #define CONFIG_CMD_BEDBUG | |
155 | #define CONFIG_CMD_DATE | |
156 | #define CONFIG_CMD_DHCP | |
acf02697 JL |
157 | #define CONFIG_CMD_EEPROM |
158 | #define CONFIG_CMD_I2C | |
159 | #define CONFIG_CMD_NFS | |
160 | #define CONFIG_CMD_SNTP | |
161 | ||
5d232d0e | 162 | #ifdef CONFIG_PCI |
842033e6 | 163 | #define CONFIG_PCI_INDIRECT_BRIDGE |
acf02697 JL |
164 | #define CONFIG_CMD_PCI |
165 | #endif | |
166 | ||
0f8c9768 WD |
167 | /* |
168 | * Miscellaneous configurable options | |
169 | */ | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
171 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
acf02697 | 172 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 173 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0f8c9768 | 174 | #else |
6d0f6bcf | 175 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0f8c9768 | 176 | #endif |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
178 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
179 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0f8c9768 | 180 | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
182 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
0f8c9768 | 183 | |
6d0f6bcf | 184 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
0f8c9768 | 185 | |
6d0f6bcf | 186 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
0f8c9768 | 187 | |
6d0f6bcf | 188 | #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ |
0f8c9768 WD |
189 | |
190 | /* | |
191 | * For booting Linux, the board info and command line data | |
192 | * have to be in the first 8 MB of memory, since this is | |
193 | * the maximum mapped by the Linux kernel during initialization. | |
194 | */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
0f8c9768 WD |
196 | |
197 | /*----------------------------------------------------------------------- | |
198 | * Flash and Boot ROM mapping | |
199 | */ | |
efa329cb | 200 | #ifdef CONFIG_FLASH_32MB |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_FLASH0_BASE 0x40000000 |
202 | #define CONFIG_SYS_FLASH0_SIZE 0x02000000 | |
efa329cb | 203 | #else |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_FLASH0_BASE 0xFF000000 |
205 | #define CONFIG_SYS_FLASH0_SIZE 0x00800000 | |
efa329cb | 206 | #endif |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_BOOTROM_BASE 0xFF800000 |
208 | #define CONFIG_SYS_BOOTROM_SIZE 0x00080000 | |
209 | #define CONFIG_SYS_DOC_BASE 0xFF800000 | |
210 | #define CONFIG_SYS_DOC_SIZE 0x00100000 | |
0f8c9768 | 211 | |
0f8c9768 WD |
212 | /* Flash bank size (for preliminary settings) |
213 | */ | |
6d0f6bcf | 214 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE |
0f8c9768 WD |
215 | |
216 | /*----------------------------------------------------------------------- | |
217 | * FLASH organization | |
218 | */ | |
6d0f6bcf | 219 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
efa329cb | 220 | #ifdef CONFIG_FLASH_32MB |
6d0f6bcf | 221 | #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ |
efa329cb | 222 | #else |
6d0f6bcf | 223 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
efa329cb | 224 | #endif |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
226 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
0f8c9768 WD |
227 | |
228 | #if 0 | |
229 | /* Start port with environment in flash; switch to EEPROM later */ | |
5a1aceb0 | 230 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 231 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) |
0e8d1586 JCPV |
232 | #define CONFIG_ENV_SIZE 0x40000 |
233 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
0f8c9768 WD |
234 | #else |
235 | /* Final version: environment in EEPROM */ | |
bb1f8b4f | 236 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 |
238 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
239 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
240 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
0e8d1586 JCPV |
241 | #define CONFIG_ENV_OFFSET 512 |
242 | #define CONFIG_ENV_SIZE (2048 - 512) | |
0f8c9768 WD |
243 | #endif |
244 | ||
245 | /*----------------------------------------------------------------------- | |
246 | * Hard Reset Configuration Words | |
247 | * | |
6d0f6bcf | 248 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
0f8c9768 | 249 | * defines for the various registers affected by the HRCW e.g. changing |
6d0f6bcf | 250 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
0f8c9768 WD |
251 | */ |
252 | #if defined(CONFIG_BOOT_ROM) | |
6d0f6bcf | 253 | #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) |
0f8c9768 | 254 | #else |
6d0f6bcf | 255 | #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) |
0f8c9768 WD |
256 | #endif |
257 | ||
258 | /* no slaves so just fill with zeros */ | |
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
260 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
261 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
262 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
263 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
264 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
265 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
0f8c9768 WD |
266 | |
267 | /*----------------------------------------------------------------------- | |
268 | * Internal Memory Mapped Register | |
269 | */ | |
6d0f6bcf | 270 | #define CONFIG_SYS_IMMR 0xF0000000 |
0f8c9768 WD |
271 | |
272 | /*----------------------------------------------------------------------- | |
273 | * Definitions for initial stack pointer and data area (in DPRAM) | |
274 | */ | |
6d0f6bcf | 275 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 276 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
25ddd1fb | 277 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 278 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
0f8c9768 WD |
279 | |
280 | /*----------------------------------------------------------------------- | |
281 | * Start addresses for the final memory configuration | |
282 | * (Set up by the startup code) | |
6d0f6bcf | 283 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
0f8c9768 | 284 | * |
6d0f6bcf | 285 | * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM |
0f8c9768 WD |
286 | * is mapped at SDRAM_BASE2_PRELIM. |
287 | */ | |
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
289 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE | |
14d0a02a | 290 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
292 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
0f8c9768 | 293 | |
6d0f6bcf JCPV |
294 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
295 | # define CONFIG_SYS_RAMBOOT | |
0f8c9768 WD |
296 | #endif |
297 | ||
10f67017 | 298 | #ifdef CONFIG_PCI |
4d75a504 WD |
299 | #define CONFIG_PCI_PNP |
300 | #define CONFIG_EEPRO100 | |
6d0f6bcf | 301 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
10f67017 | 302 | #endif |
4d75a504 | 303 | |
0f8c9768 WD |
304 | /*----------------------------------------------------------------------- |
305 | * Cache Configuration | |
306 | */ | |
6d0f6bcf | 307 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
acf02697 | 308 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 309 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
0f8c9768 WD |
310 | #endif |
311 | ||
312 | /*----------------------------------------------------------------------- | |
313 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
314 | *----------------------------------------------------------------------- | |
315 | * HID0 also contains cache control - initially enable both caches and | |
316 | * invalidate contents, then the final state leaves only the instruction | |
317 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
318 | * but Soft reset does not. | |
319 | * | |
320 | * HID1 has only read-only information - nothing to set. | |
321 | */ | |
6d0f6bcf | 322 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
8bde7f77 | 323 | HID0_IFEM|HID0_ABE) |
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) |
325 | #define CONFIG_SYS_HID2 0 | |
0f8c9768 WD |
326 | |
327 | /*----------------------------------------------------------------------- | |
328 | * RMR - Reset Mode Register 5-5 | |
329 | *----------------------------------------------------------------------- | |
330 | * turn on Checkstop Reset Enable | |
331 | */ | |
6d0f6bcf | 332 | #define CONFIG_SYS_RMR RMR_CSRE |
0f8c9768 WD |
333 | |
334 | /*----------------------------------------------------------------------- | |
335 | * BCR - Bus Configuration 4-25 | |
336 | *----------------------------------------------------------------------- | |
337 | */ | |
338 | ||
339 | #define BCR_APD01 0x10000000 | |
6d0f6bcf | 340 | #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
0f8c9768 WD |
341 | |
342 | /*----------------------------------------------------------------------- | |
343 | * SIUMCR - SIU Module Configuration 4-31 | |
344 | *----------------------------------------------------------------------- | |
345 | */ | |
346 | #if 0 | |
6d0f6bcf | 347 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) |
0f8c9768 | 348 | #else |
6d0f6bcf | 349 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) |
0f8c9768 WD |
350 | #endif |
351 | ||
352 | ||
353 | /*----------------------------------------------------------------------- | |
354 | * SYPCR - System Protection Control 4-35 | |
355 | * SYPCR can only be written once after reset! | |
356 | *----------------------------------------------------------------------- | |
357 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
358 | */ | |
359 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 360 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
8bde7f77 | 361 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
0f8c9768 | 362 | #else |
6d0f6bcf | 363 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
8bde7f77 | 364 | SYPCR_SWRI|SYPCR_SWP) |
0f8c9768 WD |
365 | #endif /* CONFIG_WATCHDOG */ |
366 | ||
367 | /*----------------------------------------------------------------------- | |
368 | * TMCNTSC - Time Counter Status and Control 4-40 | |
369 | *----------------------------------------------------------------------- | |
370 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
371 | * and enable Time Counter | |
372 | */ | |
6d0f6bcf | 373 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
0f8c9768 WD |
374 | |
375 | /*----------------------------------------------------------------------- | |
376 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
377 | *----------------------------------------------------------------------- | |
378 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
379 | * Periodic timer | |
380 | */ | |
6d0f6bcf | 381 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
0f8c9768 WD |
382 | |
383 | /*----------------------------------------------------------------------- | |
384 | * SCCR - System Clock Control 9-8 | |
385 | *----------------------------------------------------------------------- | |
386 | */ | |
6d0f6bcf | 387 | #define CONFIG_SYS_SCCR (SCCR_DFBRG00) |
0f8c9768 WD |
388 | |
389 | /*----------------------------------------------------------------------- | |
390 | * RCCR - RISC Controller Configuration 13-7 | |
391 | *----------------------------------------------------------------------- | |
392 | */ | |
6d0f6bcf | 393 | #define CONFIG_SYS_RCCR 0 |
0f8c9768 WD |
394 | |
395 | /* | |
396 | * Init Memory Controller: | |
397 | * | |
398 | * Bank Bus Machine PortSz Device | |
399 | * ---- --- ------- ------ ------ | |
400 | * 0 60x GPCM 64 bit FLASH | |
401 | * 1 60x SDRAM 64 bit SDRAM | |
0f8c9768 WD |
402 | * |
403 | */ | |
404 | ||
405 | /* Initialize SDRAM on local bus | |
406 | */ | |
6d0f6bcf | 407 | #define CONFIG_SYS_INIT_LOCAL_SDRAM |
0f8c9768 WD |
408 | |
409 | ||
410 | /* Minimum mask to separate preliminary | |
411 | * address ranges for CS[0:2] | |
412 | */ | |
6d0f6bcf | 413 | #define CONFIG_SYS_MIN_AM_MASK 0xC0000000 |
0f8c9768 | 414 | |
efa329cb WD |
415 | /* |
416 | * we use the same values for 32 MB and 128 MB SDRAM | |
417 | * refresh rate = 7.73 uS (64 MHz Bus Clock) | |
418 | */ | |
6d0f6bcf JCPV |
419 | #define CONFIG_SYS_MPTPR 0x2000 |
420 | #define CONFIG_SYS_PSRT 0x0E | |
0f8c9768 | 421 | |
6d0f6bcf | 422 | #define CONFIG_SYS_MRS_OFFS 0x00000000 |
0f8c9768 WD |
423 | |
424 | ||
425 | #if defined(CONFIG_BOOT_ROM) | |
426 | /* | |
427 | * Bank 0 - Boot ROM (8 bit wide) | |
428 | */ | |
6d0f6bcf | 429 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ |
0f8c9768 WD |
430 | BRx_PS_8 |\ |
431 | BRx_MS_GPCM_P |\ | |
432 | BRx_V) | |
433 | ||
6d0f6bcf | 434 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ |
0f8c9768 WD |
435 | ORxG_CSNT |\ |
436 | ORxG_ACS_DIV1 |\ | |
437 | ORxG_SCY_3_CLK |\ | |
438 | ORxG_EHTR |\ | |
439 | ORxG_TRLX) | |
440 | ||
441 | /* | |
442 | * Bank 1 - Flash (64 bit wide) | |
443 | */ | |
6d0f6bcf | 444 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
0f8c9768 WD |
445 | BRx_PS_64 |\ |
446 | BRx_MS_GPCM_P |\ | |
447 | BRx_V) | |
448 | ||
6d0f6bcf | 449 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
0f8c9768 WD |
450 | ORxG_CSNT |\ |
451 | ORxG_ACS_DIV1 |\ | |
452 | ORxG_SCY_3_CLK |\ | |
453 | ORxG_EHTR |\ | |
454 | ORxG_TRLX) | |
455 | ||
456 | #else /* ! CONFIG_BOOT_ROM */ | |
457 | ||
458 | /* | |
459 | * Bank 0 - Flash (64 bit wide) | |
460 | */ | |
6d0f6bcf | 461 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
462 | BRx_PS_64 |\ |
463 | BRx_MS_GPCM_P |\ | |
464 | BRx_V) | |
0f8c9768 | 465 | |
6d0f6bcf | 466 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
8bde7f77 WD |
467 | ORxG_CSNT |\ |
468 | ORxG_ACS_DIV1 |\ | |
469 | ORxG_SCY_3_CLK |\ | |
470 | ORxG_EHTR |\ | |
471 | ORxG_TRLX) | |
0f8c9768 WD |
472 | |
473 | /* | |
474 | * Bank 1 - Disk-On-Chip | |
475 | */ | |
6d0f6bcf | 476 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ |
0f8c9768 WD |
477 | BRx_PS_8 |\ |
478 | BRx_MS_GPCM_P |\ | |
479 | BRx_V) | |
480 | ||
6d0f6bcf | 481 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ |
0f8c9768 WD |
482 | ORxG_CSNT |\ |
483 | ORxG_ACS_DIV1 |\ | |
484 | ORxG_SCY_3_CLK |\ | |
485 | ORxG_EHTR |\ | |
486 | ORxG_TRLX) | |
487 | ||
488 | #endif /* CONFIG_BOOT_ROM */ | |
489 | ||
490 | /* Bank 2 - SDRAM | |
491 | */ | |
efa329cb | 492 | |
6d0f6bcf JCPV |
493 | #ifndef CONFIG_SYS_RAMBOOT |
494 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ | |
8bde7f77 WD |
495 | BRx_PS_64 |\ |
496 | BRx_MS_SDRAM_P |\ | |
497 | BRx_V) | |
0f8c9768 WD |
498 | |
499 | /* SDRAM initialization values for 8-column chips | |
500 | */ | |
6d0f6bcf | 501 | #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ |
8bde7f77 WD |
502 | ORxS_BPD_4 |\ |
503 | ORxS_ROWST_PBI0_A9 |\ | |
504 | ORxS_NUMR_12) | |
0f8c9768 | 505 | |
6d0f6bcf | 506 | #define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ |
8bde7f77 WD |
507 | PSDMR_BSMA_A14_A16 |\ |
508 | PSDMR_SDA10_PBI0_A10 |\ | |
509 | PSDMR_RFRC_7_CLK |\ | |
510 | PSDMR_PRETOACT_2W |\ | |
511 | PSDMR_ACTTORW_1W |\ | |
512 | PSDMR_LDOTOPRE_1C |\ | |
513 | PSDMR_WRC_1C |\ | |
514 | PSDMR_CL_2) | |
0f8c9768 WD |
515 | |
516 | /* SDRAM initialization values for 9-column chips | |
517 | */ | |
6d0f6bcf | 518 | #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ |
8bde7f77 WD |
519 | ORxS_BPD_4 |\ |
520 | ORxS_ROWST_PBI0_A7 |\ | |
521 | ORxS_NUMR_13) | |
0f8c9768 | 522 | |
6d0f6bcf | 523 | #define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ |
8bde7f77 WD |
524 | PSDMR_BSMA_A13_A15 |\ |
525 | PSDMR_SDA10_PBI0_A9 |\ | |
526 | PSDMR_RFRC_7_CLK |\ | |
527 | PSDMR_PRETOACT_2W |\ | |
528 | PSDMR_ACTTORW_1W |\ | |
529 | PSDMR_LDOTOPRE_1C |\ | |
530 | PSDMR_WRC_1C |\ | |
531 | PSDMR_CL_2) | |
0f8c9768 | 532 | |
6d0f6bcf JCPV |
533 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL |
534 | #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL | |
0f8c9768 | 535 | |
6d0f6bcf | 536 | #endif /* CONFIG_SYS_RAMBOOT */ |
0f8c9768 WD |
537 | |
538 | #endif /* __CONFIG_H */ |