projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0f8c9768 | 1 | /* |
| 414eec35 | 2 | * (C) Copyright 2001-2005 |
| 0f8c9768 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 6d0f6bcf | 31 | #undef CONFIG_SYS_RAMBOOT |
| 0f8c9768 WD |
32 | |
| 33 | /* | |
| 34 | * High Level Configuration Options | |
| 35 | * (easy to change) | |
| 36 | */ | |
| 37 | ||
| 38 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ | |
| 39 | #define CONFIG_PM826 1 /* ...on a PM8260 module */ | |
| 9c4c5ae3 | 40 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
| 0f8c9768 | 41 | |
| aacf9a49 WD |
42 | #undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ |
| 43 | ||
| 0f8c9768 WD |
44 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 45 | ||
| 32bf3d14 | 46 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
| 0f8c9768 WD |
47 | |
| 48 | #undef CONFIG_BOOTARGS | |
| 49 | #define CONFIG_BOOTCOMMAND \ | |
| 53677ef1 WD |
50 | "bootp; " \ |
| 51 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
| 52 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
| 0f8c9768 WD |
53 | "bootm" |
| 54 | ||
| 55 | /* enable I2C and select the hardware/software driver */ | |
| 56 | #undef CONFIG_HARD_I2C | |
| 57 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
| 6d0f6bcf JCPV |
58 | # define CONFIG_SYS_I2C_SPEED 50000 |
| 59 | # define CONFIG_SYS_I2C_SLAVE 0xFE | |
| 0f8c9768 WD |
60 | /* |
| 61 | * Software (bit-bang) I2C driver configuration | |
| 62 | */ | |
| 63 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
| 64 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
| 65 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
| 66 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
| 67 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
| 68 | else iop->pdat &= ~0x00010000 | |
| 69 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
| 70 | else iop->pdat &= ~0x00020000 | |
| 71 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
| 72 | ||
| 73 | ||
| 74 | #define CONFIG_RTC_PCF8563 | |
| 6d0f6bcf | 75 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
| 0f8c9768 WD |
76 | |
| 77 | /* | |
| 78 | * select serial console configuration | |
| 79 | * | |
| 80 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
| 81 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
| 82 | * for SCC). | |
| 83 | * | |
| 84 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
| 85 | * defined elsewhere (for example, on the cogent platform, there are serial | |
| 86 | * ports on the motherboard which are used for the serial console - see | |
| 87 | * cogent/cma101/serial.[ch]). | |
| 88 | */ | |
| 89 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
| 90 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
| 91 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
| 92 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
| 93 | ||
| 94 | /* | |
| 95 | * select ethernet configuration | |
| 96 | * | |
| aacf9a49 WD |
97 | * if CONFIG_ETHER_ON_SCC is selected, then |
| 98 | * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) | |
| 99 | * - CONFIG_NET_MULTI must not be defined | |
| 100 | * | |
| 101 | * if CONFIG_ETHER_ON_FCC is selected, then | |
| 102 | * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected | |
| 103 | * - CONFIG_NET_MULTI must be defined | |
| 0f8c9768 WD |
104 | * |
| 105 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
| 639221c7 | 106 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
| 0f8c9768 | 107 | */ |
| aacf9a49 | 108 | #define CONFIG_NET_MULTI |
| 0f8c9768 | 109 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
| 0f8c9768 | 110 | |
| aacf9a49 WD |
111 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
| 112 | #define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ | |
| 113 | ||
| 114 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
| 0f8c9768 WD |
115 | /* |
| 116 | * - Rx-CLK is CLK11 | |
| 117 | * - Tx-CLK is CLK10 | |
| aacf9a49 WD |
118 | */ |
| 119 | #define CONFIG_ETHER_ON_FCC1 | |
| 6d0f6bcf | 120 | # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
| aacf9a49 | 121 | #ifndef CONFIG_DB_CR826_J30x_ON |
| 6d0f6bcf | 122 | # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) |
| aacf9a49 | 123 | #else |
| 6d0f6bcf | 124 | # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) |
| aacf9a49 WD |
125 | #endif |
| 126 | /* | |
| 127 | * - Rx-CLK is CLK15 | |
| 128 | * - Tx-CLK is CLK14 | |
| 129 | */ | |
| 130 | #define CONFIG_ETHER_ON_FCC2 | |
| 6d0f6bcf JCPV |
131 | # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
| 132 | # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
| aacf9a49 | 133 | /* |
| 0f8c9768 WD |
134 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
| 135 | * - Enable Full Duplex in FSMR | |
| 136 | */ | |
| 6d0f6bcf JCPV |
137 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
| 138 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
| 0f8c9768 | 139 | |
| 0f8c9768 WD |
140 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
| 141 | #define CONFIG_8260_CLKIN 64000000 /* in Hz */ | |
| 142 | ||
| 143 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) | |
| 144 | #define CONFIG_BAUDRATE 230400 | |
| 145 | #else | |
| 146 | #define CONFIG_BAUDRATE 9600 | |
| 147 | #endif | |
| 148 | ||
| 149 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 150 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| 0f8c9768 WD |
151 | |
| 152 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 153 | ||
| 18225e8d JL |
154 | /* |
| 155 | * BOOTP options | |
| 156 | */ | |
| 157 | #define CONFIG_BOOTP_SUBNETMASK | |
| 158 | #define CONFIG_BOOTP_GATEWAY | |
| 159 | #define CONFIG_BOOTP_HOSTNAME | |
| 160 | #define CONFIG_BOOTP_BOOTPATH | |
| 161 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 0f8c9768 | 162 | |
| acf02697 JL |
163 | |
| 164 | /* | |
| 165 | * Command line configuration. | |
| 166 | */ | |
| 167 | #include <config_cmd_default.h> | |
| 168 | ||
| 169 | #define CONFIG_CMD_BEDBUG | |
| 170 | #define CONFIG_CMD_DATE | |
| 171 | #define CONFIG_CMD_DHCP | |
| 172 | #define CONFIG_CMD_DOC | |
| 173 | #define CONFIG_CMD_EEPROM | |
| 174 | #define CONFIG_CMD_I2C | |
| 175 | #define CONFIG_CMD_NFS | |
| 176 | #define CONFIG_CMD_SNTP | |
| 177 | ||
| 5d232d0e | 178 | #ifdef CONFIG_PCI |
| acf02697 JL |
179 | #define CONFIG_CMD_PCI |
| 180 | #endif | |
| 181 | ||
| 0f8c9768 | 182 | |
| cc4a0cee | 183 | #define CONFIG_NAND_LEGACY |
| addb2e16 | 184 | |
| 0f8c9768 WD |
185 | /* |
| 186 | * Disk-On-Chip configuration | |
| 187 | */ | |
| 188 | ||
| 6d0f6bcf JCPV |
189 | #define CONFIG_SYS_DOC_SHORT_TIMEOUT |
| 190 | #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ | |
| 0f8c9768 | 191 | |
| 6d0f6bcf JCPV |
192 | #define CONFIG_SYS_DOC_SUPPORT_2000 |
| 193 | #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM | |
| 0f8c9768 WD |
194 | |
| 195 | /* | |
| 196 | * Miscellaneous configurable options | |
| 197 | */ | |
| 6d0f6bcf JCPV |
198 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 199 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| acf02697 | 200 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 201 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 0f8c9768 | 202 | #else |
| 6d0f6bcf | 203 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 0f8c9768 | 204 | #endif |
| 6d0f6bcf JCPV |
205 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 206 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 207 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 0f8c9768 | 208 | |
| 6d0f6bcf JCPV |
209 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 210 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 0f8c9768 | 211 | |
| 6d0f6bcf | 212 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 0f8c9768 | 213 | |
| 6d0f6bcf | 214 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 0f8c9768 | 215 | |
| 6d0f6bcf | 216 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 0f8c9768 | 217 | |
| 6d0f6bcf | 218 | #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ |
| 0f8c9768 WD |
219 | |
| 220 | /* | |
| 221 | * For booting Linux, the board info and command line data | |
| 222 | * have to be in the first 8 MB of memory, since this is | |
| 223 | * the maximum mapped by the Linux kernel during initialization. | |
| 224 | */ | |
| 6d0f6bcf | 225 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 0f8c9768 WD |
226 | |
| 227 | /*----------------------------------------------------------------------- | |
| 228 | * Flash and Boot ROM mapping | |
| 229 | */ | |
| efa329cb | 230 | #ifdef CONFIG_FLASH_32MB |
| 6d0f6bcf JCPV |
231 | #define CONFIG_SYS_FLASH0_BASE 0x40000000 |
| 232 | #define CONFIG_SYS_FLASH0_SIZE 0x02000000 | |
| efa329cb | 233 | #else |
| 6d0f6bcf JCPV |
234 | #define CONFIG_SYS_FLASH0_BASE 0xFF000000 |
| 235 | #define CONFIG_SYS_FLASH0_SIZE 0x00800000 | |
| efa329cb | 236 | #endif |
| 6d0f6bcf JCPV |
237 | #define CONFIG_SYS_BOOTROM_BASE 0xFF800000 |
| 238 | #define CONFIG_SYS_BOOTROM_SIZE 0x00080000 | |
| 239 | #define CONFIG_SYS_DOC_BASE 0xFF800000 | |
| 240 | #define CONFIG_SYS_DOC_SIZE 0x00100000 | |
| 0f8c9768 | 241 | |
| 0f8c9768 WD |
242 | /* Flash bank size (for preliminary settings) |
| 243 | */ | |
| 6d0f6bcf | 244 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE |
| 0f8c9768 WD |
245 | |
| 246 | /*----------------------------------------------------------------------- | |
| 247 | * FLASH organization | |
| 248 | */ | |
| 6d0f6bcf | 249 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
| efa329cb | 250 | #ifdef CONFIG_FLASH_32MB |
| 6d0f6bcf | 251 | #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ |
| efa329cb | 252 | #else |
| 6d0f6bcf | 253 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
| efa329cb | 254 | #endif |
| 6d0f6bcf JCPV |
255 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
| 256 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
| 0f8c9768 WD |
257 | |
| 258 | #if 0 | |
| 259 | /* Start port with environment in flash; switch to EEPROM later */ | |
| 5a1aceb0 | 260 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 261 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) |
| 0e8d1586 JCPV |
262 | #define CONFIG_ENV_SIZE 0x40000 |
| 263 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
| 0f8c9768 WD |
264 | #else |
| 265 | /* Final version: environment in EEPROM */ | |
| bb1f8b4f | 266 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
| 6d0f6bcf JCPV |
267 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 |
| 268 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 269 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
| 270 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
| 0e8d1586 JCPV |
271 | #define CONFIG_ENV_OFFSET 512 |
| 272 | #define CONFIG_ENV_SIZE (2048 - 512) | |
| 0f8c9768 WD |
273 | #endif |
| 274 | ||
| 275 | /*----------------------------------------------------------------------- | |
| 276 | * Hard Reset Configuration Words | |
| 277 | * | |
| 6d0f6bcf | 278 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
| 0f8c9768 | 279 | * defines for the various registers affected by the HRCW e.g. changing |
| 6d0f6bcf | 280 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
| 0f8c9768 WD |
281 | */ |
| 282 | #if defined(CONFIG_BOOT_ROM) | |
| 6d0f6bcf | 283 | #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) |
| 0f8c9768 | 284 | #else |
| 6d0f6bcf | 285 | #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) |
| 0f8c9768 WD |
286 | #endif |
| 287 | ||
| 288 | /* no slaves so just fill with zeros */ | |
| 6d0f6bcf JCPV |
289 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
| 290 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
| 291 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
| 292 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
| 293 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
| 294 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
| 295 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
| 0f8c9768 WD |
296 | |
| 297 | /*----------------------------------------------------------------------- | |
| 298 | * Internal Memory Mapped Register | |
| 299 | */ | |
| 6d0f6bcf | 300 | #define CONFIG_SYS_IMMR 0xF0000000 |
| 0f8c9768 WD |
301 | |
| 302 | /*----------------------------------------------------------------------- | |
| 303 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 304 | */ | |
| 6d0f6bcf JCPV |
305 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 306 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
| 307 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
| 308 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 309 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 0f8c9768 WD |
310 | |
| 311 | /*----------------------------------------------------------------------- | |
| 312 | * Start addresses for the final memory configuration | |
| 313 | * (Set up by the startup code) | |
| 6d0f6bcf | 314 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 0f8c9768 | 315 | * |
| 6d0f6bcf | 316 | * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM |
| 0f8c9768 WD |
317 | * is mapped at SDRAM_BASE2_PRELIM. |
| 318 | */ | |
| 6d0f6bcf JCPV |
319 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 320 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE | |
| 321 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
| 322 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 323 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
| 0f8c9768 | 324 | |
| 6d0f6bcf JCPV |
325 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 326 | # define CONFIG_SYS_RAMBOOT | |
| 0f8c9768 WD |
327 | #endif |
| 328 | ||
| 10f67017 | 329 | #ifdef CONFIG_PCI |
| 4d75a504 WD |
330 | #define CONFIG_PCI_PNP |
| 331 | #define CONFIG_EEPRO100 | |
| 6d0f6bcf | 332 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
| 10f67017 | 333 | #endif |
| 4d75a504 | 334 | |
| 0f8c9768 WD |
335 | /* |
| 336 | * Internal Definitions | |
| 337 | * | |
| 338 | * Boot Flags | |
| 339 | */ | |
| 340 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
| 341 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 342 | ||
| 343 | ||
| 344 | /*----------------------------------------------------------------------- | |
| 345 | * Cache Configuration | |
| 346 | */ | |
| 6d0f6bcf | 347 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
| acf02697 | 348 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 349 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 0f8c9768 WD |
350 | #endif |
| 351 | ||
| 352 | /*----------------------------------------------------------------------- | |
| 353 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
| 354 | *----------------------------------------------------------------------- | |
| 355 | * HID0 also contains cache control - initially enable both caches and | |
| 356 | * invalidate contents, then the final state leaves only the instruction | |
| 357 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
| 358 | * but Soft reset does not. | |
| 359 | * | |
| 360 | * HID1 has only read-only information - nothing to set. | |
| 361 | */ | |
| 6d0f6bcf | 362 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
| 8bde7f77 | 363 | HID0_IFEM|HID0_ABE) |
| 6d0f6bcf JCPV |
364 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) |
| 365 | #define CONFIG_SYS_HID2 0 | |
| 0f8c9768 WD |
366 | |
| 367 | /*----------------------------------------------------------------------- | |
| 368 | * RMR - Reset Mode Register 5-5 | |
| 369 | *----------------------------------------------------------------------- | |
| 370 | * turn on Checkstop Reset Enable | |
| 371 | */ | |
| 6d0f6bcf | 372 | #define CONFIG_SYS_RMR RMR_CSRE |
| 0f8c9768 WD |
373 | |
| 374 | /*----------------------------------------------------------------------- | |
| 375 | * BCR - Bus Configuration 4-25 | |
| 376 | *----------------------------------------------------------------------- | |
| 377 | */ | |
| 378 | ||
| 379 | #define BCR_APD01 0x10000000 | |
| 6d0f6bcf | 380 | #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
| 0f8c9768 WD |
381 | |
| 382 | /*----------------------------------------------------------------------- | |
| 383 | * SIUMCR - SIU Module Configuration 4-31 | |
| 384 | *----------------------------------------------------------------------- | |
| 385 | */ | |
| 386 | #if 0 | |
| 6d0f6bcf | 387 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) |
| 0f8c9768 | 388 | #else |
| 6d0f6bcf | 389 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) |
| 0f8c9768 WD |
390 | #endif |
| 391 | ||
| 392 | ||
| 393 | /*----------------------------------------------------------------------- | |
| 394 | * SYPCR - System Protection Control 4-35 | |
| 395 | * SYPCR can only be written once after reset! | |
| 396 | *----------------------------------------------------------------------- | |
| 397 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
| 398 | */ | |
| 399 | #if defined(CONFIG_WATCHDOG) | |
| 6d0f6bcf | 400 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
| 8bde7f77 | 401 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
| 0f8c9768 | 402 | #else |
| 6d0f6bcf | 403 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
| 8bde7f77 | 404 | SYPCR_SWRI|SYPCR_SWP) |
| 0f8c9768 WD |
405 | #endif /* CONFIG_WATCHDOG */ |
| 406 | ||
| 407 | /*----------------------------------------------------------------------- | |
| 408 | * TMCNTSC - Time Counter Status and Control 4-40 | |
| 409 | *----------------------------------------------------------------------- | |
| 410 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
| 411 | * and enable Time Counter | |
| 412 | */ | |
| 6d0f6bcf | 413 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
| 0f8c9768 WD |
414 | |
| 415 | /*----------------------------------------------------------------------- | |
| 416 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
| 417 | *----------------------------------------------------------------------- | |
| 418 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
| 419 | * Periodic timer | |
| 420 | */ | |
| 6d0f6bcf | 421 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
| 0f8c9768 WD |
422 | |
| 423 | /*----------------------------------------------------------------------- | |
| 424 | * SCCR - System Clock Control 9-8 | |
| 425 | *----------------------------------------------------------------------- | |
| 426 | */ | |
| 6d0f6bcf | 427 | #define CONFIG_SYS_SCCR (SCCR_DFBRG00) |
| 0f8c9768 WD |
428 | |
| 429 | /*----------------------------------------------------------------------- | |
| 430 | * RCCR - RISC Controller Configuration 13-7 | |
| 431 | *----------------------------------------------------------------------- | |
| 432 | */ | |
| 6d0f6bcf | 433 | #define CONFIG_SYS_RCCR 0 |
| 0f8c9768 WD |
434 | |
| 435 | /* | |
| 436 | * Init Memory Controller: | |
| 437 | * | |
| 438 | * Bank Bus Machine PortSz Device | |
| 439 | * ---- --- ------- ------ ------ | |
| 440 | * 0 60x GPCM 64 bit FLASH | |
| 441 | * 1 60x SDRAM 64 bit SDRAM | |
| 0f8c9768 WD |
442 | * |
| 443 | */ | |
| 444 | ||
| 445 | /* Initialize SDRAM on local bus | |
| 446 | */ | |
| 6d0f6bcf | 447 | #define CONFIG_SYS_INIT_LOCAL_SDRAM |
| 0f8c9768 WD |
448 | |
| 449 | ||
| 450 | /* Minimum mask to separate preliminary | |
| 451 | * address ranges for CS[0:2] | |
| 452 | */ | |
| 6d0f6bcf | 453 | #define CONFIG_SYS_MIN_AM_MASK 0xC0000000 |
| 0f8c9768 | 454 | |
| efa329cb WD |
455 | /* |
| 456 | * we use the same values for 32 MB and 128 MB SDRAM | |
| 457 | * refresh rate = 7.73 uS (64 MHz Bus Clock) | |
| 458 | */ | |
| 6d0f6bcf JCPV |
459 | #define CONFIG_SYS_MPTPR 0x2000 |
| 460 | #define CONFIG_SYS_PSRT 0x0E | |
| 0f8c9768 | 461 | |
| 6d0f6bcf | 462 | #define CONFIG_SYS_MRS_OFFS 0x00000000 |
| 0f8c9768 WD |
463 | |
| 464 | ||
| 465 | #if defined(CONFIG_BOOT_ROM) | |
| 466 | /* | |
| 467 | * Bank 0 - Boot ROM (8 bit wide) | |
| 468 | */ | |
| 6d0f6bcf | 469 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ |
| 0f8c9768 WD |
470 | BRx_PS_8 |\ |
| 471 | BRx_MS_GPCM_P |\ | |
| 472 | BRx_V) | |
| 473 | ||
| 6d0f6bcf | 474 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ |
| 0f8c9768 WD |
475 | ORxG_CSNT |\ |
| 476 | ORxG_ACS_DIV1 |\ | |
| 477 | ORxG_SCY_3_CLK |\ | |
| 478 | ORxG_EHTR |\ | |
| 479 | ORxG_TRLX) | |
| 480 | ||
| 481 | /* | |
| 482 | * Bank 1 - Flash (64 bit wide) | |
| 483 | */ | |
| 6d0f6bcf | 484 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
| 0f8c9768 WD |
485 | BRx_PS_64 |\ |
| 486 | BRx_MS_GPCM_P |\ | |
| 487 | BRx_V) | |
| 488 | ||
| 6d0f6bcf | 489 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
| 0f8c9768 WD |
490 | ORxG_CSNT |\ |
| 491 | ORxG_ACS_DIV1 |\ | |
| 492 | ORxG_SCY_3_CLK |\ | |
| 493 | ORxG_EHTR |\ | |
| 494 | ORxG_TRLX) | |
| 495 | ||
| 496 | #else /* ! CONFIG_BOOT_ROM */ | |
| 497 | ||
| 498 | /* | |
| 499 | * Bank 0 - Flash (64 bit wide) | |
| 500 | */ | |
| 6d0f6bcf | 501 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
| 8bde7f77 WD |
502 | BRx_PS_64 |\ |
| 503 | BRx_MS_GPCM_P |\ | |
| 504 | BRx_V) | |
| 0f8c9768 | 505 | |
| 6d0f6bcf | 506 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
| 8bde7f77 WD |
507 | ORxG_CSNT |\ |
| 508 | ORxG_ACS_DIV1 |\ | |
| 509 | ORxG_SCY_3_CLK |\ | |
| 510 | ORxG_EHTR |\ | |
| 511 | ORxG_TRLX) | |
| 0f8c9768 WD |
512 | |
| 513 | /* | |
| 514 | * Bank 1 - Disk-On-Chip | |
| 515 | */ | |
| 6d0f6bcf | 516 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ |
| 0f8c9768 WD |
517 | BRx_PS_8 |\ |
| 518 | BRx_MS_GPCM_P |\ | |
| 519 | BRx_V) | |
| 520 | ||
| 6d0f6bcf | 521 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ |
| 0f8c9768 WD |
522 | ORxG_CSNT |\ |
| 523 | ORxG_ACS_DIV1 |\ | |
| 524 | ORxG_SCY_3_CLK |\ | |
| 525 | ORxG_EHTR |\ | |
| 526 | ORxG_TRLX) | |
| 527 | ||
| 528 | #endif /* CONFIG_BOOT_ROM */ | |
| 529 | ||
| 530 | /* Bank 2 - SDRAM | |
| 531 | */ | |
| efa329cb | 532 | |
| 6d0f6bcf JCPV |
533 | #ifndef CONFIG_SYS_RAMBOOT |
| 534 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ | |
| 8bde7f77 WD |
535 | BRx_PS_64 |\ |
| 536 | BRx_MS_SDRAM_P |\ | |
| 537 | BRx_V) | |
| 0f8c9768 WD |
538 | |
| 539 | /* SDRAM initialization values for 8-column chips | |
| 540 | */ | |
| 6d0f6bcf | 541 | #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ |
| 8bde7f77 WD |
542 | ORxS_BPD_4 |\ |
| 543 | ORxS_ROWST_PBI0_A9 |\ | |
| 544 | ORxS_NUMR_12) | |
| 0f8c9768 | 545 | |
| 6d0f6bcf | 546 | #define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ |
| 8bde7f77 WD |
547 | PSDMR_BSMA_A14_A16 |\ |
| 548 | PSDMR_SDA10_PBI0_A10 |\ | |
| 549 | PSDMR_RFRC_7_CLK |\ | |
| 550 | PSDMR_PRETOACT_2W |\ | |
| 551 | PSDMR_ACTTORW_1W |\ | |
| 552 | PSDMR_LDOTOPRE_1C |\ | |
| 553 | PSDMR_WRC_1C |\ | |
| 554 | PSDMR_CL_2) | |
| 0f8c9768 WD |
555 | |
| 556 | /* SDRAM initialization values for 9-column chips | |
| 557 | */ | |
| 6d0f6bcf | 558 | #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ |
| 8bde7f77 WD |
559 | ORxS_BPD_4 |\ |
| 560 | ORxS_ROWST_PBI0_A7 |\ | |
| 561 | ORxS_NUMR_13) | |
| 0f8c9768 | 562 | |
| 6d0f6bcf | 563 | #define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ |
| 8bde7f77 WD |
564 | PSDMR_BSMA_A13_A15 |\ |
| 565 | PSDMR_SDA10_PBI0_A9 |\ | |
| 566 | PSDMR_RFRC_7_CLK |\ | |
| 567 | PSDMR_PRETOACT_2W |\ | |
| 568 | PSDMR_ACTTORW_1W |\ | |
| 569 | PSDMR_LDOTOPRE_1C |\ | |
| 570 | PSDMR_WRC_1C |\ | |
| 571 | PSDMR_CL_2) | |
| 0f8c9768 | 572 | |
| 6d0f6bcf JCPV |
573 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL |
| 574 | #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL | |
| 0f8c9768 | 575 | |
| 6d0f6bcf | 576 | #endif /* CONFIG_SYS_RAMBOOT */ |
| 0f8c9768 WD |
577 | |
| 578 | #endif /* __CONFIG_H */ |