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rename CFG_ macros to CONFIG_SYS
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1/*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * MicroSys PM856 board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
38#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41#define CONFIG_MPC8560 1 /* MPC8560 specific */
452e8e72 42#define CONFIG_CPM2 1 /* Has a CPM2 */
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43#define CONFIG_PM856 1 /* PM856 board specific */
44
45#define CONFIG_PCI
53677ef1 46#define CONFIG_TSEC_ENET /* tsec ethernet support */
b20d0032 47#define CONFIG_ENV_OVERWRITE
b20d0032 48
45f2166a 49#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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50
51/*
52 * sysclk for MPC85xx
53 *
54 * Two valid values are:
55 * 33000000
56 * 66000000
57 *
58 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
59 * is likely the desired value here, so that is now the default.
60 * The board, however, can run at 66MHz. In any event, this value
61 * must match the settings of some switches. Details can be found
62 * in the README.mpc85xxads.
63 */
64
65#ifndef CONFIG_SYS_CLK_FREQ
66#define CONFIG_SYS_CLK_FREQ 66000000
67#endif
68
69
70/*
71 * These can be toggled for performance analysis, otherwise use default.
72 */
73#define CONFIG_L2_CACHE /* toggle L2 cache */
74#define CONFIG_BTB /* toggle branch predition */
75#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
76
77#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
78
6d0f6bcf 79#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
b20d0032 80
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81#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
82#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
83#define CONFIG_SYS_MEMTEST_END 0x00400000
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84
85
86/*
87 * Base addresses -- Note these are effective addresses where the
88 * actual resources get mapped (not physical addresses)
89 */
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90#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
91#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
92#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
93#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
b20d0032 94
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95/* DDR Setup */
96#define CONFIG_FSL_DDR1
97#undef CONFIG_FSL_DDR_INTERACTIVE
98#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
99#undef CONFIG_DDR_SPD
100#define CONFIG_DDR_DLL /* possible DLL fix needed */
101#define CONFIG_DDR_ECC /* only for ECC DDR module */
b20d0032 102
6bfa8f72 103#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
b20d0032 104
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105#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
106#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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107#define CONFIG_VERY_BIG_RAM
108
109#define CONFIG_NUM_DDR_CONTROLLERS 1
110#define CONFIG_DIMM_SLOTS_PER_CTLR 1
111#define CONFIG_CHIP_SELECTS_PER_CTRL 2
112
113/* I2C addresses of SPD EEPROMs */
114#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */
115
116/* Manually set up DDR parameters */
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117#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256 MB */
118#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
119#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
120#define CONFIG_SYS_DDR_TIMING_1 0x47444321
121#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
122#define CONFIG_SYS_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
123#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
124#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
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125
126/*
127 * SDRAM on the Local Bus
128 */
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129#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
130#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */
b20d0032 131
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132#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
133#define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */
b20d0032 134
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135#define CONFIG_SYS_OR0_PRELIM 0xfe006f67 /* 32MB Flash */
136#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
137#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
138#undef CONFIG_SYS_FLASH_CHECKSUM
139#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
140#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
b20d0032 141
6d0f6bcf 142#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
b20d0032 143
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144#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
145#define CONFIG_SYS_RAMBOOT
b20d0032 146#else
6d0f6bcf 147#undef CONFIG_SYS_RAMBOOT
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148#endif
149
00b1883a 150#define CONFIG_FLASH_CFI_DRIVER
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151#define CONFIG_SYS_FLASH_CFI
152#define CONFIG_SYS_FLASH_EMPTY_INFO
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153
154#undef CONFIG_CLOCKS_IN_MHZ
155
156
157/*
158 * Local Bus Definitions
159 */
160
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161#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
162#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
163#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
164#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
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165
166
167#define CONFIG_L1_INIT_RAM
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168#define CONFIG_SYS_INIT_RAM_LOCK 1
169#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
170#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
b20d0032 171
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172#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
173#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
174#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
b20d0032 175
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176#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
177#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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178
179/* Serial Port */
180#define CONFIG_CONS_ON_SCC /* define if console on SCC */
181#undef CONFIG_CONS_NONE /* define if console on something else */
182#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
183
6d0f6bcf 184#define CONFIG_SYS_BAUDRATE_TABLE \
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185 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
186
187/* Use the HUSH parser */
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188#define CONFIG_SYS_HUSH_PARSER
189#ifdef CONFIG_SYS_HUSH_PARSER
190#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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191#endif
192
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193/*
194 * I2C
195 */
196#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
197#define CONFIG_HARD_I2C /* I2C with hardware support*/
b20d0032 198#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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199#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
200#define CONFIG_SYS_I2C_SLAVE 0x7F
201#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
202#define CONFIG_SYS_I2C_OFFSET 0x3000
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203
204/*
205 * EEPROM configuration
206 */
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207#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
208#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
209#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
210#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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211
212/*
213 * RTC configuration
214 */
215#define CONFIG_RTC_PCF8563
6d0f6bcf 216#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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217
218/* RapidIO MMU */
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219#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
220#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
221#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
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222
223/*
224 * General PCI
225 * Addresses are mapped 1-1.
226 */
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227#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
228#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
229#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
230#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
231#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
232#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
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233
234#if defined(CONFIG_PCI)
235
236#define CONFIG_NET_MULTI
53677ef1 237#define CONFIG_PCI_PNP /* do pci plug-and-play */
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238
239#undef CONFIG_EEPRO100
240#undef CONFIG_TULIP
241
242#if !defined(CONFIG_PCI_PNP)
243 #define PCI_ENET0_IOADDR 0xe0000000
244 #define PCI_ENET0_MEMADDR 0xe0000000
53677ef1 245 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
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246#endif
247
248#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf 249#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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250
251#endif /* CONFIG_PCI */
252
253
254#if defined(CONFIG_TSEC_ENET)
255
256#ifndef CONFIG_NET_MULTI
53677ef1 257#define CONFIG_NET_MULTI 1
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258#endif
259
260#define CONFIG_MII 1 /* MII PHY management */
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261#define CONFIG_TSEC1 1
262#define CONFIG_TSEC1_NAME "TSEC0"
263#define CONFIG_TSEC2 1
264#define CONFIG_TSEC2_NAME "TSEC1"
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265#define TSEC1_PHY_ADDR 0
266#define TSEC2_PHY_ADDR 1
267#define TSEC1_PHYIDX 0
268#define TSEC2_PHYIDX 0
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269#define TSEC1_FLAGS TSEC_GIGABIT
270#define TSEC2_FLAGS TSEC_GIGABIT
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271
272#endif /* CONFIG_TSEC_ENET */
273
452e8e72 274#define CONFIG_ETHPRIME "TSEC0"
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275
276#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
277#undef CONFIG_ETHER_NONE /* define if ether on something else */
278
279
280/*
281 * - Rx-CLK is CLK15
282 * - Tx-CLK is CLK14
283 * - Select bus for bd/buffers
284 * - Full duplex
285 */
286#define CONFIG_ETHER_ON_FCC3
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287#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
288#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
289#define CONFIG_SYS_CPMFCR_RAMTYPE 0
290#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
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291
292/*
293 * Environment
294 */
6d0f6bcf 295#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0 296 #define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf 297 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000)
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298 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
299 #define CONFIG_ENV_SIZE 0x2000
b20d0032 300#else
6d0f6bcf 301 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
93f6d725 302 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf 303 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586 304 #define CONFIG_ENV_SIZE 0x2000
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305#endif
306
307#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 308#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
b20d0032 309
2835e518 310
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311/*
312 * BOOTP options
313 */
314#define CONFIG_BOOTP_BOOTFILESIZE
315#define CONFIG_BOOTP_BOOTPATH
316#define CONFIG_BOOTP_GATEWAY
317#define CONFIG_BOOTP_HOSTNAME
318
319
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320/*
321 * Command line configuration.
322 */
323#include <config_cmd_default.h>
324
325#define CONFIG_CMD_PING
326#define CONFIG_CMD_I2C
327#define CONFIG_CMD_DATE
328#define CONFIG_CMD_EEPROM
329
330#if defined(CONFIG_PCI)
331 #define CONFIG_CMD_PCI
332#endif
333
6d0f6bcf 334#if defined(CONFIG_SYS_RAMBOOT)
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335 #undef CONFIG_CMD_ENV
336 #undef CONFIG_CMD_LOADS
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337#endif
338
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339
340#undef CONFIG_WATCHDOG /* watchdog disabled */
341
342/*
343 * Miscellaneous configurable options
344 */
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345#define CONFIG_SYS_LONGHELP /* undef to save memory */
346#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
347#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
b20d0032 348
2835e518 349#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 350 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
b20d0032 351#else
6d0f6bcf 352 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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353#endif
354
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355#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
356#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
357#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
358#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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359#define CONFIG_LOOPW
360
361/*
362 * For booting Linux, the board info and command line data
363 * have to be in the first 8 MB of memory, since this is
364 * the maximum mapped by the Linux kernel during initialization.
365 */
6d0f6bcf 366#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
b20d0032 367
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368/*
369 * Internal Definitions
370 *
371 * Boot Flags
372 */
373#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
374#define BOOTFLAG_WARM 0x02 /* Software reboot */
375
2835e518 376#if defined(CONFIG_CMD_KGDB)
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377#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
378#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
379#endif
380
381
382/*
383 * Environment Configuration
384 */
385
386/* The mac addresses for all ethernet interface */
387#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
10327dc5 388#define CONFIG_HAS_ETH0
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389#define CONFIG_ETHADDR 00:40:42:01:00:00
390#define CONFIG_HAS_ETH1
391#define CONFIG_ETH1ADDR 00:40:42:01:00:01
392#define CONFIG_HAS_ETH2
393#define CONFIG_ETH2ADDR 00:40:42:01:00:02
394#endif
395
396
397#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
398#define CONFIG_BOOTFILE pm856/uImage
399
400#define CONFIG_HOSTNAME pm856
401#define CONFIG_IPADDR 192.168.0.103
402#define CONFIG_SERVERIP 192.168.0.64
403#define CONFIG_GATEWAYIP 192.168.0.1
404#define CONFIG_NETMASK 255.255.255.0
405
406#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
407
408#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
409#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
410
411#define CONFIG_BAUDRATE 9600
412
413#define CONFIG_EXTRA_ENV_SETTINGS \
414 "netdev=eth0\0" \
415 "consoledev=ttyS0\0" \
416 "ramdiskaddr=400000\0" \
417 "ramdiskfile=pm856/uRamdisk\0"
418
419#define CONFIG_NFSBOOTCOMMAND \
420 "setenv bootargs root=/dev/nfs rw " \
421 "nfsroot=$serverip:$rootpath " \
422 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
423 "console=$consoledev,$baudrate $othbootargs;" \
424 "tftp $loadaddr $bootfile;" \
425 "bootm $loadaddr"
426
427#define CONFIG_RAMBOOTCOMMAND \
428 "setenv bootargs root=/dev/ram rw " \
429 "console=$consoledev,$baudrate $othbootargs;" \
430 "tftp $ramdiskaddr $ramdiskfile;" \
431 "tftp $loadaddr $bootfile;" \
432 "bootm $loadaddr $ramdiskaddr"
433
434#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
435
436#endif /* __CONFIG_H */