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Commit | Line | Data |
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071d897c | 1 | /* |
a20b27a3 | 2 | * (C) Copyright 2001-2004 |
071d897c SR |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
071d897c SR |
6 | */ |
7 | ||
071d897c SR |
8 | #ifndef __CONFIG_H |
9 | #define __CONFIG_H | |
10 | ||
11 | /* | |
12 | * High Level Configuration Options | |
071d897c SR |
13 | */ |
14 | ||
15 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
c837dcb1 WD |
16 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
17 | #define CONFIG_PMC405 1 /* ...on a PMC405 board */ | |
071d897c | 18 | |
2ae18241 WD |
19 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
20 | ||
c837dcb1 WD |
21 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
22 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
071d897c | 23 | |
a20b27a3 | 24 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
071d897c SR |
25 | |
26 | #define CONFIG_BAUDRATE 9600 | |
27 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
28 | ||
2f6eb917 MF |
29 | /* Only interrupt boot if space is pressed. */ |
30 | #define CONFIG_AUTOBOOT_KEYED 1 | |
31 | #define CONFIG_AUTOBOOT_PROMPT \ | |
32 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
33 | #undef CONFIG_AUTOBOOT_DELAY_STR | |
34 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
35 | ||
c553b5f4 MF |
36 | #undef CONFIG_BOOTARGS |
37 | #undef CONFIG_BOOTCOMMAND | |
a20b27a3 | 38 | |
c553b5f4 | 39 | #define CONFIG_PREBOOT /* enable preboot variable */ |
071d897c | 40 | |
2f6eb917 MF |
41 | #define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */ |
42 | ||
071d897c | 43 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
c553b5f4 | 44 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
071d897c | 45 | |
2076d0a1 SR |
46 | #undef CONFIG_HAS_ETH1 |
47 | ||
96e21f86 | 48 | #define CONFIG_PPC4xx_EMAC |
071d897c | 49 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 50 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
c553b5f4 MF |
51 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
52 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ | |
acf02697 | 53 | |
a1aa0bb5 JL |
54 | /* |
55 | * BOOTP options | |
56 | */ | |
57 | #define CONFIG_BOOTP_BOOTFILESIZE | |
58 | #define CONFIG_BOOTP_BOOTPATH | |
59 | #define CONFIG_BOOTP_GATEWAY | |
60 | #define CONFIG_BOOTP_HOSTNAME | |
61 | ||
acf02697 JL |
62 | /* |
63 | * Command line configuration. | |
64 | */ | |
65 | #include <config_cmd_default.h> | |
66 | ||
67 | #define CONFIG_CMD_BSP | |
68 | #define CONFIG_CMD_PCI | |
69 | #define CONFIG_CMD_IRQ | |
70 | #define CONFIG_CMD_ELF | |
71 | #define CONFIG_CMD_DATE | |
72 | #define CONFIG_CMD_JFFS2 | |
73 | #define CONFIG_CMD_MII | |
74 | #define CONFIG_CMD_I2C | |
75 | #define CONFIG_CMD_PING | |
76 | #define CONFIG_CMD_UNIVERSE | |
77 | #define CONFIG_CMD_EEPROM | |
78 | ||
071d897c SR |
79 | #define CONFIG_MAC_PARTITION |
80 | #define CONFIG_DOS_PARTITION | |
81 | ||
c553b5f4 | 82 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
071d897c | 83 | |
c553b5f4 MF |
84 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */ |
85 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ | |
071d897c | 86 | |
c837dcb1 | 87 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
071d897c SR |
88 | |
89 | /* | |
90 | * Miscellaneous configurable options | |
91 | */ | |
c553b5f4 MF |
92 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
93 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
071d897c | 94 | |
c553b5f4 | 95 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
071d897c | 96 | |
acf02697 | 97 | #if defined(CONFIG_CMD_KGDB) |
c553b5f4 | 98 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
071d897c | 99 | #else |
2f6eb917 | 100 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
071d897c | 101 | #endif |
c553b5f4 MF |
102 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
103 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
104 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */ | |
071d897c | 105 | |
c553b5f4 | 106 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
071d897c | 107 | |
c553b5f4 | 108 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */ |
071d897c | 109 | |
c553b5f4 | 110 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
a20b27a3 | 111 | |
c553b5f4 MF |
112 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
113 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
071d897c | 114 | |
550650dd SR |
115 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
116 | #define CONFIG_SYS_NS16550 | |
117 | #define CONFIG_SYS_NS16550_SERIAL | |
118 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
119 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
120 | ||
c553b5f4 | 121 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */ |
2f6eb917 | 122 | #define CONFIG_SYS_BASE_BAUD 806400 |
071d897c SR |
123 | |
124 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 125 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
2f6eb917 | 126 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
071d897c | 127 | |
6d0f6bcf | 128 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
c553b5f4 | 129 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
071d897c | 130 | |
c553b5f4 | 131 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
071d897c | 132 | |
2f6eb917 | 133 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
c553b5f4 | 134 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
a20b27a3 | 135 | |
071d897c SR |
136 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
137 | ||
c837dcb1 | 138 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
53cf9435 | 139 | |
c553b5f4 | 140 | #define CONFIG_SYS_RX_ETH_BUFFER 16 |
53cf9435 | 141 | |
c553b5f4 | 142 | /* |
071d897c | 143 | * PCI stuff |
071d897c | 144 | */ |
c553b5f4 MF |
145 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
146 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
147 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
a20b27a3 | 148 | |
c553b5f4 | 149 | #define CONFIG_PCI /* include pci support */ |
842033e6 | 150 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
c553b5f4 MF |
151 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
152 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
153 | /* resource configuration */ | |
a20b27a3 | 154 | |
c553b5f4 | 155 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
a20b27a3 | 156 | |
c553b5f4 | 157 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */ |
a20b27a3 | 158 | |
c553b5f4 MF |
159 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
160 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */ | |
161 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */ | |
6d0f6bcf | 162 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid() |
2076d0a1 | 163 | |
c553b5f4 MF |
164 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */ |
165 | ||
166 | #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ | |
167 | #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */ | |
168 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
169 | #define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */ | |
170 | #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */ | |
171 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
172 | ||
82379b55 MF |
173 | #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ |
174 | ||
c553b5f4 | 175 | /* |
071d897c SR |
176 | * Start addresses for the final memory configuration |
177 | * (Set up by the startup code) | |
6d0f6bcf | 178 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
071d897c | 179 | */ |
6d0f6bcf | 180 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
14d0a02a WD |
181 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
182 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) | |
c553b5f4 | 183 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */ |
071d897c | 184 | |
2f6eb917 MF |
185 | #define CONFIG_PRAM 0 /* use pram variable to overwrite */ |
186 | ||
071d897c SR |
187 | /* |
188 | * For booting Linux, the board info and command line data | |
189 | * have to be in the first 8 MB of memory, since this is | |
190 | * the maximum mapped by the Linux kernel during initialization. | |
191 | */ | |
c553b5f4 | 192 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
071d897c | 193 | |
c553b5f4 | 194 | /* |
071d897c SR |
195 | * FLASH organization |
196 | */ | |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
198 | #define CONFIG_SYS_FLASH_INCREMENT 0x01000000 | |
071d897c | 199 | |
c553b5f4 MF |
200 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
201 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
202 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */ | |
2f6eb917 | 203 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}} |
c553b5f4 MF |
204 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */ |
205 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ | |
206 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ | |
207 | CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT} | |
208 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
209 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */ | |
071d897c | 210 | |
c553b5f4 | 211 | /* |
071d897c SR |
212 | * Environment Variable setup |
213 | */ | |
bb1f8b4f | 214 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
071d897c | 215 | |
c553b5f4 MF |
216 | /* environment starts at the beginning of the EEPROM */ |
217 | #define CONFIG_ENV_OFFSET 0x000 | |
218 | #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */ | |
219 | ||
220 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ | |
221 | #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ | |
071d897c | 222 | |
c553b5f4 | 223 | /* |
071d897c SR |
224 | * I2C EEPROM (CAT24WC16) for environment |
225 | */ | |
226 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
d0b0dcaa | 227 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
2f6eb917 | 228 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
6d0f6bcf | 229 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
071d897c | 230 | |
2f6eb917 | 231 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */ |
c553b5f4 MF |
232 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
233 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
6d0f6bcf | 234 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
2f6eb917 MF |
235 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */ |
236 | /* 16 byte page write mode using*/ | |
237 | /* last 4 bits of the address */ | |
238 | ||
c553b5f4 | 239 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
071d897c | 240 | |
c553b5f4 | 241 | /* |
071d897c SR |
242 | * External Bus Controller (EBC) Setup |
243 | */ | |
c553b5f4 MF |
244 | #define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ |
245 | #define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ | |
246 | #define CAN_BA 0xF0000000 /* CAN Base Addres */ | |
247 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
248 | #define NVRAM_BA 0xF0200000 /* NVRAM Base Address */ | |
071d897c | 249 | |
c553b5f4 | 250 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf | 251 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
c553b5f4 MF |
252 | /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ |
253 | #define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000) | |
071d897c | 254 | |
c553b5f4 | 255 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
6d0f6bcf | 256 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
c553b5f4 MF |
257 | /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ |
258 | #define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000) | |
071d897c | 259 | |
c553b5f4 MF |
260 | /* Memory Bank 2 (CAN0, 1, RTC) initialization */ |
261 | /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ | |
262 | #define CONFIG_SYS_EBC_PB2AP 0x03000440 | |
263 | /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
264 | #define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000) | |
071d897c | 265 | |
2076d0a1 SR |
266 | /* Memory Bank 3 -> unused */ |
267 | ||
c553b5f4 MF |
268 | /* Memory Bank 4 (NVRAM) initialization */ |
269 | /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ | |
270 | #define CONFIG_SYS_EBC_PB4AP 0x03000440 | |
271 | /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
272 | #define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000) | |
071d897c | 273 | |
c553b5f4 | 274 | /* |
2853d29b SR |
275 | * FPGA stuff |
276 | */ | |
2853d29b | 277 | /* FPGA program pin configuration */ |
c553b5f4 MF |
278 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */ |
279 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */ | |
280 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */ | |
281 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ | |
282 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */ | |
2853d29b | 283 | |
c553b5f4 MF |
284 | /* pass Ethernet MAC to VxWorks */ |
285 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 | |
a20b27a3 | 286 | |
c553b5f4 | 287 | /* |
2076d0a1 SR |
288 | * GPIOs |
289 | */ | |
2f6eb917 | 290 | #define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */ |
c553b5f4 MF |
291 | #define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */ |
292 | #define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */ | |
293 | #define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ | |
294 | #define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */ | |
295 | #define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */ | |
2076d0a1 | 296 | |
c553b5f4 | 297 | /* |
071d897c SR |
298 | * Definitions for initial stack pointer and data area (in data cache) |
299 | */ | |
300 | ||
c553b5f4 | 301 | /* use on chip memory (OCM) for temperary stack until sdram is tested */ |
6d0f6bcf | 302 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
071d897c SR |
303 | |
304 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
305 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
306 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
307 | ||
c553b5f4 MF |
308 | /* inside of SDRAM */ |
309 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR | |
310 | ||
311 | /* End of used area in RAM */ | |
553f0982 | 312 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE |
c553b5f4 | 313 | |
553f0982 | 314 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 315 | GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 316 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
071d897c | 317 | |
2f6eb917 MF |
318 | #define CONFIG_OF_LIBFDT |
319 | #define CONFIG_OF_BOARD_SETUP | |
320 | ||
c553b5f4 | 321 | #endif /* __CONFIG_H */ |