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c609719b WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* ------------------------------------------------------------------------- */ | |
25 | ||
26 | /* | |
27 | * board/config.h - configuration options, board specific | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC824X 1 | |
39 | #define CONFIG_MPC8240 1 | |
40 | #define CONFIG_PN62 1 | |
41 | ||
42 | #define CONFIG_CONS_INDEX 1 | |
43 | ||
44 | ||
a1aa0bb5 JL |
45 | /* |
46 | * BOOTP options | |
47 | */ | |
48 | #define CONFIG_BOOTP_BOOTFILESIZE | |
49 | #define CONFIG_BOOTP_BOOTPATH | |
50 | #define CONFIG_BOOTP_GATEWAY | |
51 | #define CONFIG_BOOTP_HOSTNAME | |
52 | ||
53 | ||
acf02697 JL |
54 | /* |
55 | * Command line configuration. | |
56 | */ | |
57 | #include <config_cmd_default.h> | |
58 | ||
59 | #define CONFIG_CMD_PCI | |
60 | #define CONFIG_CMD_BSP | |
61 | ||
62 | #undef CONFIG_CMD_AUTOSCRIPT | |
63 | #undef CONFIG_CMD_LOADS | |
64 | #undef CONFIG_CMD_ENV | |
65 | #undef CONFIG_CMD_FLASH | |
66 | #undef CONFIG_CMD_IMLS | |
c609719b | 67 | |
c609719b WD |
68 | |
69 | #define CONFIG_BAUDRATE 19200 /* console baudrate */ | |
70 | ||
71 | #define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */ | |
72 | ||
73 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
74 | ||
75 | #define CONFIG_SERVERIP 10.0.0.201 | |
53677ef1 | 76 | #define CONFIG_IPADDR 10.0.0.200 |
c609719b WD |
77 | #define CONFIG_ROOTPATH /opt/eldk/ppc_82xx |
78 | #define CONFIG_NETMASK 255.255.255.0 | |
79 | #undef CONFIG_BOOTARGS | |
80 | #if 0 | |
81 | /* Boot Linux with NFS root filesystem */ | |
82 | #define CONFIG_BOOTCOMMAND \ | |
83 | "setenv verify y;" \ | |
53677ef1 | 84 | "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ |
fe126d8b WD |
85 | "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
86 | "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ | |
c609719b | 87 | "loadp 100000; bootm" |
3bac3513 | 88 | /* "tftpboot 100000 uImage; bootm" */ |
c609719b WD |
89 | #else |
90 | /* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ | |
91 | #define CONFIG_BOOTCOMMAND \ | |
92 | "setenv verify n;" \ | |
53677ef1 | 93 | "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ |
c609719b | 94 | "root=/dev/ram rw " \ |
fe126d8b | 95 | "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ |
c609719b WD |
96 | "loadp 200000; bootm" |
97 | #endif | |
98 | ||
c609719b WD |
99 | /* |
100 | * Miscellaneous configurable options | |
101 | */ | |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
103 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
104 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
105 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
106 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
107 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
108 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ | |
109 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
c609719b WD |
110 | |
111 | #define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */ | |
112 | ||
113 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ | |
114 | ||
e2ffd59b WD |
115 | #define CONFIG_HAS_ETH1 1 /* add support for eth1addr */ |
116 | ||
c609719b WD |
117 | #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ |
118 | ||
119 | /* | |
120 | * PCI stuff | |
121 | */ | |
122 | #define CONFIG_PCI /* include pci support */ | |
123 | #define CONFIG_PCI_PNP /* we need Plug 'n Play */ | |
124 | #if 0 | |
125 | #define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */ | |
126 | #endif | |
127 | ||
128 | /* | |
129 | * Networking stuff | |
130 | */ | |
53677ef1 | 131 | #define CONFIG_NET_MULTI /* Multi ethernet cards support */ |
c609719b WD |
132 | |
133 | #define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ | |
134 | #define CONFIG_PCNET_79C973 | |
135 | ||
136 | #define _IO_BASE 0xfe000000 /* points to PCI I/O space */ | |
137 | ||
138 | ||
139 | /* | |
140 | * Start addresses for the final memory configuration | |
141 | * (Set up by the startup code) | |
6d0f6bcf | 142 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 143 | */ |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
145 | #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 | |
c609719b | 146 | |
6d0f6bcf | 147 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
c609719b | 148 | |
6d0f6bcf JCPV |
149 | #undef CONFIG_SYS_RAMBOOT |
150 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 | |
151 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
c609719b | 152 | |
6d0f6bcf JCPV |
153 | /*#define CONFIG_SYS_GBL_DATA_SIZE 256*/ |
154 | #define CONFIG_SYS_GBL_DATA_SIZE 128 | |
c609719b | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
157 | #define CONFIG_SYS_INIT_RAM_END 0x1000 | |
158 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
c609719b WD |
159 | |
160 | ||
6d0f6bcf | 161 | #define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */ |
c609719b | 162 | |
93f6d725 | 163 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
0e8d1586 JCPV |
164 | #define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ |
165 | #define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ | |
c609719b | 166 | |
6d0f6bcf | 167 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ |
c609719b | 168 | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ |
170 | #define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */ | |
c609719b WD |
171 | |
172 | /* | |
173 | * Serial port configuration | |
174 | */ | |
6d0f6bcf | 175 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
c609719b | 176 | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_NS16550 |
178 | #define CONFIG_SYS_NS16550_SERIAL | |
c609719b | 179 | |
6d0f6bcf | 180 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
c609719b | 181 | |
6d0f6bcf | 182 | #define CONFIG_SYS_NS16550_CLK 1843200 |
c609719b | 183 | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_NS16550_COM1 0xff800008 |
185 | #define CONFIG_SYS_NS16550_COM2 0xff800000 | |
c609719b WD |
186 | |
187 | /* | |
188 | * Low Level Configuration Settings | |
189 | * (address mappings, register initial values, etc.) | |
190 | * You should know what you are doing if you make changes here. | |
191 | */ | |
192 | ||
193 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
194 | #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 | |
195 | ||
6d0f6bcf | 196 | #define CONFIG_SYS_EUMB_ADDR 0xFCE00000 |
c609719b WD |
197 | |
198 | /* MCCR1 */ | |
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_ROMNAL 3 /* rom/flash next access time */ |
200 | #define CONFIG_SYS_ROMFAL 7 /* rom/flash access time */ | |
c609719b WD |
201 | |
202 | /* MCCR2 */ | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_ASRISE 6 /* ASRISE in clocks */ |
204 | #define CONFIG_SYS_ASFALL 12 /* ASFALL in clocks */ | |
205 | #define CONFIG_SYS_REFINT 5600 /* REFINT in clocks */ | |
c609719b WD |
206 | |
207 | /* MCCR3 */ | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_BSTOPRE 0x3cf /* Burst To Precharge */ |
209 | #define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ | |
210 | #define CONFIG_SYS_RDLAT 3 /* data latency from read command */ | |
c609719b WD |
211 | |
212 | /* MCCR4 */ | |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_PRETOACT 1 /* Precharge to activate interval */ |
214 | #define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */ | |
215 | #define CONFIG_SYS_ACTORW 2 /* Activate to R/W */ | |
216 | #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ | |
217 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE Wrap type */ | |
218 | #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ | |
219 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 | |
c609719b WD |
220 | |
221 | /* Memory bank settings: | |
222 | * | |
223 | * only bits 20-29 are actually used from these vales to set the | |
224 | * start/qend address the upper two bits will be 0, and the lower 20 | |
225 | * bits will be set to 0x00000 for a start address, or 0xfffff for an | |
226 | * end address | |
227 | */ | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_BANK0_START 0x00000000 |
229 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
230 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
231 | #define CONFIG_SYS_BANK1_START 0x00000000 | |
232 | #define CONFIG_SYS_BANK1_END 0x00000000 | |
233 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
234 | #define CONFIG_SYS_BANK2_START 0x00000000 | |
235 | #define CONFIG_SYS_BANK2_END 0x00000000 | |
236 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
237 | #define CONFIG_SYS_BANK3_START 0x00000000 | |
238 | #define CONFIG_SYS_BANK3_END 0x00000000 | |
239 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
240 | #define CONFIG_SYS_BANK4_START 0x00000000 | |
241 | #define CONFIG_SYS_BANK4_END 0x00000000 | |
242 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
243 | #define CONFIG_SYS_BANK5_START 0x00000000 | |
244 | #define CONFIG_SYS_BANK5_END 0x00000000 | |
245 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
246 | #define CONFIG_SYS_BANK6_START 0x00000000 | |
247 | #define CONFIG_SYS_BANK6_END 0x00000000 | |
248 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
249 | #define CONFIG_SYS_BANK7_START 0x00000000 | |
250 | #define CONFIG_SYS_BANK7_END 0x00000000 | |
251 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
c609719b WD |
252 | |
253 | /* | |
254 | * Memory bank enable bitmask, specifying which of the banks defined above | |
255 | * are actually present. MSB is for bank #7, LSB is for bank #0. | |
256 | */ | |
6d0f6bcf | 257 | #define CONFIG_SYS_BANK_ENABLE 0x01 |
c609719b | 258 | |
6d0f6bcf | 259 | #define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ |
c609719b | 260 | /* see 8240 book for bit definitions */ |
6d0f6bcf | 261 | #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ |
c609719b WD |
262 | /* currently accessed page in memory */ |
263 | /* see 8240 book for details */ | |
264 | ||
265 | /* SDRAM 0 - 256MB */ | |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
267 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
c609719b | 268 | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) |
270 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
c609719b WD |
271 | |
272 | /* PCI memory space */ | |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
274 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
c609719b WD |
275 | |
276 | /* Config addrs, etc */ | |
6d0f6bcf JCPV |
277 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
278 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
279 | ||
280 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
281 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
282 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
283 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
284 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
285 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
286 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
287 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
c609719b WD |
288 | |
289 | /* | |
290 | * For booting Linux, the board info and command line data | |
291 | * have to be in the first 8 MB of memory, since this is | |
292 | * the maximum mapped by the Linux kernel during initialization. | |
293 | */ | |
6d0f6bcf | 294 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
295 | |
296 | /* | |
297 | * Cache Configuration | |
298 | */ | |
6d0f6bcf | 299 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ |
acf02697 | 300 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 301 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
c609719b WD |
302 | #endif |
303 | ||
304 | ||
305 | /* | |
306 | * Internal Definitions | |
307 | * | |
308 | * Boot Flags | |
309 | */ | |
310 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
311 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
312 | ||
313 | ||
314 | #endif /* __CONFIG_H */ |