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3bbc899f WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * MuLogic B.V. | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Simple Network Magic Corporation | |
7 | * | |
8 | * (C) Copyright 2000 | |
9 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | /* | |
31 | * board/config.h - configuration options, board specific | |
32 | */ | |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
37 | /* various debug settings */ | |
6d0f6bcf | 38 | #undef CONFIG_SYS_DEVICE_NULLDEV /* null device */ |
3bbc899f | 39 | #undef CONFIG_SILENT_CONSOLE /* silent console */ |
6d0f6bcf | 40 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */ |
3bbc899f WD |
41 | #undef DEBUG_FLASH /* debug flash code */ |
42 | #undef FLASH_DEBUG /* debug fash code */ | |
43 | #undef DEBUG_ENV /* debug environment code */ | |
44 | ||
6d0f6bcf | 45 | #define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ |
3bbc899f WD |
46 | #define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ |
47 | ||
48 | ||
3bbc899f WD |
49 | /* |
50 | * High Level Configuration Options | |
51 | * (easy to change) | |
52 | */ | |
53 | ||
54 | #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ | |
55 | #define CONFIG_QS860T 1 /* ...on a QS860T module */ | |
56 | ||
57 | #define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */ | |
63ff004c | 58 | #define CONFIG_MII |
3bbc899f WD |
59 | #define FEC_INTERRUPT SIU_LEVEL1 |
60 | #undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */ | |
6d0f6bcf | 61 | #define CONFIG_SYS_DISCOVER_PHY |
3bbc899f WD |
62 | |
63 | #undef CONFIG_8xx_CONS_SMC1 | |
64 | #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */ | |
65 | #undef CONFIG_8xx_CONS_NONE | |
66 | ||
67 | #define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ | |
68 | ||
69 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
70 | ||
71 | /* Pass clocks to Linux 2.4.18 in Hz */ | |
72 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ | |
73 | ||
74 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 75 | "echo 'Type \\\"run flash_nfs\\\" to mount root filesystem over NFS';" \ |
3bbc899f WD |
76 | "echo" |
77 | ||
78 | #undef CONFIG_BOOTARGS | |
79 | /* TODO compare against CADM860 */ | |
80 | #define CONFIG_BOOTCOMMAND "bootp; " \ | |
fe126d8b WD |
81 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
82 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
3bbc899f WD |
83 | "bootm" |
84 | ||
85 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 86 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
3bbc899f WD |
87 | |
88 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
89 | ||
90 | #undef CONFIG_STATUS_LED /* Status LED disabled */ | |
91 | ||
92 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
93 | ||
18225e8d JL |
94 | /* |
95 | * BOOTP options | |
96 | */ | |
97 | #define CONFIG_BOOTP_SUBNETMASK | |
98 | #define CONFIG_BOOTP_GATEWAY | |
99 | #define CONFIG_BOOTP_HOSTNAME | |
100 | #define CONFIG_BOOTP_BOOTPATH | |
101 | #define CONFIG_BOOTP_BOOTFILESIZE | |
102 | ||
3bbc899f WD |
103 | |
104 | #define CONFIG_MAC_PARTITION | |
105 | #define CONFIG_DOS_PARTITION | |
106 | ||
107 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
108 | ||
3bbc899f | 109 | |
12aa9fd2 JL |
110 | /* |
111 | * Command line configuration. | |
112 | */ | |
113 | #include <config_cmd_default.h> | |
114 | ||
115 | #define CONFIG_CMD_REGINFO | |
116 | #define CONFIG_CMD_IMMAP | |
117 | #define CONFIG_CMD_ASKENV | |
118 | #define CONFIG_CMD_NET | |
119 | #define CONFIG_CMD_DHCP | |
120 | #define CONFIG_CMD_DATE | |
3bbc899f WD |
121 | |
122 | ||
123 | /* TODO */ | |
124 | #if 0 | |
125 | /* Look at these */ | |
126 | CONFIG_IPADDR | |
127 | CONFIG_SERVERIP | |
128 | CONFIG_I2C | |
129 | CONFIG_SPI | |
130 | #endif | |
131 | ||
132 | /* | |
133 | * Environment variable storage is in NVRAM | |
134 | */ | |
9314cee6 | 135 | #define CONFIG_ENV_IS_IN_NVRAM 1 |
0e8d1586 JCPV |
136 | #define CONFIG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */ |
137 | #define CONFIG_ENV_ADDR 0xD100E000 | |
3bbc899f WD |
138 | |
139 | /* | |
140 | * Miscellaneous configurable options | |
141 | */ | |
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
143 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
3bbc899f | 144 | |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
146 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
3bbc899f | 147 | |
12aa9fd2 | 148 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 149 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
3bbc899f | 150 | #else |
6d0f6bcf | 151 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
3bbc899f | 152 | #endif |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
154 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
155 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
3bbc899f WD |
156 | |
157 | /* TODO - size? */ | |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */ |
159 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
3bbc899f | 160 | |
6d0f6bcf | 161 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
3bbc899f | 162 | |
6d0f6bcf | 163 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
3bbc899f | 164 | |
6d0f6bcf | 165 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
3bbc899f WD |
166 | |
167 | /*----------------------------------------------------------------------- | |
168 | * Low Level Configuration Settings | |
169 | * (address mappings, register initial values, etc.) | |
170 | * You should know what you are doing if you make changes here. | |
171 | */ | |
172 | /*----------------------------------------------------------------------- | |
173 | * Internal Memory Mapped Register | |
174 | */ | |
6d0f6bcf | 175 | #define CONFIG_SYS_IMMR 0xF0000000 |
3bbc899f WD |
176 | |
177 | /*----------------------------------------------------------------------- | |
178 | * Definitions for initial stack pointer and data area (in DPRAM) | |
179 | */ | |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
181 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
182 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
183 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
184 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
3bbc899f WD |
185 | |
186 | /*----------------------------------------------------------------------- | |
187 | * Start addresses for the final memory configuration | |
188 | * (Set up by the startup code) | |
6d0f6bcf | 189 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
3bbc899f | 190 | */ |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
192 | #define CONFIG_SYS_FLASH_BASE 0xFFF00000 | |
3bbc899f | 193 | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
195 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
196 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
3bbc899f WD |
197 | |
198 | /* | |
199 | * For booting Linux, the board info and command line data | |
200 | * have to be in the first 8 MB of memory, since this is | |
201 | * the maximum mapped by the Linux kernel during initialization. | |
202 | */ | |
6d0f6bcf | 203 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
3bbc899f WD |
204 | |
205 | /* TODO flash parameters */ | |
206 | /*----------------------------------------------------------------------- | |
207 | * FLASH organization for Intel Strataflash | |
208 | */ | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_FLASH_16BIT 1 /* 16-bit wide flash memory */ |
210 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
211 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ | |
3bbc899f | 212 | |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
214 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
3bbc899f | 215 | |
5a1aceb0 | 216 | #undef CONFIG_ENV_IS_IN_FLASH |
3bbc899f WD |
217 | |
218 | /*----------------------------------------------------------------------- | |
219 | * Cache Configuration | |
220 | */ | |
6d0f6bcf | 221 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
12aa9fd2 | 222 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 223 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
3bbc899f WD |
224 | #endif |
225 | ||
226 | /*----------------------------------------------------------------------- | |
227 | * SYPCR - System Protection Control 11-9 | |
228 | * SYPCR can only be written once after reset! | |
229 | *----------------------------------------------------------------------- | |
230 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
231 | */ | |
232 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 233 | #define CONFIG_SYS_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI) |
3bbc899f | 234 | #else |
6d0f6bcf | 235 | #define CONFIG_SYS_SYPCR 0xFFFFFF88 |
3bbc899f WD |
236 | #endif |
237 | ||
238 | /*----------------------------------------------------------------------- | |
239 | * SIUMCR - SIU Module Configuration 11-6 | |
240 | *----------------------------------------------------------------------- | |
241 | */ | |
6d0f6bcf | 242 | #define CONFIG_SYS_SIUMCR 0x00620000 |
3bbc899f WD |
243 | |
244 | /*----------------------------------------------------------------------- | |
245 | * TBSCR - Time Base Status and Control 11-26 | |
246 | *----------------------------------------------------------------------- | |
247 | */ | |
6d0f6bcf | 248 | #define CONFIG_SYS_TBSCR 0x00C3 |
3bbc899f WD |
249 | |
250 | /*----------------------------------------------------------------------- | |
251 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
252 | *----------------------------------------------------------------------- | |
253 | */ | |
6d0f6bcf | 254 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
3bbc899f WD |
255 | |
256 | /*----------------------------------------------------------------------- | |
257 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
258 | *----------------------------------------------------------------------- | |
259 | */ | |
6d0f6bcf | 260 | #define CONFIG_SYS_PISCR 0x0082 |
3bbc899f WD |
261 | |
262 | /*----------------------------------------------------------------------- | |
263 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
264 | *----------------------------------------------------------------------- | |
265 | */ | |
6d0f6bcf | 266 | #define CONFIG_SYS_PLPRCR 0x0090D000 |
3bbc899f WD |
267 | |
268 | /*----------------------------------------------------------------------- | |
269 | * SCCR - System Clock and reset Control Register 15-27 | |
270 | *----------------------------------------------------------------------- | |
271 | */ | |
272 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 273 | #define CONFIG_SYS_SCCR 0x02000000 |
3bbc899f WD |
274 | |
275 | ||
276 | /*----------------------------------------------------------------------- | |
277 | * Debug Enable Register | |
278 | * 0x73E67C0F - All interrupts handled by BDM | |
279 | * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM | |
280 | *----------------------------------------------------------------------- | |
6d0f6bcf | 281 | #define CONFIG_SYS_DER 0x73E67C0F |
3bbc899f | 282 | */ |
6d0f6bcf | 283 | #define CONFIG_SYS_DER 0x0082400F |
3bbc899f WD |
284 | |
285 | ||
286 | /*----------------------------------------------------------------------- | |
287 | * Memory Controller Initialization Constants | |
288 | *----------------------------------------------------------------------- | |
289 | */ | |
290 | ||
291 | /* | |
292 | * BR0 and OR0 (AMD 512K Socketed FLASH) | |
293 | * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) | |
294 | */ | |
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_PRELIM_OR_AM |
296 | #define CONFIG_SYS_OR_TIMING_FLASH | |
3bbc899f WD |
297 | |
298 | #define FLASH_BASE0_PRELIM 0xFFF00001 | |
6d0f6bcf JCPV |
299 | #define CONFIG_SYS_OR0_PRELIM 0xFFF80D42 |
300 | #define CONFIG_SYS_BR0_PRELIM 0xFFF00401 | |
3bbc899f WD |
301 | |
302 | ||
303 | /* | |
304 | * BR1 and OR1 (Intel 8M StrataFLASH) | |
305 | * Base address = 0xD000_0000 - 0xD07F_FFFF | |
306 | */ | |
307 | ||
308 | #define FLASH_BASE1_PRELIM 0xD0000000 | |
6d0f6bcf JCPV |
309 | #define CONFIG_SYS_OR1_PRELIM 0xFF800D42 |
310 | #define CONFIG_SYS_BR1_PRELIM 0xD0000801 | |
311 | /* #define CONFIG_SYS_OR1 0xFF800D42 */ | |
312 | /* #define CONFIG_SYS_BR1 0xD0000801 */ | |
3bbc899f WD |
313 | |
314 | ||
315 | /* | |
316 | * BR2 and OR2 (SDRAM) | |
317 | * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) | |
318 | * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) | |
319 | * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) | |
320 | * | |
321 | */ | |
322 | #define SDRAM_BASE 0x00000000 /* SDRAM bank */ | |
323 | #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ | |
324 | ||
325 | /* SDRAM timing */ | |
326 | #define SDRAM_TIMING 0x00000A00 | |
327 | ||
328 | /* For boards with 16M of SDRAM */ | |
329 | #define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ | |
6d0f6bcf | 330 | #define CONFIG_SYS_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */ |
3bbc899f WD |
331 | |
332 | /* For boards with 64M of SDRAM */ | |
333 | #define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */ | |
334 | /* TODO - determine real value */ | |
6d0f6bcf | 335 | #define CONFIG_SYS_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */ |
3bbc899f | 336 | |
6d0f6bcf JCPV |
337 | #define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING) |
338 | #define CONFIG_SYS_BR2 (SDRAM_BASE | 0x000000C1) | |
3bbc899f WD |
339 | |
340 | ||
341 | /* | |
342 | * BR3 and OR3 (NVRAM, Sipex, NAND Flash) | |
343 | * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM) | |
344 | * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register) | |
345 | * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register) | |
346 | * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register) | |
347 | * | |
348 | */ | |
349 | ||
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_OR3_PRELIM 0xFFC00DF6 |
351 | #define CONFIG_SYS_BR3_PRELIM 0xD1000401 | |
352 | /* #define CONFIG_SYS_OR3 0xFFC00DF6 */ | |
353 | /* #define CONFIG_SYS_BR3 0xD1000401 */ | |
3bbc899f WD |
354 | |
355 | ||
356 | /* | |
357 | * BR4 and OR4 (Unused) | |
358 | * Base address = 0xE000_0000 - 0xE3FF_FFFF | |
359 | * | |
360 | */ | |
361 | ||
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_OR4_PRELIM 0xFF000000 |
363 | #define CONFIG_SYS_BR4_PRELIM 0xE0000000 | |
364 | /* #define CONFIG_SYS_OR4 0xFF000000 */ | |
365 | /* #define CONFIG_SYS_BR4 0xE0000000 */ | |
3bbc899f WD |
366 | |
367 | ||
368 | /* | |
369 | * BR5 and OR5 (Expansion bus) | |
370 | * Base address = 0xE400_0000 - 0xE7FF_FFFF | |
371 | * | |
372 | */ | |
373 | ||
6d0f6bcf JCPV |
374 | #define CONFIG_SYS_OR5_PRELIM 0xFF000000 |
375 | #define CONFIG_SYS_BR5_PRELIM 0xE4000000 | |
376 | /* #define CONFIG_SYS_OR5 0xFF000000 */ | |
377 | /* #define CONFIG_SYS_BR5 0xE4000000 */ | |
3bbc899f WD |
378 | |
379 | ||
3bbc899f WD |
380 | /* |
381 | * BR6 and OR6 (Expansion bus) | |
382 | * Base address = 0xE800_0000 - 0xEBFF_FFFF | |
383 | * | |
384 | */ | |
385 | ||
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_OR6_PRELIM 0xFF000000 |
387 | #define CONFIG_SYS_BR6_PRELIM 0xE8000000 | |
388 | /* #define CONFIG_SYS_OR6 0xFF000000 */ | |
389 | /* #define CONFIG_SYS_BR6 0xE8000000 */ | |
3bbc899f WD |
390 | |
391 | ||
3bbc899f WD |
392 | /* |
393 | * BR7 and OR7 (Expansion bus) | |
394 | * Base address = 0xEC00_0000 - 0xEFFF_FFFF | |
395 | * | |
396 | */ | |
397 | ||
6d0f6bcf JCPV |
398 | #define CONFIG_SYS_OR7_PRELIM 0xFF000000 |
399 | #define CONFIG_SYS_BR7_PRELIM 0xE8000000 | |
400 | /* #define CONFIG_SYS_OR7 0xFF000000 */ | |
401 | /* #define CONFIG_SYS_BR7 0xE8000000 */ | |
3bbc899f WD |
402 | |
403 | ||
3bbc899f WD |
404 | /* |
405 | * Internal Definitions | |
406 | * | |
407 | * Boot Flags | |
408 | */ | |
409 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
410 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
411 | ||
412 | /* | |
413 | * Sanity checks | |
414 | */ | |
415 | #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) | |
416 | #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured | |
417 | #endif | |
418 | ||
419 | #endif /* __CONFIG_H */ |