[people/ms/u-boot.git] / include / configs / R360MPI.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_R360MPI		1

#define CONFIG_LCD
#undef  CONFIG_EDT32F10
#define CONFIG_SHARP_LQ057Q3DC02

#define	CONFIG_SPLASH_SCREEN

#define MPC8XX_FACT             1		/* Multiply by 1	*/
#define MPC8XX_XIN              50000000	/* 50 MHz in		*/
#define CONFIG_8xx_GCLK_FREQ    50000000 /* define if can't use get_gclk_freq */

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate in bps	*/
#if 0
#define CONFIG_BOOTDELAY	0	/* immediate boot		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#undef	CONFIG_SCC1_ENET
#define	CONFIG_SCC2_ENET

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#define	CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_CAN_DRIVER		/* CAN Driver support enabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

#define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
#undef CONFIG_SORT_I2C			/* To I2C with software support */
#define CFG_I2C_SPEED		4700	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL			0x00000020	/* PB 26 */
#define PB_SDA			0x00000010	/* PB 27 */

#define I2C_INIT		(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE		(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ		((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
				else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
				else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY		udelay(50)

#define CFG_I2C_LCD_ADDR	0x8	/* LCD Control */
#define CFG_I2C_KEY_ADDR	0x9	/* Keyboard coprocessor */
#define CFG_I2C_TEM_ADDR	0x49	/* Temperature Sensors */


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BMP
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_SNTP


/*
 * Miscellaneous configurable options
 */
#define CFG_DEVICE_NULLDEV	1	/* we need the null device	*/
#define CFG_CONSOLE_IS_IN_ENV	1	/* must set console from env	*/

#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * JFFS2 partitions
 */
/* No command line, one static partition
 * use all the space starting at offset 3MB*/
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00300000

/* mtdparts command line support */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=r360-0"
#define MTDPARTS_DEFAULT	"mtdparts=r360-0:-@3m(user)"
*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000
#if defined(DEBUG)
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CFG_ENV_OFFSET		0x40000	/* Offset of Environment		*/
#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
#define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment sector	*/
#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
#define CFG_PLPRCR							\
		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
#else			/* up to 50 MHz we use a 1:1 clock */
#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#endif	/* CONFIG_80MHz */

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#if 1
#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0100
#endif

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xFF000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )


/*
 * BR2 and OR2 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

#define CFG_PRELIM_OR2_AM	0xF8000000	/* OR addr mask */

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	(OR_ACS_DIV1  | OR_CSNT_SAM | \
				 OR_SCY_0_CLK | OR_G5LS)

#define CFG_OR2_PRELIM	(CFG_PRELIM_OR2_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * BR3 and OR3 (CAN Controller)
 */
#ifdef CONFIG_CAN_DRIVER
#define CFG_CAN_BASE		0xC0000000	/* CAN base address   */
#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask */
#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA |OR_BI)
#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
				 BR_PS_8 | BR_MS_UPMB | BR_V)
#endif	/* CONFIG_CAN_DRIVER */


/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
#if   defined(CONFIG_80MHz)
#define CFG_MAMR_PTA		156
#elif defined(CONFIG_66MHz)
#define CFG_MAMR_PTA		129
#else		/*   50 MHz */
#define CFG_MAMR_PTA		 98
#endif	/*CONFIG_??MHz */

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
ce23b153	1	/*
414eec35	2	* (C) Copyright 2000-2005
ce23b153 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
	37	#define CONFIG_R360MPI 1
	38
	39	#define CONFIG_LCD
	40	#undef CONFIG_EDT32F10
	41	#define CONFIG_SHARP_LQ057Q3DC02
	42
d791b1dc WD	43	#define CONFIG_SPLASH_SCREEN
d791b1dc WD	44
ce23b153 WD	45	#define MPC8XX_FACT 1 /* Multiply by 1 */
	46	#define MPC8XX_XIN 50000000 /* 50 MHz in */
	47	#define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */
	48
	49	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	50	#undef CONFIG_8xx_CONS_SMC2
	51	#undef CONFIG_8xx_CONS_NONE
4a6fd34b	52	#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */
ce23b153	53	#if 0
cb4dbb7b	54	#define CONFIG_BOOTDELAY 0 /* immediate boot */
ce23b153 WD	55	#else
	56	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	57	#endif
	58
	59	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	60
32bf3d14	61	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
ce23b153 WD	62
	63	#undef CONFIG_BOOTARGS
	64	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	65	"bootp; " \
	66	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	67	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
ce23b153 WD	68	"bootm"
	69
	70	#undef CONFIG_SCC1_ENET
	71	#define CONFIG_SCC2_ENET
	72
	73	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	74	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	75
	76	#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
	77
	78	#undef CONFIG_WATCHDOG /* watchdog disabled */
	79
4a6fd34b	80	#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
ce23b153	81
18225e8d JL	82	/*
	83	* BOOTP options
	84	*/
	85	#define CONFIG_BOOTP_SUBNETMASK
	86	#define CONFIG_BOOTP_GATEWAY
	87	#define CONFIG_BOOTP_HOSTNAME
	88	#define CONFIG_BOOTP_BOOTPATH
	89	#define CONFIG_BOOTP_BOOTFILESIZE
ce23b153 WD	90
	91	#define CONFIG_MAC_PARTITION
	92	#define CONFIG_DOS_PARTITION
	93
	94	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	95
	96	#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
	97	#undef CONFIG_SORT_I2C /* To I2C with software support */
	98	#define CFG_I2C_SPEED 4700 /* I2C speed and slave address */
	99	#define CFG_I2C_SLAVE 0x7F
	100
	101	/*
	102	* Software (bit-bang) I2C driver configuration
	103	*/
	104	#define PB_SCL 0x00000020 /* PB 26 */
	105	#define PB_SDA 0x00000010 /* PB 27 */
	106
	107	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	108	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	109	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	110	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	111	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	112	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	113	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	114	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	115	#define I2C_DELAY udelay(50)
	116
4a6fd34b WD	117	#define CFG_I2C_LCD_ADDR 0x8 /* LCD Control */
	118	#define CFG_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
	119	#define CFG_I2C_TEM_ADDR 0x49 /* Temperature Sensors */
ce23b153	120
e9a0f8f1 JL	121
	122	/*
	123	* Command line configuration.
	124	*/
	125	#include <config_cmd_default.h>
	126
	127	#define CONFIG_CMD_BMP
	128	#define CONFIG_CMD_BSP
	129	#define CONFIG_CMD_DATE
	130	#define CONFIG_CMD_DHCP
	131	#define CONFIG_CMD_I2C
	132	#define CONFIG_CMD_IDE
	133	#define CONFIG_CMD_JFFS2
	134	#define CONFIG_CMD_NFS
	135	#define CONFIG_CMD_PCMCIA
	136	#define CONFIG_CMD_SNTP
	137
ce23b153 WD	138
	139	/*
	140	* Miscellaneous configurable options
	141	*/
cb4dbb7b WD	142	#define CFG_DEVICE_NULLDEV 1 /* we need the null device */
	143	#define CFG_CONSOLE_IS_IN_ENV 1 /* must set console from env */
	144
ce23b153 WD	145	#define CFG_LONGHELP /* undef to save memory */
ce23b153 WD	146	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
e9a0f8f1	147	#if defined(CONFIG_CMD_KGDB)
ce23b153 WD	148	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	149	#else
	150	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	151	#endif
	152	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	153	#define CFG_MAXARGS 16 /* max number of command args */
	154	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	155
	156	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	157	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	158
	159	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	160
	161	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	162
	163	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	164
700a0c64 WD	165	/*
	166	* JFFS2 partitions
	167	*/
	168	/* No command line, one static partition
	169	* use all the space starting at offset 3MB*/
	170	#undef CONFIG_JFFS2_CMDLINE
	171	#define CONFIG_JFFS2_DEV "nor0"
	172	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	173	#define CONFIG_JFFS2_PART_OFFSET 0x00300000
	174
	175	/* mtdparts command line support */
	176	/*
	177	#define CONFIG_JFFS2_CMDLINE
	178	#define MTDIDS_DEFAULT "nor0=r360-0"
	179	#define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)"
	180	*/
cb4dbb7b	181
ce23b153 WD	182	/*
	183	* Low Level Configuration Settings
	184	* (address mappings, register initial values, etc.)
	185	* You should know what you are doing if you make changes here.
	186	*/
	187	/*-----------------------------------------------------------------------
	188	* Internal Memory Mapped Register
	189	*/
	190	#define CFG_IMMR 0xFF000000
	191
	192	/*-----------------------------------------------------------------------
	193	* Definitions for initial stack pointer and data area (in DPRAM)
	194	*/
	195	#define CFG_INIT_RAM_ADDR CFG_IMMR
	196	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	197	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	198	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	199	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	200
	201	/*-----------------------------------------------------------------------
	202	* Start addresses for the final memory configuration
	203	* (Set up by the startup code)
	204	* Please note that CFG_SDRAM_BASE _must_ start at 0
	205	*/
	206	#define CFG_SDRAM_BASE 0x00000000
	207	#define CFG_FLASH_BASE 0x40000000
	208	#if defined(DEBUG)
	209	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	210	#else
	211	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	212	#endif
	213	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	214	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	215
	216	/*
	217	* For booting Linux, the board info and command line data
	218	* have to be in the first 8 MB of memory, since this is
	219	* the maximum mapped by the Linux kernel during initialization.
	220	*/
	221	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	222
	223	/*-----------------------------------------------------------------------
	224	* FLASH organization
	225	*/
	226	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	227	#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
	228
	229	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	230	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	231
5a1aceb0	232	#define CONFIG_ENV_IS_IN_FLASH 1
ce23b153 WD	233	#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */
	234	#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
	235	#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
67c31036	236	#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
ce23b153 WD	237
	238	/*-----------------------------------------------------------------------
	239	* Cache Configuration
	240	*/
	241	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
e9a0f8f1	242	#if defined(CONFIG_CMD_KGDB)
ce23b153 WD	243	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	244	#endif
	245
	246	/*-----------------------------------------------------------------------
	247	* SYPCR - System Protection Control 11-9
	248	* SYPCR can only be written once after reset!
	249	*-----------------------------------------------------------------------
	250	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	251	*/
	252	#if defined(CONFIG_WATCHDOG)
	253	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	254	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	255	#else
	256	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	257	#endif
	258
	259	/*-----------------------------------------------------------------------
	260	* SIUMCR - SIU Module Configuration 11-6
	261	*-----------------------------------------------------------------------
	262	* PCMCIA config., multi-function pin tri-state
	263	*/
ce23b153	264	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
ce23b153 WD	265
	266	/*-----------------------------------------------------------------------
	267	* TBSCR - Time Base Status and Control 11-26
	268	*-----------------------------------------------------------------------
	269	* Clear Reference Interrupt Status, Timebase freezing enabled
	270	*/
	271	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
	272
	273	/*-----------------------------------------------------------------------
	274	* RTCSC - Real-Time Clock Status and Control Register 11-27
	275	*-----------------------------------------------------------------------
	276	*/
	277	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
	278
	279	/*-----------------------------------------------------------------------
	280	* PISCR - Periodic Interrupt Status and Control 11-31
	281	*-----------------------------------------------------------------------
	282	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	283	*/
	284	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	285
	286	/*-----------------------------------------------------------------------
	287	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	288	*-----------------------------------------------------------------------
	289	* Reset PLL lock status sticky bit, timer expired status bit and timer
	290	* interrupt status bit
	291	*
	292	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	293	*/
	294	#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
	295	#define CFG_PLPRCR \
	296	( (5-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_TMIST )
	297	#else /* up to 50 MHz we use a 1:1 clock */
	298	#define CFG_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
	299	#endif /* CONFIG_80MHz */
	300
	301	/*-----------------------------------------------------------------------
	302	* SCCR - System Clock and reset Control Register 15-27
	303	*-----------------------------------------------------------------------
	304	* Set clock output, timebase and RTC source and divider,
	305	* power management and some other internal clocks
	306	*/
	307	#define SCCR_MASK SCCR_EBDF11
	308	#define CFG_SCCR (SCCR_TBS \| \
	309	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	310	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	311	SCCR_DFALCD00)
	312
	313	/*-----------------------------------------------------------------------
	314	* PCMCIA stuff
	315	*-----------------------------------------------------------------------
	316	*
	317	*/
	318	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
	319	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
	320	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
	321	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
	322	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
	323	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	324	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
	325	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
	326
	327	/*-----------------------------------------------------------------------
	328	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
329	*-----------------------------------------------------------------------
330	*/
331
332	#if 1
333	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
334
335	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
336	#undef CONFIG_IDE_LED /* LED for ide not supported */
337	#undef CONFIG_IDE_RESET /* reset for ide not supported */
338
339	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
340	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
341
342	#define CFG_ATA_IDE0_OFFSET 0x0000
343
344	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
345
346	/* Offset for data I/O */
347	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
348
349	/* Offset for normal register accesses */
350	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
351
352	/* Offset for alternate registers */
353	#define CFG_ATA_ALT_OFFSET 0x0100
354	#endif
355
356	/*-----------------------------------------------------------------------
357	*
358	*-----------------------------------------------------------------------
359	*
360	*/
3b57fe0a	361	#define CFG_DER 0
ce23b153 WD	362
	363	/*
	364	* Init Memory Controller:
	365	*
	366	* BR0/1 and OR0/1 (FLASH)
	367	*/
	368
	369	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	370
	371	/* used to re-map FLASH both when starting from SRAM or FLASH:
	372	* restrict access enough to keep SRAM working (if any)
	373	* but not too much to meddle with FLASH accesses
	374	*/
	375	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
	376	#define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
	377
	378	/*
	379	* FLASH timing:
	380	*/
	381	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_SCY_7_CLK \| OR_BI)
	382
	383	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
	384	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	385	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
	386
	387
	388	/*
4a6fd34b	389	* BR2 and OR2 (SDRAM)
ce23b153 WD	390	*
ce23b153 WD	391	*/
4a6fd34b	392	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
ce23b153 WD	393	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
ce23b153 WD	394
4a6fd34b	395	#define CFG_PRELIM_OR2_AM 0xF8000000 /* OR addr mask */
ce23b153 WD	396
	397	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
	398	#define CFG_OR_TIMING_SDRAM (OR_ACS_DIV1 \| OR_CSNT_SAM \| \
	399	OR_SCY_0_CLK \| OR_G5LS)
	400
4a6fd34b WD	401	#define CFG_OR2_PRELIM (CFG_PRELIM_OR2_AM \| CFG_OR_TIMING_SDRAM )
	402	#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	403
	404	/*
	405	* BR3 and OR3 (CAN Controller)
	406	*/
	407	#ifdef CONFIG_CAN_DRIVER
	408	#define CFG_CAN_BASE 0xC0000000 /* CAN base address */
	409	#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	410	#define CFG_OR3_CAN (CFG_CAN_OR_AM \| OR_G5LA \|OR_BI)
	411	#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) \| \
	412	BR_PS_8 \| BR_MS_UPMB \| BR_V)
	413	#endif /* CONFIG_CAN_DRIVER */
ce23b153 WD	414
	415
	416	/*
	417	* Memory Periodic Timer Prescaler
	418	*
	419	* The Divider for PTA (refresh timer) configuration is based on an
	420	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	421	* the number of chip selects (NCS) and the actually needed refresh
	422	* rate is done by setting MPTPR.
	423	*
	424	* PTA is calculated from
	425	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	426	*
	427	* gclk CPU clock (not bus clock!)
	428	* Trefresh Refresh cycle * 4 (four word bursts used)
	429	*
	430	* 4096 Rows from SDRAM example configuration
	431	* 1000 factor s -> ms
	432	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	433	* 4 Number of refresh cycles per period
	434	* 64 Refresh cycle in ms per number of rows
	435	* --------------------------------------------
	436	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	437	*
	438	* 50 MHz => 50.000.000 / Divider = 98
	439	* 66 Mhz => 66.000.000 / Divider = 129
	440	* 80 Mhz => 80.000.000 / Divider = 156
	441	*/
	442	#if defined(CONFIG_80MHz)
	443	#define CFG_MAMR_PTA 156
	444	#elif defined(CONFIG_66MHz)
	445	#define CFG_MAMR_PTA 129
	446	#else /* 50 MHz */
	447	#define CFG_MAMR_PTA 98
	448	#endif /CONFIG_??MHz /
	449
	450	/*
	451	* For 16 MBit, refresh rates could be 31.3 us
	452	* (= 64 ms / 2K = 125 / quad bursts).
	453	* For a simpler initialization, 15.6 us is used instead.
	454	*
	455	* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
	456	* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
	457	*/
	458	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
	459	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
	460
	461	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
	462	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
	463	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
	464
	465	/*
	466	* MAMR settings for SDRAM
	467	*/
	468
	469	/* 8 column SDRAM */
	470	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	471	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	472	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	473	/* 9 column SDRAM */
	474	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	475	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	476	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	477
478
479	/*
480	* Internal Definitions
481	*
482	* Boot Flags
483	*/
484	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
485	#define BOOTFLAG_WARM 0x02 /* Software reboot */
486
487	#endif /* __CONFIG_H */