[people/ms/u-boot.git] / include / configs / Sandpoint8245.h

/*
 * (C) Copyright 2001-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_SANDPOINT	1

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
#define CONFIG_SYS_LDSCRIPT	"board/sandpoint/u-boot.lds"

#if 0
#define USE_DINK32		1
#else
#undef USE_DINK32
#endif

#define CONFIG_CONS_INDEX     3               /* set to '3' for on-chip DUART */
#define CONFIG_BAUDRATE		9600
#define CONFIG_DRAM_SPEED	100		/* MHz				*/

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI				/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#undef CONFIG_PCI_PNP


#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
#define CONFIG_NATSEMI
#define CONFIG_NS8382X

#define PCI_ENET0_IOADDR	0x80000000
#define PCI_ENET0_MEMADDR	0x80000000
#define	PCI_ENET1_IOADDR	0x81000000
#define	PCI_ENET1_MEMADDR	0x81000000


/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000

#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100

#if defined (USE_DINK32)
#define CONFIG_SYS_MONITOR_LEN		0x00030000
#define CONFIG_SYS_MONITOR_BASE	0x00090000
#define CONFIG_SYS_RAMBOOT		1
#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#else
#undef	CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN		0x00030000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE


#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#endif

#define CONFIG_SYS_FLASH_BASE		0xFFF00000
#if 0
#define CONFIG_SYS_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
#else
#define CONFIG_SYS_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
#endif
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */

#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/

#define CONFIG_SYS_EUMB_ADDR		0xFC000000

#define CONFIG_SYS_ISA_MEM		0xFD000000
#define CONFIG_SYS_ISA_IO		0xFE000000

#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/

/*
 * select i2c support configuration
 *
 * Supported configurations are {none, software, hardware} drivers.
 * If the software driver is chosen, there are some additional
 * configuration items that the driver uses to drive the port pins.
 */
#define CONFIG_HARD_I2C		1		/* To enable I2C support */
#undef  CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C_SPEED	400000
#define CONFIG_SYS_I2C_SLAVE	0x7F

#ifdef CONFIG_SYS_I2C_SOFT
#error "Soft I2C is not configured properly.  Please review!"
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
#define I2C_READ		((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
				else    iop->pdat &= ~0x00010000
#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
				else    iop->pdat &= ~0x00020000
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
#endif /* CONFIG_SYS_I2C_SOFT */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */


/* #define CONFIG_WINBOND_83C553	1	/ *has a winbond bridge			*/
#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/

#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

/*
 * NS87308 Configuration
 */
#define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */

#define CONFIG_SYS_NS87308_BADDR_10	1

#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
				  CONFIG_SYS_NS87308_UART2   | \
				  CONFIG_SYS_NS87308_POWRMAN | \
				  CONFIG_SYS_NS87308_RTC_APC )

#undef  CONFIG_SYS_NS87308_PS2MOD

#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
#define CONFIG_SYS_NS87308_CS0_CONF	0x30
#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
#define CONFIG_SYS_NS87308_CS1_CONF	0x30
#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
#define CONFIG_SYS_NS87308_CS2_CONF	0x30

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#if (CONFIG_CONS_INDEX > 2)
#define CONFIG_SYS_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
#else
#define CONFIG_SYS_NS16550_CLK         1843200
#endif

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4500)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_EUMB_ADDR + 0x4600)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */

#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/

#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */

/* the following are for SDRAM only*/
#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#if 0
#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
#endif

#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
#define CONFIG_SYS_EXTROM 1
#define CONFIG_SYS_REGDIMM 0


/* memory bank settings*/
/*
 * only bits 20-29 are actually used from these vales to set the
 * start/end address the upper two bits will be 0, and the lower 20
 * bits will be set to 0x00000 for a start address, or 0xfffff for an
 * end address
 */
#define CONFIG_SYS_BANK0_START		0x00000000
#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE	1
#define CONFIG_SYS_BANK1_START		0x3ff00000
#define CONFIG_SYS_BANK1_END		0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE	0
#define CONFIG_SYS_BANK2_START		0x3ff00000
#define CONFIG_SYS_BANK2_END		0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE	0
#define CONFIG_SYS_BANK3_START		0x3ff00000
#define CONFIG_SYS_BANK3_END		0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE	0
#define CONFIG_SYS_BANK4_START		0x00000000
#define CONFIG_SYS_BANK4_END		0x00000000
#define CONFIG_SYS_BANK4_ENABLE	0
#define CONFIG_SYS_BANK5_START		0x00000000
#define CONFIG_SYS_BANK5_END		0x00000000
#define CONFIG_SYS_BANK5_ENABLE	0
#define CONFIG_SYS_BANK6_START		0x00000000
#define CONFIG_SYS_BANK6_END		0x00000000
#define CONFIG_SYS_BANK6_ENABLE	0
#define CONFIG_SYS_BANK7_START		0x00000000
#define CONFIG_SYS_BANK7_END		0x00000000
#define CONFIG_SYS_BANK7_ENABLE	0
/*
 * Memory bank enable bitmask, specifying which of the banks defined above
 are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CONFIG_SYS_BANK_ENABLE		0x01

#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
					/* see 8240 book for bit definitions	*/
#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

/* SDRAM 0 - 256MB */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE @ 1GB (no backing mem) */
#if defined(USE_DINK32)
#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
#else
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#endif

/* PCI memory */
#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* Flash, config addrs, etc */
#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/* values according to the manual */

#define CONFIG_DRAM_50MHZ	1
#define CONFIG_SDRAM_50MHZ

#undef	NR_8259_INTS
#define NR_8259_INTS		1


#define CONFIG_DISK_SPINUP_TIME 1000000


#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b	1	/*
414eec35	2	* (C) Copyright 2001-2005
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
c609719b WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/* ------------------------------------------------------------------------- */
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
	22	#define CONFIG_MPC824X 1
	23	#define CONFIG_MPC8245 1
	24	#define CONFIG_SANDPOINT 1
	25
2ae18241	26	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
de550d6b	27	#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds"
2ae18241	28
c609719b WD	29	#if 0
	30	#define USE_DINK32 1
	31	#else
	32	#undef USE_DINK32
	33	#endif
	34
	35	#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
	36	#define CONFIG_BAUDRATE 9600
	37	#define CONFIG_DRAM_SPEED 100 /* MHz */
	38
414eec35 WD	39	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
414eec35 WD	40
c609719b	41
a1aa0bb5 JL	42	/*
	43	* BOOTP options
	44	*/
	45	#define CONFIG_BOOTP_BOOTFILESIZE
	46	#define CONFIG_BOOTP_BOOTPATH
	47	#define CONFIG_BOOTP_GATEWAY
	48	#define CONFIG_BOOTP_HOSTNAME
	49
	50
fe7f782d JL	51	/*
	52	* Command line configuration.
	53	*/
	54	#include <config_cmd_default.h>
	55
	56	#define CONFIG_CMD_DHCP
	57	#define CONFIG_CMD_ELF
	58	#define CONFIG_CMD_I2C
	59	#define CONFIG_CMD_EEPROM
	60	#define CONFIG_CMD_NFS
	61	#define CONFIG_CMD_PCI
	62	#define CONFIG_CMD_SNTP
c609719b WD	63
	64
	65	/*
	66	* Miscellaneous configurable options
	67	*/
6d0f6bcf	68	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
6d0f6bcf JCPV	69	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	70	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	71	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	72	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	73	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
	74	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b WD	75
	76	/*-----------------------------------------------------------------------
	77	* PCI stuff
	78	*-----------------------------------------------------------------------
	79	*/
	80	#define CONFIG_PCI /* include pci support */
842033e6	81	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c609719b WD	82	#undef CONFIG_PCI_PNP
c609719b WD	83
c609719b WD	84
c609719b WD	85	#define CONFIG_EEPRO100
6d0f6bcf	86	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
c609719b WD	87	#define CONFIG_NATSEMI
	88	#define CONFIG_NS8382X
	89
	90	#define PCI_ENET0_IOADDR 0x80000000
	91	#define PCI_ENET0_MEMADDR 0x80000000
	92	#define PCI_ENET1_IOADDR 0x81000000
	93	#define PCI_ENET1_MEMADDR 0x81000000
	94
	95
	96	/*-----------------------------------------------------------------------
	97	* Start addresses for the final memory configuration
	98	* (Set up by the startup code)
6d0f6bcf	99	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	100	*/
6d0f6bcf JCPV	101	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	102	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
c609719b	103
6d0f6bcf	104	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
c609719b WD	105
c609719b WD	106	#if defined (USE_DINK32)
6d0f6bcf JCPV	107	#define CONFIG_SYS_MONITOR_LEN 0x00030000
	108	#define CONFIG_SYS_MONITOR_BASE 0x00090000
	109	#define CONFIG_SYS_RAMBOOT 1
	110	#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
553f0982	111	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
25ddd1fb	112	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	113	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b	114	#else
6d0f6bcf JCPV	115	#undef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	116	#define CONFIG_SYS_MONITOR_LEN 0x00030000
14d0a02a	117	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
c609719b	118
c609719b	119
6d0f6bcf	120	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	121	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	122	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
c609719b WD	123
	124	#endif
	125
6d0f6bcf	126	#define CONFIG_SYS_FLASH_BASE 0xFFF00000
c609719b	127	#if 0
6d0f6bcf	128	#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
c609719b	129	#else
6d0f6bcf	130	#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
c609719b	131	#endif
5a1aceb0	132	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	133	#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
0e8d1586 JCPV	134	#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
c609719b	135
6d0f6bcf	136	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
c609719b	137
6d0f6bcf JCPV	138	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
6d0f6bcf JCPV	139	#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
c609719b	140
6d0f6bcf	141	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
c609719b	142
6d0f6bcf JCPV	143	#define CONFIG_SYS_ISA_MEM 0xFD000000
6d0f6bcf JCPV	144	#define CONFIG_SYS_ISA_IO 0xFE000000
c609719b	145
6d0f6bcf JCPV	146	#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
6d0f6bcf JCPV	147	#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
c609719b WD	148	#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
	149	#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
	150
	151	/*
	152	* select i2c support configuration
	153	*
	154	* Supported configurations are {none, software, hardware} drivers.
	155	* If the software driver is chosen, there are some additional
	156	* configuration items that the driver uses to drive the port pins.
	157	*/
ea818dbb HS	158	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
	159	#undef CONFIG_SYS_I2C_SOFT
	160	#define CONFIG_SYS_I2C_SPEED 400000
	161	#define CONFIG_SYS_I2C_SLAVE 0x7F
c609719b	162
ea818dbb	163	#ifdef CONFIG_SYS_I2C_SOFT
c609719b	164	#error "Soft I2C is not configured properly. Please review!"
ea818dbb HS	165	#define CONFIG_SYS_I2C
	166	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	167	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
c609719b WD	168	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	169	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	170	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
	171	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
	172	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
	173	else iop->pdat &= ~0x00010000
	174	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
	175	else iop->pdat &= ~0x00020000
	176	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
ea818dbb	177	#endif /* CONFIG_SYS_I2C_SOFT */
c609719b	178
6d0f6bcf JCPV	179	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
	180	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	181	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	182	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c609719b	183
6d0f6bcf	184	#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
c609719b WD	185
	186	/*-----------------------------------------------------------------------
	187	* Definitions for initial stack pointer and data area (in DPRAM)
	188	*/
	189
	190
57d6c589	191	/* #define CONFIG_WINBOND_83C553 1 / has a winbond bridge /
6d0f6bcf JCPV	192	#define CONFIG_SYS_USE_WINBOND_IDE 0 /use winbond 83c553 internal IDE ctrlr /
	193	#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /pci-isa bridge config addr /
	194	#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /ide config addr /
c609719b	195
6d0f6bcf JCPV	196	#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
6d0f6bcf JCPV	197	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS2) / max. 2 drives per IDE bus */
c609719b WD	198
	199	/*
	200	* NS87308 Configuration
	201	*/
55d6d2d3	202	#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
c609719b	203
6d0f6bcf	204	#define CONFIG_SYS_NS87308_BADDR_10 1
c609719b	205
6d0f6bcf JCPV	206	#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 \| \
	207	CONFIG_SYS_NS87308_UART2 \| \
	208	CONFIG_SYS_NS87308_POWRMAN \| \
	209	CONFIG_SYS_NS87308_RTC_APC )
c609719b	210
6d0f6bcf	211	#undef CONFIG_SYS_NS87308_PS2MOD
c609719b	212
6d0f6bcf JCPV	213	#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
	214	#define CONFIG_SYS_NS87308_CS0_CONF 0x30
	215	#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
	216	#define CONFIG_SYS_NS87308_CS1_CONF 0x30
	217	#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
	218	#define CONFIG_SYS_NS87308_CS2_CONF 0x30
c609719b WD	219
	220	/*
	221	* NS16550 Configuration
	222	*/
6d0f6bcf JCPV	223	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	224	#define CONFIG_SYS_NS16550_SERIAL
c609719b	225
6d0f6bcf	226	#define CONFIG_SYS_NS16550_REG_SIZE 1
c609719b	227
f832d8a1	228	#if (CONFIG_CONS_INDEX > 2)
6d0f6bcf	229	#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
f832d8a1	230	#else
6d0f6bcf	231	#define CONFIG_SYS_NS16550_CLK 1843200
f832d8a1	232	#endif
49822e23	233
6d0f6bcf JCPV	234	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
	235	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
	236	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
	237	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
c609719b WD	238
	239	/*
	240	* Low Level Configuration Settings
	241	* (address mappings, register initial values, etc.)
	242	* You should know what you are doing if you make changes here.
	243	*/
	244
	245	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	246
6d0f6bcf JCPV	247	#define CONFIG_SYS_ROMNAL 7 /rom/flash next access time /
6d0f6bcf JCPV	248	#define CONFIG_SYS_ROMFAL 11 /rom/flash access time /
c609719b	249
6d0f6bcf	250	#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
c609719b WD	251
c609719b WD	252	/* the following are for SDRAM only*/
6d0f6bcf JCPV	253	#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
	254	#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
	255	#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
	256	#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
	257	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	258	#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
	259	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
	260	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
c609719b	261	#if 0
6d0f6bcf	262	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
c609719b WD	263	#endif
c609719b WD	264
6d0f6bcf JCPV	265	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
	266	#define CONFIG_SYS_EXTROM 1
	267	#define CONFIG_SYS_REGDIMM 0
c609719b WD	268
	269
	270	/* memory bank settings*/
	271	/*
	272	* only bits 20-29 are actually used from these vales to set the
	273	* start/end address the upper two bits will be 0, and the lower 20
	274	* bits will be set to 0x00000 for a start address, or 0xfffff for an
	275	* end address
	276	*/
6d0f6bcf JCPV	277	#define CONFIG_SYS_BANK0_START 0x00000000
	278	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	279	#define CONFIG_SYS_BANK0_ENABLE 1
	280	#define CONFIG_SYS_BANK1_START 0x3ff00000
	281	#define CONFIG_SYS_BANK1_END 0x3fffffff
	282	#define CONFIG_SYS_BANK1_ENABLE 0
	283	#define CONFIG_SYS_BANK2_START 0x3ff00000
	284	#define CONFIG_SYS_BANK2_END 0x3fffffff
	285	#define CONFIG_SYS_BANK2_ENABLE 0
	286	#define CONFIG_SYS_BANK3_START 0x3ff00000
	287	#define CONFIG_SYS_BANK3_END 0x3fffffff
	288	#define CONFIG_SYS_BANK3_ENABLE 0
	289	#define CONFIG_SYS_BANK4_START 0x00000000
	290	#define CONFIG_SYS_BANK4_END 0x00000000
	291	#define CONFIG_SYS_BANK4_ENABLE 0
	292	#define CONFIG_SYS_BANK5_START 0x00000000
	293	#define CONFIG_SYS_BANK5_END 0x00000000
	294	#define CONFIG_SYS_BANK5_ENABLE 0
	295	#define CONFIG_SYS_BANK6_START 0x00000000
	296	#define CONFIG_SYS_BANK6_END 0x00000000
	297	#define CONFIG_SYS_BANK6_ENABLE 0
	298	#define CONFIG_SYS_BANK7_START 0x00000000
	299	#define CONFIG_SYS_BANK7_END 0x00000000
	300	#define CONFIG_SYS_BANK7_ENABLE 0
c609719b WD	301	/*
	302	* Memory bank enable bitmask, specifying which of the banks defined above
	303	are actually present. MSB is for bank #7, LSB is for bank #0.
	304	*/
6d0f6bcf	305	#define CONFIG_SYS_BANK_ENABLE 0x01
c609719b	306
6d0f6bcf	307	#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
c609719b	308	/* see 8240 book for bit definitions */
6d0f6bcf	309	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
c609719b WD	310	/* currently accessed page in memory */
	311	/* see 8240 book for details */
	312
	313	/* SDRAM 0 - 256MB */
6d0f6bcf JCPV	314	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	315	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b WD	316
	317	/* stack in DCACHE @ 1GB (no backing mem) */
	318	#if defined(USE_DINK32)
6d0f6bcf JCPV	319	#define CONFIG_SYS_IBAT1L (0x40000000 \| BATL_PP_00 )
6d0f6bcf JCPV	320	#define CONFIG_SYS_IBAT1U (0x40000000 \| BATU_BL_128K )
c609719b	321	#else
6d0f6bcf JCPV	322	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	323	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
c609719b WD	324	#endif
	325
	326	/* PCI memory */
6d0f6bcf JCPV	327	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	328	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b WD	329
c609719b WD	330	/* Flash, config addrs, etc */
6d0f6bcf JCPV	331	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	332	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	333
	334	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	335	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	336	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	337	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	338	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	339	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	340	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	341	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
c609719b WD	342
	343	/*
	344	* For booting Linux, the board info and command line data
	345	* have to be in the first 8 MB of memory, since this is
	346	* the maximum mapped by the Linux kernel during initialization.
	347	*/
6d0f6bcf	348	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	349	/*-----------------------------------------------------------------------
	350	* FLASH organization
	351	*/
6d0f6bcf JCPV	352	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	353	#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
c609719b	354
6d0f6bcf JCPV	355	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	356	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b WD	357
	358	/*-----------------------------------------------------------------------
	359	* Cache Configuration
	360	*/
6d0f6bcf	361	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
fe7f782d	362	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	363	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
c609719b WD	364	#endif
c609719b WD	365
c609719b WD	366	/* values according to the manual */
	367
	368	#define CONFIG_DRAM_50MHZ 1
	369	#define CONFIG_SDRAM_50MHZ
	370
	371	#undef NR_8259_INTS
	372	#define NR_8259_INTS 1
	373
	374
	375	#define CONFIG_DISK_SPINUP_TIME 1000000
	376
	377
	378	#endif /* __CONFIG_H */