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Commit | Line | Data |
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c609719b | 1 | /* |
414eec35 | 2 | * (C) Copyright 2001-2005 |
c609719b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | /* ------------------------------------------------------------------------- */ | |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
21 | ||
22 | #define CONFIG_MPC824X 1 | |
23 | #define CONFIG_MPC8245 1 | |
24 | #define CONFIG_SANDPOINT 1 | |
25 | ||
2ae18241 | 26 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
de550d6b | 27 | #define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" |
2ae18241 | 28 | |
c609719b WD |
29 | #if 0 |
30 | #define USE_DINK32 1 | |
31 | #else | |
32 | #undef USE_DINK32 | |
33 | #endif | |
34 | ||
35 | #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ | |
36 | #define CONFIG_BAUDRATE 9600 | |
37 | #define CONFIG_DRAM_SPEED 100 /* MHz */ | |
38 | ||
414eec35 WD |
39 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
40 | ||
c609719b | 41 | |
a1aa0bb5 JL |
42 | /* |
43 | * BOOTP options | |
44 | */ | |
45 | #define CONFIG_BOOTP_BOOTFILESIZE | |
46 | #define CONFIG_BOOTP_BOOTPATH | |
47 | #define CONFIG_BOOTP_GATEWAY | |
48 | #define CONFIG_BOOTP_HOSTNAME | |
49 | ||
50 | ||
fe7f782d JL |
51 | /* |
52 | * Command line configuration. | |
53 | */ | |
54 | #include <config_cmd_default.h> | |
55 | ||
56 | #define CONFIG_CMD_DHCP | |
57 | #define CONFIG_CMD_ELF | |
58 | #define CONFIG_CMD_I2C | |
59 | #define CONFIG_CMD_EEPROM | |
60 | #define CONFIG_CMD_NFS | |
61 | #define CONFIG_CMD_PCI | |
62 | #define CONFIG_CMD_SNTP | |
c609719b WD |
63 | |
64 | ||
65 | /* | |
66 | * Miscellaneous configurable options | |
67 | */ | |
6d0f6bcf JCPV |
68 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
69 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
70 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
71 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
72 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
73 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
74 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ | |
75 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
c609719b WD |
76 | |
77 | /*----------------------------------------------------------------------- | |
78 | * PCI stuff | |
79 | *----------------------------------------------------------------------- | |
80 | */ | |
81 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 82 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
c609719b WD |
83 | #undef CONFIG_PCI_PNP |
84 | ||
c609719b WD |
85 | |
86 | #define CONFIG_EEPRO100 | |
6d0f6bcf | 87 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
c609719b WD |
88 | #define CONFIG_NATSEMI |
89 | #define CONFIG_NS8382X | |
90 | ||
91 | #define PCI_ENET0_IOADDR 0x80000000 | |
92 | #define PCI_ENET0_MEMADDR 0x80000000 | |
93 | #define PCI_ENET1_IOADDR 0x81000000 | |
94 | #define PCI_ENET1_MEMADDR 0x81000000 | |
95 | ||
96 | ||
97 | /*----------------------------------------------------------------------- | |
98 | * Start addresses for the final memory configuration | |
99 | * (Set up by the startup code) | |
6d0f6bcf | 100 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 101 | */ |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
103 | #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 | |
c609719b | 104 | |
6d0f6bcf | 105 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
c609719b WD |
106 | |
107 | #if defined (USE_DINK32) | |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 |
109 | #define CONFIG_SYS_MONITOR_BASE 0x00090000 | |
110 | #define CONFIG_SYS_RAMBOOT 1 | |
111 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
553f0982 | 112 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 |
25ddd1fb | 113 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 114 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c609719b | 115 | #else |
6d0f6bcf JCPV |
116 | #undef CONFIG_SYS_RAMBOOT |
117 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 | |
14d0a02a | 118 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
c609719b | 119 | |
c609719b | 120 | |
6d0f6bcf | 121 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
553f0982 | 122 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
25ddd1fb | 123 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
c609719b WD |
124 | |
125 | #endif | |
126 | ||
6d0f6bcf | 127 | #define CONFIG_SYS_FLASH_BASE 0xFFF00000 |
c609719b | 128 | #if 0 |
6d0f6bcf | 129 | #define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ |
c609719b | 130 | #else |
6d0f6bcf | 131 | #define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ |
c609719b | 132 | #endif |
5a1aceb0 | 133 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
134 | #define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ |
135 | #define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ | |
c609719b | 136 | |
6d0f6bcf | 137 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ |
c609719b | 138 | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
140 | #define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ | |
c609719b | 141 | |
6d0f6bcf | 142 | #define CONFIG_SYS_EUMB_ADDR 0xFC000000 |
c609719b | 143 | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_ISA_MEM 0xFD000000 |
145 | #define CONFIG_SYS_ISA_IO 0xFE000000 | |
c609719b | 146 | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ |
148 | #define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 | |
c609719b WD |
149 | #define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ |
150 | #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ | |
151 | ||
152 | /* | |
153 | * select i2c support configuration | |
154 | * | |
155 | * Supported configurations are {none, software, hardware} drivers. | |
156 | * If the software driver is chosen, there are some additional | |
157 | * configuration items that the driver uses to drive the port pins. | |
158 | */ | |
159 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
160 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
162 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
c609719b WD |
163 | |
164 | #ifdef CONFIG_SOFT_I2C | |
165 | #error "Soft I2C is not configured properly. Please review!" | |
166 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
167 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
168 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
169 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
170 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
171 | else iop->pdat &= ~0x00010000 | |
172 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
173 | else iop->pdat &= ~0x00020000 | |
174 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
175 | #endif /* CONFIG_SOFT_I2C */ | |
176 | ||
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ |
178 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
179 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
180 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
c609719b | 181 | |
6d0f6bcf | 182 | #define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } |
c609719b WD |
183 | |
184 | /*----------------------------------------------------------------------- | |
185 | * Definitions for initial stack pointer and data area (in DPRAM) | |
186 | */ | |
187 | ||
188 | ||
57d6c589 | 189 | /* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ |
191 | #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ | |
192 | #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ | |
c609719b | 193 | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
195 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
c609719b WD |
196 | |
197 | /* | |
198 | * NS87308 Configuration | |
199 | */ | |
55d6d2d3 | 200 | #define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ |
c609719b | 201 | |
6d0f6bcf | 202 | #define CONFIG_SYS_NS87308_BADDR_10 1 |
c609719b | 203 | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ |
205 | CONFIG_SYS_NS87308_UART2 | \ | |
206 | CONFIG_SYS_NS87308_POWRMAN | \ | |
207 | CONFIG_SYS_NS87308_RTC_APC ) | |
c609719b | 208 | |
6d0f6bcf | 209 | #undef CONFIG_SYS_NS87308_PS2MOD |
c609719b | 210 | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_NS87308_CS0_BASE 0x0076 |
212 | #define CONFIG_SYS_NS87308_CS0_CONF 0x30 | |
213 | #define CONFIG_SYS_NS87308_CS1_BASE 0x0075 | |
214 | #define CONFIG_SYS_NS87308_CS1_CONF 0x30 | |
215 | #define CONFIG_SYS_NS87308_CS2_BASE 0x0074 | |
216 | #define CONFIG_SYS_NS87308_CS2_CONF 0x30 | |
c609719b WD |
217 | |
218 | /* | |
219 | * NS16550 Configuration | |
220 | */ | |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_NS16550 |
222 | #define CONFIG_SYS_NS16550_SERIAL | |
c609719b | 223 | |
6d0f6bcf | 224 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
c609719b | 225 | |
f832d8a1 | 226 | #if (CONFIG_CONS_INDEX > 2) |
6d0f6bcf | 227 | #define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000 |
f832d8a1 | 228 | #else |
6d0f6bcf | 229 | #define CONFIG_SYS_NS16550_CLK 1843200 |
f832d8a1 | 230 | #endif |
49822e23 | 231 | |
6d0f6bcf JCPV |
232 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) |
233 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) | |
234 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500) | |
235 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600) | |
c609719b WD |
236 | |
237 | /* | |
238 | * Low Level Configuration Settings | |
239 | * (address mappings, register initial values, etc.) | |
240 | * You should know what you are doing if you make changes here. | |
241 | */ | |
242 | ||
243 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
244 | ||
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ |
246 | #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ | |
c609719b | 247 | |
6d0f6bcf | 248 | #define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ |
c609719b WD |
249 | |
250 | /* the following are for SDRAM only*/ | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ |
252 | #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ | |
253 | #define CONFIG_SYS_RDLAT 4 /* data latency from read command */ | |
254 | #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ | |
255 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ | |
256 | #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ | |
257 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ | |
258 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ | |
c609719b | 259 | #if 0 |
6d0f6bcf | 260 | #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ |
c609719b WD |
261 | #endif |
262 | ||
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 |
264 | #define CONFIG_SYS_EXTROM 1 | |
265 | #define CONFIG_SYS_REGDIMM 0 | |
c609719b WD |
266 | |
267 | ||
268 | /* memory bank settings*/ | |
269 | /* | |
270 | * only bits 20-29 are actually used from these vales to set the | |
271 | * start/end address the upper two bits will be 0, and the lower 20 | |
272 | * bits will be set to 0x00000 for a start address, or 0xfffff for an | |
273 | * end address | |
274 | */ | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_BANK0_START 0x00000000 |
276 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
277 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
278 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
279 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
280 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
281 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
282 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
283 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
284 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
285 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
286 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
287 | #define CONFIG_SYS_BANK4_START 0x00000000 | |
288 | #define CONFIG_SYS_BANK4_END 0x00000000 | |
289 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
290 | #define CONFIG_SYS_BANK5_START 0x00000000 | |
291 | #define CONFIG_SYS_BANK5_END 0x00000000 | |
292 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
293 | #define CONFIG_SYS_BANK6_START 0x00000000 | |
294 | #define CONFIG_SYS_BANK6_END 0x00000000 | |
295 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
296 | #define CONFIG_SYS_BANK7_START 0x00000000 | |
297 | #define CONFIG_SYS_BANK7_END 0x00000000 | |
298 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
c609719b WD |
299 | /* |
300 | * Memory bank enable bitmask, specifying which of the banks defined above | |
301 | are actually present. MSB is for bank #7, LSB is for bank #0. | |
302 | */ | |
6d0f6bcf | 303 | #define CONFIG_SYS_BANK_ENABLE 0x01 |
c609719b | 304 | |
6d0f6bcf | 305 | #define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ |
c609719b | 306 | /* see 8240 book for bit definitions */ |
6d0f6bcf | 307 | #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ |
c609719b WD |
308 | /* currently accessed page in memory */ |
309 | /* see 8240 book for details */ | |
310 | ||
311 | /* SDRAM 0 - 256MB */ | |
6d0f6bcf JCPV |
312 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
313 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
c609719b WD |
314 | |
315 | /* stack in DCACHE @ 1GB (no backing mem) */ | |
316 | #if defined(USE_DINK32) | |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) |
318 | #define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) | |
c609719b | 319 | #else |
6d0f6bcf JCPV |
320 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) |
321 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
c609719b WD |
322 | #endif |
323 | ||
324 | /* PCI memory */ | |
6d0f6bcf JCPV |
325 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
326 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
c609719b WD |
327 | |
328 | /* Flash, config addrs, etc */ | |
6d0f6bcf JCPV |
329 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
330 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
331 | ||
332 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
333 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
334 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
335 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
336 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
337 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
338 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
339 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
c609719b WD |
340 | |
341 | /* | |
342 | * For booting Linux, the board info and command line data | |
343 | * have to be in the first 8 MB of memory, since this is | |
344 | * the maximum mapped by the Linux kernel during initialization. | |
345 | */ | |
6d0f6bcf | 346 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
347 | /*----------------------------------------------------------------------- |
348 | * FLASH organization | |
349 | */ | |
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
351 | #define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ | |
c609719b | 352 | |
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
354 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b WD |
355 | |
356 | /*----------------------------------------------------------------------- | |
357 | * Cache Configuration | |
358 | */ | |
6d0f6bcf | 359 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ |
fe7f782d | 360 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 361 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
c609719b WD |
362 | #endif |
363 | ||
c609719b WD |
364 | /* values according to the manual */ |
365 | ||
366 | #define CONFIG_DRAM_50MHZ 1 | |
367 | #define CONFIG_SDRAM_50MHZ | |
368 | ||
369 | #undef NR_8259_INTS | |
370 | #define NR_8259_INTS 1 | |
371 | ||
372 | ||
373 | #define CONFIG_DISK_SPINUP_TIME 1000000 | |
374 | ||
375 | ||
376 | #endif /* __CONFIG_H */ |