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062ef1a6 PJ |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #ifndef __CONFIG_H | |
24 | #define __CONFIG_H | |
25 | ||
26 | /* | |
27 | * T1040 RDB board configuration file | |
28 | */ | |
29 | #define CONFIG_T104xRDB | |
30 | #define CONFIG_T1040RDB | |
31 | #define CONFIG_PHYS_64BIT | |
32 | ||
33 | #ifdef CONFIG_RAMBOOT_PBL | |
34 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
35 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
36 | #endif | |
37 | ||
38 | /* High Level Configuration Options */ | |
39 | #define CONFIG_BOOKE | |
40 | #define CONFIG_E500 /* BOOKE e500 family */ | |
41 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
42 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
43 | #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ | |
44 | #define CONFIG_MP /* support multiple processors */ | |
45 | ||
46 | #ifndef CONFIG_SYS_TEXT_BASE | |
47 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
48 | #endif | |
49 | ||
50 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
51 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
52 | #endif | |
53 | ||
54 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
55 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
56 | #define CONFIG_FSL_IFC /* Enable IFC Support */ | |
57 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
58 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
59 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
60 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
61 | #define CONFIG_PCIE3 /* PCIE controler 3 */ | |
62 | #define CONFIG_PCIE4 /* PCIE controler 4 */ | |
63 | ||
64 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
65 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
66 | ||
67 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
68 | ||
69 | #define CONFIG_ENV_OVERWRITE | |
70 | ||
71 | #ifdef CONFIG_SYS_NO_FLASH | |
72 | #define CONFIG_ENV_IS_NOWHERE | |
73 | #else | |
74 | #define CONFIG_FLASH_CFI_DRIVER | |
75 | #define CONFIG_SYS_FLASH_CFI | |
76 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
77 | #endif | |
78 | ||
79 | #ifndef CONFIG_SYS_NO_FLASH | |
80 | #if defined(CONFIG_SPIFLASH) | |
81 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
82 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
83 | #define CONFIG_ENV_SPI_BUS 0 | |
84 | #define CONFIG_ENV_SPI_CS 0 | |
85 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
86 | #define CONFIG_ENV_SPI_MODE 0 | |
87 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
88 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
89 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
90 | #elif defined(CONFIG_SDCARD) | |
91 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
92 | #define CONFIG_ENV_IS_IN_MMC | |
93 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
94 | #define CONFIG_ENV_SIZE 0x2000 | |
95 | #define CONFIG_ENV_OFFSET (512 * 1105) | |
96 | #elif defined(CONFIG_NAND) | |
97 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
98 | #define CONFIG_ENV_IS_IN_NAND | |
99 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
100 | #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
101 | #else | |
102 | #define CONFIG_ENV_IS_IN_FLASH | |
103 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
104 | #define CONFIG_ENV_SIZE 0x2000 | |
105 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
106 | #endif | |
107 | #else /* CONFIG_SYS_NO_FLASH */ | |
108 | #define CONFIG_ENV_SIZE 0x2000 | |
109 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
110 | #endif | |
111 | ||
112 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
113 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
114 | ||
115 | /* | |
116 | * These can be toggled for performance analysis, otherwise use default. | |
117 | */ | |
118 | #define CONFIG_SYS_CACHE_STASHING | |
119 | #define CONFIG_BACKSIDE_L2_CACHE | |
120 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
121 | #define CONFIG_BTB /* toggle branch predition */ | |
122 | #define CONFIG_DDR_ECC | |
123 | #ifdef CONFIG_DDR_ECC | |
124 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
125 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
126 | #endif | |
127 | ||
128 | #define CONFIG_ENABLE_36BIT_PHYS | |
129 | ||
130 | #define CONFIG_ADDR_MAP | |
131 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
132 | ||
133 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
134 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
135 | #define CONFIG_SYS_ALT_MEMTEST | |
136 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
137 | ||
138 | /* | |
139 | * Config the L3 Cache as L3 SRAM | |
140 | */ | |
141 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 | |
142 | ||
143 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
144 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
145 | ||
146 | /* | |
147 | * DDR Setup | |
148 | */ | |
149 | #define CONFIG_VERY_BIG_RAM | |
150 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
151 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
152 | ||
153 | /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ | |
154 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
155 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
156 | ||
157 | #define CONFIG_DDR_SPD | |
158 | #define CONFIG_SYS_DDR_RAW_TIMING | |
5614e71b | 159 | #define CONFIG_SYS_FSL_DDR3 |
062ef1a6 PJ |
160 | |
161 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
162 | #define SPD_EEPROM_ADDRESS 0x51 | |
163 | ||
164 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
165 | ||
166 | /* | |
167 | * IFC Definitions | |
168 | */ | |
169 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 | |
170 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
171 | ||
172 | #define CONFIG_SYS_NOR_CSPR_EXT (0xf) | |
173 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ | |
174 | CSPR_PORT_SIZE_16 | \ | |
175 | CSPR_MSEL_NOR | \ | |
176 | CSPR_V) | |
177 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
178 | /* NOR Flash Timing Params */ | |
179 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
180 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
181 | FTIM0_NOR_TEADC(0x5) | \ | |
182 | FTIM0_NOR_TEAHC(0x5)) | |
183 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
184 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
185 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
186 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
187 | FTIM2_NOR_TCH(0x4) | \ | |
188 | FTIM2_NOR_TWPH(0x0E) | \ | |
189 | FTIM2_NOR_TWP(0x1c)) | |
190 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
191 | ||
192 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
193 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
194 | ||
195 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
196 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
197 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
198 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
199 | ||
200 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
201 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
202 | ||
203 | /* CPLD on IFC */ | |
204 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 | |
205 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
206 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | |
207 | | CSPR_PORT_SIZE_8 \ | |
208 | | CSPR_MSEL_GPCM \ | |
209 | | CSPR_V) | |
210 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
211 | #define CONFIG_SYS_CSOR2 0x0 | |
212 | /* CPLD Timing parameters for IFC CS2 */ | |
213 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
214 | FTIM0_GPCM_TEADC(0x0e) | \ | |
215 | FTIM0_GPCM_TEAHC(0x0e)) | |
216 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
217 | FTIM1_GPCM_TRAD(0x1f)) | |
218 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
219 | FTIM2_GPCM_TCH(0x0) | \ | |
220 | FTIM2_GPCM_TWP(0x1f)) | |
221 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
222 | ||
223 | /* NAND Flash on IFC */ | |
224 | #define CONFIG_NAND_FSL_IFC | |
225 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
226 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
227 | ||
228 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
229 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
230 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
231 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
232 | | CSPR_V) | |
233 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
234 | ||
235 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
236 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
237 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
238 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
239 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
240 | | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ | |
241 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
242 | ||
243 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
244 | ||
245 | /* ONFI NAND Flash mode0 Timing Params */ | |
246 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
247 | FTIM0_NAND_TWP(0x18) | \ | |
248 | FTIM0_NAND_TWCHT(0x07) | \ | |
249 | FTIM0_NAND_TWH(0x0a)) | |
250 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
251 | FTIM1_NAND_TWBE(0x39) | \ | |
252 | FTIM1_NAND_TRR(0x0e) | \ | |
253 | FTIM1_NAND_TRP(0x18)) | |
254 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
255 | FTIM2_NAND_TREH(0x0a) | \ | |
256 | FTIM2_NAND_TWHRE(0x1e)) | |
257 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
258 | ||
259 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
260 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
261 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
262 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
263 | #define CONFIG_CMD_NAND | |
264 | ||
265 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
266 | ||
267 | #if defined(CONFIG_NAND) | |
268 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
269 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
270 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
271 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
272 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
273 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
274 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
275 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
276 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT | |
277 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
278 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
279 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
280 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
281 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
282 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
283 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
284 | #else | |
285 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT | |
286 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR | |
287 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
288 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
289 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
290 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
291 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
292 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
293 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
294 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
295 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
296 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
297 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
298 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
299 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
300 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
301 | #endif | |
302 | ||
303 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
304 | ||
305 | #if defined(CONFIG_RAMBOOT_PBL) | |
306 | #define CONFIG_SYS_RAMBOOT | |
307 | #endif | |
308 | ||
309 | #define CONFIG_BOARD_EARLY_INIT_R | |
310 | #define CONFIG_MISC_INIT_R | |
311 | ||
312 | #define CONFIG_HWCONFIG | |
313 | ||
314 | /* define to use L1 as initial stack */ | |
315 | #define CONFIG_L1_INIT_RAM | |
316 | #define CONFIG_SYS_INIT_RAM_LOCK | |
317 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
318 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
319 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 | |
320 | /* The assembler doesn't like typecast */ | |
321 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
322 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
323 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
324 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
325 | ||
326 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
327 | GENERATED_GBL_DATA_SIZE) | |
328 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
329 | ||
330 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
331 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
332 | ||
333 | /* Serial Port - controlled on board with jumper J8 | |
334 | * open - index 2 | |
335 | * shorted - index 1 | |
336 | */ | |
337 | #define CONFIG_CONS_INDEX 1 | |
338 | #define CONFIG_SYS_NS16550 | |
339 | #define CONFIG_SYS_NS16550_SERIAL | |
340 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
341 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
342 | ||
343 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
344 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
345 | ||
346 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
347 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
348 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
349 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
350 | #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ | |
351 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ | |
352 | ||
353 | /* Use the HUSH parser */ | |
354 | #define CONFIG_SYS_HUSH_PARSER | |
355 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
356 | ||
357 | /* pass open firmware flat tree */ | |
358 | #define CONFIG_OF_LIBFDT | |
359 | #define CONFIG_OF_BOARD_SETUP | |
360 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
361 | ||
362 | /* new uImage format support */ | |
363 | #define CONFIG_FIT | |
364 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
365 | ||
366 | /* I2C */ | |
367 | #define CONFIG_SYS_I2C | |
368 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
369 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ | |
370 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
371 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ | |
372 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
373 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
374 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 | |
375 | ||
376 | /* I2C bus multiplexer */ | |
377 | #define I2C_MUX_PCA_ADDR 0x70 | |
378 | #define I2C_MUX_CH_DEFAULT 0x8 | |
379 | ||
380 | ||
381 | /* | |
382 | * eSPI - Enhanced SPI | |
383 | */ | |
384 | #define CONFIG_FSL_ESPI | |
385 | #define CONFIG_SPI_FLASH | |
386 | #define CONFIG_SPI_FLASH_STMICRO | |
387 | #define CONFIG_CMD_SF | |
388 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
389 | #define CONFIG_SF_DEFAULT_MODE 0 | |
390 | ||
391 | /* | |
392 | * General PCI | |
393 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
394 | */ | |
395 | ||
396 | #ifdef CONFIG_PCI | |
397 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
398 | #ifdef CONFIG_PCIE1 | |
399 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
400 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
401 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
402 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
403 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
404 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
405 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
406 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
407 | #endif | |
408 | ||
409 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
410 | #ifdef CONFIG_PCIE2 | |
411 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 | |
412 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
413 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull | |
414 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
415 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
416 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
417 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
418 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
419 | #endif | |
420 | ||
421 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
422 | #ifdef CONFIG_PCIE3 | |
423 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
424 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
425 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
426 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
427 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
428 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
429 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
430 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
431 | #endif | |
432 | ||
433 | /* controller 4, Base address 203000 */ | |
434 | #ifdef CONFIG_PCIE4 | |
435 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 | |
436 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
437 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull | |
438 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
439 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 | |
440 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
441 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
442 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
443 | #endif | |
444 | ||
445 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
446 | #define CONFIG_E1000 | |
447 | ||
448 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
449 | #define CONFIG_DOS_PARTITION | |
450 | #endif /* CONFIG_PCI */ | |
451 | ||
452 | /* SATA */ | |
453 | #define CONFIG_FSL_SATA_V2 | |
454 | #ifdef CONFIG_FSL_SATA_V2 | |
455 | #define CONFIG_LIBATA | |
456 | #define CONFIG_FSL_SATA | |
457 | ||
458 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
459 | #define CONFIG_SATA1 | |
460 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
461 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
462 | ||
463 | #define CONFIG_LBA48 | |
464 | #define CONFIG_CMD_SATA | |
465 | #define CONFIG_DOS_PARTITION | |
466 | #define CONFIG_CMD_EXT2 | |
467 | #endif | |
468 | ||
469 | /* | |
470 | * USB | |
471 | */ | |
472 | #define CONFIG_HAS_FSL_DR_USB | |
473 | ||
474 | #ifdef CONFIG_HAS_FSL_DR_USB | |
475 | #define CONFIG_USB_EHCI | |
476 | ||
477 | #ifdef CONFIG_USB_EHCI | |
478 | #define CONFIG_CMD_USB | |
479 | #define CONFIG_USB_STORAGE | |
480 | #define CONFIG_USB_EHCI_FSL | |
481 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
482 | #define CONFIG_CMD_EXT2 | |
483 | #endif | |
484 | #endif | |
485 | ||
486 | #define CONFIG_MMC | |
487 | ||
488 | #ifdef CONFIG_MMC | |
489 | #define CONFIG_FSL_ESDHC | |
490 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
491 | #define CONFIG_CMD_MMC | |
492 | #define CONFIG_GENERIC_MMC | |
493 | #define CONFIG_CMD_EXT2 | |
494 | #define CONFIG_CMD_FAT | |
495 | #define CONFIG_DOS_PARTITION | |
496 | #endif | |
497 | ||
498 | /* Qman/Bman */ | |
499 | #ifndef CONFIG_NOBQFMAN | |
500 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
501 | #define CONFIG_SYS_BMAN_NUM_PORTALS 25 | |
502 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
503 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
504 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
505 | #define CONFIG_SYS_QMAN_NUM_PORTALS 25 | |
506 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
507 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
508 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
509 | ||
510 | #define CONFIG_SYS_DPAA_FMAN | |
511 | #define CONFIG_SYS_DPAA_PME | |
512 | ||
513 | /* Default address of microcode for the Linux Fman driver */ | |
514 | #if defined(CONFIG_SPIFLASH) | |
515 | /* | |
516 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
517 | * env, so we got 0x110000. | |
518 | */ | |
519 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
520 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 | |
521 | #elif defined(CONFIG_SDCARD) | |
522 | /* | |
523 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
524 | * about 545KB (1089 blocks), Env is stored after the image, and the env size is | |
525 | * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. | |
526 | */ | |
527 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
528 | #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) | |
529 | #elif defined(CONFIG_NAND) | |
530 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
531 | #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
532 | #else | |
533 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
534 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 | |
535 | #endif | |
536 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
537 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
538 | #endif /* CONFIG_NOBQFMAN */ | |
539 | ||
540 | #ifdef CONFIG_SYS_DPAA_FMAN | |
541 | #define CONFIG_FMAN_ENET | |
542 | #define CONFIG_PHY_VITESSE | |
543 | #define CONFIG_PHY_REALTEK | |
544 | #endif | |
545 | ||
546 | #ifdef CONFIG_FMAN_ENET | |
547 | #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c | |
548 | #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d | |
549 | #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e | |
550 | #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f | |
551 | ||
552 | #define CONFIG_MII /* MII PHY management */ | |
553 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
554 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
555 | #endif | |
556 | ||
557 | /* | |
558 | * Environment | |
559 | */ | |
560 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
561 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
562 | ||
563 | /* | |
564 | * Command line configuration. | |
565 | */ | |
566 | #include <config_cmd_default.h> | |
567 | ||
568 | #define CONFIG_CMD_DHCP | |
569 | #define CONFIG_CMD_ELF | |
570 | #define CONFIG_CMD_ERRATA | |
571 | #define CONFIG_CMD_GREPENV | |
572 | #define CONFIG_CMD_IRQ | |
573 | #define CONFIG_CMD_I2C | |
574 | #define CONFIG_CMD_MII | |
575 | #define CONFIG_CMD_PING | |
576 | #define CONFIG_CMD_REGINFO | |
577 | #define CONFIG_CMD_SETEXPR | |
578 | ||
579 | #ifdef CONFIG_PCI | |
580 | #define CONFIG_CMD_PCI | |
581 | #define CONFIG_CMD_NET | |
582 | #endif | |
583 | ||
584 | /* | |
585 | * Miscellaneous configurable options | |
586 | */ | |
587 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
588 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
589 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
590 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
591 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
592 | #ifdef CONFIG_CMD_KGDB | |
593 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
594 | #else | |
595 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
596 | #endif | |
597 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
598 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
599 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
600 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ | |
601 | ||
602 | /* | |
603 | * For booting Linux, the board info and command line data | |
604 | * have to be in the first 64 MB of memory, since this is | |
605 | * the maximum mapped by the Linux kernel during initialization. | |
606 | */ | |
607 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
608 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
609 | ||
610 | #ifdef CONFIG_CMD_KGDB | |
611 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
062ef1a6 PJ |
612 | #endif |
613 | ||
614 | /* | |
615 | * Environment Configuration | |
616 | */ | |
617 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
618 | #define CONFIG_BOOTFILE "uImage" | |
619 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
620 | ||
621 | /* default location for tftp and bootm */ | |
622 | #define CONFIG_LOADADDR 1000000 | |
623 | ||
624 | #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ | |
625 | ||
626 | #define CONFIG_BAUDRATE 115200 | |
627 | ||
628 | #define __USB_PHY_TYPE utmi | |
629 | ||
630 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
631 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ | |
632 | "bank_intlv=cs0_cs1;" \ | |
633 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
634 | "netdev=eth0\0" \ | |
635 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
636 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
637 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
638 | "protect off $ubootaddr +$filesize && " \ | |
639 | "erase $ubootaddr +$filesize && " \ | |
640 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
641 | "protect on $ubootaddr +$filesize && " \ | |
642 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
643 | "consoledev=ttyS0\0" \ | |
644 | "ramdiskaddr=2000000\0" \ | |
645 | "ramdiskfile=t1040rdb/ramdisk.uboot\0" \ | |
646 | "fdtaddr=c00000\0" \ | |
647 | "fdtfile=t1040rdb/t1040rdb.dtb\0" \ | |
648 | "bdev=sda3\0" \ | |
649 | "c=ffe\0" | |
650 | ||
651 | #define CONFIG_LINUX \ | |
652 | "setenv bootargs root=/dev/ram rw " \ | |
653 | "console=$consoledev,$baudrate $othbootargs;" \ | |
654 | "setenv ramdiskaddr 0x02000000;" \ | |
655 | "setenv fdtaddr 0x00c00000;" \ | |
656 | "setenv loadaddr 0x1000000;" \ | |
657 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
658 | ||
659 | #define CONFIG_HDBOOT \ | |
660 | "setenv bootargs root=/dev/$bdev rw " \ | |
661 | "console=$consoledev,$baudrate $othbootargs;" \ | |
662 | "tftp $loadaddr $bootfile;" \ | |
663 | "tftp $fdtaddr $fdtfile;" \ | |
664 | "bootm $loadaddr - $fdtaddr" | |
665 | ||
666 | #define CONFIG_NFSBOOTCOMMAND \ | |
667 | "setenv bootargs root=/dev/nfs rw " \ | |
668 | "nfsroot=$serverip:$rootpath " \ | |
669 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
670 | "console=$consoledev,$baudrate $othbootargs;" \ | |
671 | "tftp $loadaddr $bootfile;" \ | |
672 | "tftp $fdtaddr $fdtfile;" \ | |
673 | "bootm $loadaddr - $fdtaddr" | |
674 | ||
675 | #define CONFIG_RAMBOOTCOMMAND \ | |
676 | "setenv bootargs root=/dev/ram rw " \ | |
677 | "console=$consoledev,$baudrate $othbootargs;" \ | |
678 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
679 | "tftp $loadaddr $bootfile;" \ | |
680 | "tftp $fdtaddr $fdtfile;" \ | |
681 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
682 | ||
683 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
684 | ||
685 | #ifdef CONFIG_SECURE_BOOT | |
686 | #include <asm/fsl_secure_boot.h> | |
687 | #endif | |
688 | ||
689 | #endif /* __CONFIG_H */ |