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efc6f447 GL |
1 | /* |
2 | * (C) Copyright 2000-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
28 | * board/config.h - configuration options, board specific | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
34 | /* | |
35 | * High Level Configuration Options | |
36 | * (easy to change) | |
37 | */ | |
38 | ||
39 | #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ | |
40 | #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ | |
41 | #define CONFIG_TK885D 1 /* ...in a TK885D base board */ | |
42 | ||
43 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ | |
44 | #define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ | |
45 | #define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ | |
46 | #define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ | |
47 | /* (it will be used if there is no */ | |
48 | /* 'cpuclk' variable with valid value) */ | |
49 | ||
50 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
51 | ||
52 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
53 | ||
54 | #define CONFIG_BOOTCOUNT_LIMIT | |
55 | ||
56 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
57 | ||
58 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
59 | ||
60 | #define CONFIG_PREBOOT "echo;" \ | |
61 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
62 | "echo" | |
63 | ||
64 | #undef CONFIG_BOOTARGS | |
65 | ||
66 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
2b4f778f WD |
67 | "ethprime=FEC ETHERNET\0" \ |
68 | "ethact=FEC ETHERNET\0" \ | |
efc6f447 GL |
69 | "netdev=eth0\0" \ |
70 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
71 | "nfsroot=${serverip}:${rootpath}\0" \ | |
72 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
73 | "addip=setenv bootargs ${bootargs} " \ | |
74 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
75 | ":${hostname}:${netdev}:off panic=1\0" \ | |
76 | "flash_nfs=run nfsargs addip;" \ | |
77 | "bootm ${kernel_addr}\0" \ | |
78 | "flash_self=run ramargs addip;" \ | |
79 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
80 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
81 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
2b4f778f WD |
82 | "bootfile=/tftpboot/tk885d/uImage\0" \ |
83 | "u-boot=/tftpboot/tk885d/u-boot.bin\0" \ | |
efc6f447 GL |
84 | "kernel_addr=40080000\0" \ |
85 | "ramdisk_addr=40180000\0" \ | |
86 | "load=tftp 200000 ${u-boot}\0" \ | |
87 | "update=protect off 40000000 +${filesize};" \ | |
88 | "erase 40000000 +${filesize};" \ | |
89 | "cp.b 200000 40000000 ${filesize};" \ | |
90 | "protect on 40000000 +${filesize}\0" \ | |
91 | "" | |
92 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
93 | ||
94 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
95 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
96 | ||
97 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
98 | ||
99 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
100 | ||
101 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
102 | ||
103 | /* enable I2C and select the hardware/software driver */ | |
104 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
105 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
106 | ||
107 | #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ | |
108 | #define CFG_I2C_SLAVE 0xFE | |
109 | ||
110 | #ifdef CONFIG_SOFT_I2C | |
111 | /* | |
112 | * Software (bit-bang) I2C driver configuration | |
113 | */ | |
114 | #define PB_SCL 0x00000020 /* PB 26 */ | |
115 | #define PB_SDA 0x00000010 /* PB 27 */ | |
116 | ||
117 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
118 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
119 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
120 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
121 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
122 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
123 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
124 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
125 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ | |
126 | #endif /* CONFIG_SOFT_I2C */ | |
127 | ||
128 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ | |
129 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
130 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 | |
131 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
132 | ||
133 | # define CONFIG_RTC_DS1337 1 | |
134 | # define CFG_I2C_RTC_ADDR 0x68 | |
135 | ||
136 | /* | |
137 | * BOOTP options | |
138 | */ | |
139 | #define CONFIG_BOOTP_SUBNETMASK | |
140 | #define CONFIG_BOOTP_GATEWAY | |
141 | #define CONFIG_BOOTP_HOSTNAME | |
142 | #define CONFIG_BOOTP_BOOTPATH | |
143 | #define CONFIG_BOOTP_BOOTFILESIZE | |
144 | ||
145 | ||
146 | #define CONFIG_MAC_PARTITION | |
147 | #define CONFIG_DOS_PARTITION | |
148 | ||
149 | #undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ | |
150 | ||
151 | #define CONFIG_TIMESTAMP /* but print image timestmps */ | |
152 | ||
153 | ||
154 | /* | |
155 | * Command line configuration. | |
156 | */ | |
157 | #include <config_cmd_default.h> | |
158 | ||
159 | #define CONFIG_CMD_ASKENV | |
160 | #define CONFIG_CMD_DATE | |
161 | #define CONFIG_CMD_DHCP | |
162 | #define CONFIG_CMD_EEPROM | |
163 | #define CONFIG_CMD_I2C | |
164 | #define CONFIG_CMD_IDE | |
165 | #define CONFIG_CMD_MII | |
166 | #define CONFIG_CMD_NFS | |
167 | #define CONFIG_CMD_PING | |
168 | ||
169 | ||
170 | /* | |
171 | * Miscellaneous configurable options | |
172 | */ | |
173 | #define CFG_LONGHELP /* undef to save memory */ | |
174 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
175 | ||
176 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
177 | #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ | |
178 | #ifdef CFG_HUSH_PARSER | |
179 | #define CFG_PROMPT_HUSH_PS2 "> " | |
180 | #endif | |
181 | ||
182 | #if defined(CONFIG_CMD_KGDB) | |
183 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
184 | #else | |
185 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
186 | #endif | |
187 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
188 | #define CFG_MAXARGS 16 /* max number of command args */ | |
189 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
190 | ||
191 | #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ | |
192 | #define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ | |
193 | #define CFG_ALT_MEMTEST /* alternate, more extensive | |
194 | memory test.*/ | |
195 | ||
196 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
197 | ||
198 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
199 | ||
200 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
201 | ||
202 | /* | |
203 | * Enable loopw command. | |
204 | */ | |
205 | #define CONFIG_LOOPW | |
206 | ||
207 | /* | |
208 | * Low Level Configuration Settings | |
209 | * (address mappings, register initial values, etc.) | |
210 | * You should know what you are doing if you make changes here. | |
211 | */ | |
212 | /*----------------------------------------------------------------------- | |
213 | * Internal Memory Mapped Register | |
214 | */ | |
215 | #define CFG_IMMR 0xFFF00000 | |
216 | ||
217 | /*----------------------------------------------------------------------- | |
218 | * Definitions for initial stack pointer and data area (in DPRAM) | |
219 | */ | |
220 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
221 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
222 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
223 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
224 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
225 | ||
226 | /*----------------------------------------------------------------------- | |
227 | * Start addresses for the final memory configuration | |
228 | * (Set up by the startup code) | |
229 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
230 | */ | |
231 | #define CFG_SDRAM_BASE 0x00000000 | |
232 | #define CFG_FLASH_BASE 0x40000000 | |
233 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
234 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
235 | #define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ | |
236 | ||
237 | /* | |
238 | * For booting Linux, the board info and command line data | |
239 | * have to be in the first 8 MB of memory, since this is | |
240 | * the maximum mapped by the Linux kernel during initialization. | |
241 | */ | |
242 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
243 | ||
244 | /*----------------------------------------------------------------------- | |
245 | * FLASH organization | |
246 | */ | |
247 | ||
248 | /* use CFI flash driver */ | |
249 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ | |
250 | #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
251 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } | |
252 | #define CFG_FLASH_EMPTY_INFO | |
253 | #define CFG_FLASH_USE_BUFFER_WRITE 1 | |
254 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
255 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
256 | ||
257 | #define CFG_ENV_IS_IN_FLASH 1 | |
258 | #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ | |
259 | #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ | |
2b4f778f | 260 | #define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ |
efc6f447 GL |
261 | |
262 | /* Address and size of Redundant Environment Sector */ | |
263 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) | |
264 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
265 | ||
266 | /*----------------------------------------------------------------------- | |
267 | * Hardware Information Block | |
268 | */ | |
269 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
270 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
271 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
272 | ||
273 | /*----------------------------------------------------------------------- | |
274 | * Cache Configuration | |
275 | */ | |
276 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
277 | #if defined(CONFIG_CMD_KGDB) | |
278 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
279 | #endif | |
280 | ||
281 | /*----------------------------------------------------------------------- | |
282 | * SYPCR - System Protection Control 11-9 | |
283 | * SYPCR can only be written once after reset! | |
284 | *----------------------------------------------------------------------- | |
285 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
286 | */ | |
287 | #if defined(CONFIG_WATCHDOG) | |
288 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
289 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
290 | #else | |
291 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
292 | #endif | |
293 | ||
294 | /*----------------------------------------------------------------------- | |
295 | * SIUMCR - SIU Module Configuration 11-6 | |
296 | *----------------------------------------------------------------------- | |
297 | * PCMCIA config., multi-function pin tri-state | |
298 | */ | |
299 | #ifndef CONFIG_CAN_DRIVER | |
300 | #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
301 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
302 | #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
303 | #endif /* CONFIG_CAN_DRIVER */ | |
304 | ||
305 | /*----------------------------------------------------------------------- | |
306 | * TBSCR - Time Base Status and Control 11-26 | |
307 | *----------------------------------------------------------------------- | |
308 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
309 | */ | |
310 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
311 | ||
312 | /*----------------------------------------------------------------------- | |
313 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
314 | *----------------------------------------------------------------------- | |
315 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
316 | */ | |
317 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
318 | ||
319 | /*----------------------------------------------------------------------- | |
320 | * SCCR - System Clock and reset Control Register 15-27 | |
321 | *----------------------------------------------------------------------- | |
322 | * Set clock output, timebase and RTC source and divider, | |
323 | * power management and some other internal clocks | |
324 | */ | |
325 | #define SCCR_MASK SCCR_EBDF11 | |
326 | #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
327 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
328 | SCCR_DFALCD00) | |
329 | ||
330 | /*----------------------------------------------------------------------- | |
331 | * PCMCIA stuff | |
332 | *----------------------------------------------------------------------- | |
333 | * | |
334 | */ | |
335 | #define CFG_PCMCIA_MEM_ADDR (0xE0000000) | |
336 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
337 | #define CFG_PCMCIA_DMA_ADDR (0xE4000000) | |
338 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
339 | #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) | |
340 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
341 | #define CFG_PCMCIA_IO_ADDR (0xEC000000) | |
342 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) | |
343 | ||
344 | /*----------------------------------------------------------------------- | |
345 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
346 | *----------------------------------------------------------------------- | |
347 | */ | |
348 | ||
349 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
350 | ||
351 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
352 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
353 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
354 | ||
355 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
356 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
357 | ||
358 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
359 | ||
360 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR | |
361 | ||
362 | /* Offset for data I/O */ | |
363 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) | |
364 | ||
365 | /* Offset for normal register accesses */ | |
366 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) | |
367 | ||
368 | /* Offset for alternate registers */ | |
369 | #define CFG_ATA_ALT_OFFSET 0x0100 | |
370 | ||
371 | /*----------------------------------------------------------------------- | |
372 | * | |
373 | *----------------------------------------------------------------------- | |
374 | * | |
375 | */ | |
376 | #define CFG_DER 0 | |
377 | ||
378 | /* | |
379 | * Init Memory Controller: | |
380 | * | |
381 | * BR0/1 and OR0/1 (FLASH) | |
382 | */ | |
383 | ||
384 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
385 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
386 | ||
387 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
388 | * restrict access enough to keep SRAM working (if any) | |
389 | * but not too much to meddle with FLASH accesses | |
390 | */ | |
391 | #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
392 | #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
393 | ||
394 | /* | |
395 | * FLASH timing: Default value of OR0 after reset | |
396 | */ | |
397 | #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ | |
398 | OR_SCY_6_CLK | OR_TRLX) | |
399 | ||
400 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
401 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
402 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
403 | ||
404 | #define CFG_OR1_REMAP CFG_OR0_REMAP | |
405 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
406 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
407 | ||
408 | /* | |
409 | * BR2/3 and OR2/3 (SDRAM) | |
410 | * | |
411 | */ | |
412 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
413 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
414 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ | |
415 | ||
416 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
417 | #define CFG_OR_TIMING_SDRAM 0x00000A00 | |
418 | ||
419 | #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) | |
420 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
421 | ||
422 | #ifndef CONFIG_CAN_DRIVER | |
423 | #define CFG_OR3_PRELIM CFG_OR2_PRELIM | |
424 | #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
425 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
426 | #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ | |
427 | #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
428 | #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) | |
429 | #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ | |
430 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
431 | #endif /* CONFIG_CAN_DRIVER */ | |
432 | ||
433 | /* | |
434 | * 4096 Rows from SDRAM example configuration | |
435 | * 1000 factor s -> ms | |
436 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
437 | * 4 Number of refresh cycles per period | |
438 | * 64 Refresh cycle in ms per number of rows | |
439 | */ | |
440 | #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) | |
441 | ||
442 | /* | |
443 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) | |
444 | * | |
445 | * CPUclock(MHz) * 31.2 | |
446 | * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0 | |
447 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 | |
448 | * | |
449 | * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us | |
450 | * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us | |
451 | * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us | |
452 | * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us | |
453 | * | |
454 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will | |
455 | * be met also in the default configuration, i.e. if environment variable | |
456 | * 'cpuclk' is not set. | |
457 | */ | |
458 | #define CFG_MAMR_PTA 128 | |
459 | ||
460 | /* | |
461 | * Memory Periodic Timer Prescaler Register (MPTPR) values. | |
462 | */ | |
463 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ | |
464 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 | |
465 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ | |
466 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 | |
467 | ||
468 | /* | |
469 | * MAMR settings for SDRAM | |
470 | */ | |
471 | ||
472 | /* 8 column SDRAM */ | |
473 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
474 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
475 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
476 | /* 9 column SDRAM */ | |
477 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
478 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
479 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
480 | /* 10 column SDRAM */ | |
481 | #define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
482 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ | |
483 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
484 | ||
485 | /* | |
486 | * Internal Definitions | |
487 | * | |
488 | * Boot Flags | |
489 | */ | |
490 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
491 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
492 | ||
493 | /* | |
494 | * Network configuration | |
495 | */ | |
496 | #define CONFIG_FEC_ENET /* enable ethernet on FEC */ | |
497 | #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ | |
498 | #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ | |
499 | ||
500 | #define CONFIG_LAST_STAGE_INIT 1 /* Have to configure PHYs for Linux */ | |
501 | ||
502 | /* CFG_DISCOVER_PHY only works with FEC if only one interface is enabled */ | |
503 | #if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2)) | |
504 | #define CFG_DISCOVER_PHY | |
505 | #endif | |
506 | ||
507 | #ifndef CFG_DISCOVER_PHY | |
508 | /* PHY addresses - hard wired in hardware */ | |
509 | #define CONFIG_FEC1_PHY 1 | |
510 | #define CONFIG_FEC2_PHY 2 | |
511 | #endif | |
512 | ||
513 | #define CONFIG_NET_RETRY_COUNT 3 | |
514 | #define CONFIG_ETHPRIME "FEC ETHERNET" | |
515 | ||
516 | #endif /* __CONFIG_H */ |