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56523f12 | 1 | /* |
8f0b7cbe | 2 | * (C) Copyright 2003-2005 |
56523f12 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
8f0b7cbe | 5 | * (C) Copyright 2004-2005 |
56523f12 WD |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
56523f12 WD |
30 | /* |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | ||
35 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
36 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
37 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ | |
8f0b7cbe | 38 | #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ |
7e6bf358 | 39 | #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ |
83e40ba7 | 40 | #define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ |
56523f12 WD |
41 | |
42 | #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ | |
43 | ||
44 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
45 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
46 | ||
47 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ | |
48 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
49 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
50 | #endif | |
51 | ||
52 | /* | |
53 | * Serial console configuration | |
54 | */ | |
55 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
56 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
57 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
58 | ||
7e6bf358 WD |
59 | #ifdef CONFIG_STK52XX |
60 | #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ | |
61 | #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ | |
62 | #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ | |
63 | #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ | |
64 | #define CONFIG_BOARD_EARLY_INIT_R | |
65 | #endif /* CONFIG_STK52XX */ | |
56523f12 | 66 | |
56523f12 WD |
67 | /* |
68 | * PCI Mapping: | |
69 | * 0x40000000 - 0x4fffffff - PCI Memory | |
70 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
71 | */ | |
7e6bf358 WD |
72 | #ifdef CONFIG_STK52XX |
73 | #define CONFIG_PCI 1 | |
56523f12 | 74 | #define CONFIG_PCI_PNP 1 |
31a64923 | 75 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ |
56523f12 WD |
76 | |
77 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
78 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
79 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
80 | ||
81 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
82 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
83 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
84 | ||
85 | #define CONFIG_NET_MULTI 1 | |
63ff004c | 86 | #define CONFIG_EEPRO100 |
56523f12 WD |
87 | #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
88 | #define CONFIG_NS8382X 1 | |
83e40ba7 | 89 | #endif /* CONFIG_STK52XX */ |
56523f12 | 90 | |
8f0b7cbe | 91 | #ifdef CONFIG_PCI |
7e6bf358 | 92 | #define ADD_PCI_CMD CFG_CMD_PCI |
8f0b7cbe | 93 | #else |
7e6bf358 WD |
94 | #define ADD_PCI_CMD 0 |
95 | #endif | |
56523f12 | 96 | |
8f0b7cbe WD |
97 | /* |
98 | * Video console | |
99 | */ | |
100 | #if 1 | |
101 | #define CONFIG_VIDEO | |
102 | #define CONFIG_VIDEO_SM501 | |
103 | #define CONFIG_VIDEO_SM501_32BPP | |
104 | #define CONFIG_CFB_CONSOLE | |
105 | #define CONFIG_VIDEO_LOGO | |
106 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
107 | #define CONFIG_CONSOLE_EXTRA_INFO | |
108 | #define CONFIG_VIDEO_SW_CURSOR | |
109 | #define CONFIG_SPLASH_SCREEN | |
83e40ba7 | 110 | #define CFG_CONSOLE_IS_IN_ENV |
8f0b7cbe | 111 | #endif |
56523f12 | 112 | |
8f0b7cbe WD |
113 | #ifdef CONFIG_VIDEO |
114 | #define ADD_BMP_CMD CFG_CMD_BMP | |
115 | #else | |
116 | #define ADD_BMP_CMD 0 | |
56523f12 WD |
117 | #endif |
118 | ||
119 | /* Partitions */ | |
89c02e2c | 120 | #define CONFIG_MAC_PARTITION |
56523f12 | 121 | #define CONFIG_DOS_PARTITION |
8f0b7cbe | 122 | #define CONFIG_ISO_PARTITION |
56523f12 WD |
123 | |
124 | /* USB */ | |
7e6bf358 | 125 | #ifdef CONFIG_STK52XX |
56523f12 | 126 | #define CONFIG_USB_OHCI |
81050926 | 127 | #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT |
56523f12 WD |
128 | #define CONFIG_USB_STORAGE |
129 | #else | |
81050926 | 130 | #define ADD_USB_CMD 0 |
56523f12 WD |
131 | #endif |
132 | ||
133 | /* POST support */ | |
134 | #define CONFIG_POST (CFG_POST_MEMORY | \ | |
135 | CFG_POST_CPU | \ | |
136 | CFG_POST_I2C) | |
137 | ||
138 | #ifdef CONFIG_POST | |
139 | #define CFG_CMD_POST_DIAG CFG_CMD_DIAG | |
140 | /* preserve space for the post_word at end of on-chip SRAM */ | |
141 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
142 | #else | |
143 | #define CFG_CMD_POST_DIAG 0 | |
144 | #endif | |
145 | ||
146 | /* IDE */ | |
7e6bf358 | 147 | #if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) |
151ab83a | 148 | #define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) |
56523f12 WD |
149 | #else |
150 | #define ADD_IDE_CMD 0 | |
151 | #endif | |
152 | ||
153 | /* | |
154 | * Supported commands | |
155 | */ | |
156 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
8f0b7cbe | 157 | ADD_BMP_CMD | \ |
151ab83a | 158 | ADD_IDE_CMD | \ |
56523f12 WD |
159 | ADD_PCI_CMD | \ |
160 | ADD_USB_CMD | \ | |
151ab83a | 161 | CFG_CMD_ASKENV | \ |
56523f12 | 162 | CFG_CMD_DATE | \ |
151ab83a | 163 | CFG_CMD_DHCP | \ |
151ab83a WD |
164 | CFG_CMD_EEPROM | \ |
165 | CFG_CMD_I2C | \ | |
d534f5cc | 166 | CFG_CMD_JFFS2 | \ |
56523f12 | 167 | CFG_CMD_MII | \ |
414eec35 | 168 | CFG_CMD_NFS | \ |
56523f12 | 169 | CFG_CMD_PING | \ |
151ab83a | 170 | CFG_CMD_POST_DIAG | \ |
414eec35 | 171 | CFG_CMD_REGINFO | \ |
6617aae9 WD |
172 | CFG_CMD_SNTP | \ |
173 | CFG_CMD_BSP) | |
56523f12 WD |
174 | |
175 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
176 | #include <cmd_confdefs.h> | |
177 | ||
151ab83a WD |
178 | #define CONFIG_TIMESTAMP /* display image timestamps */ |
179 | ||
56523f12 | 180 | #if (TEXT_BASE == 0xFC000000) /* Boot low */ |
81050926 | 181 | # define CFG_LOWBOOT 1 |
56523f12 WD |
182 | #endif |
183 | ||
184 | /* | |
185 | * Autobooting | |
186 | */ | |
187 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
188 | ||
81050926 | 189 | #define CONFIG_PREBOOT "echo;" \ |
56523f12 WD |
190 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ |
191 | "echo" | |
192 | ||
193 | #undef CONFIG_BOOTARGS | |
194 | ||
195 | #if defined (CONFIG_TQM5200_AA) | |
8f0b7cbe | 196 | # define CONFIG_U_BOOT_SUFFIX "-AA\0" |
89c02e2c | 197 | #elif defined (CONFIG_TQM5200_AB) |
e6325153 | 198 | # define CONFIG_U_BOOT_SUFFIX "-AB\0" |
89c02e2c | 199 | #elif defined (CONFIG_TQM5200_AC) |
e6325153 | 200 | # define CONFIG_U_BOOT_SUFFIX "-AC\0" |
56523f12 | 201 | #else |
e6325153 | 202 | # define CONFIG_U_BOOT_SUFFIX "\0" |
89c02e2c WD |
203 | #endif |
204 | ||
81050926 | 205 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
56523f12 | 206 | "netdev=eth0\0" \ |
89c02e2c | 207 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
56523f12 | 208 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
56523f12 | 209 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b WD |
210 | "nfsroot=${serverip}:${rootpath}\0" \ |
211 | "addip=setenv bootargs ${bootargs} " \ | |
212 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
213 | ":${hostname}:${netdev}:off panic=1\0" \ | |
56523f12 | 214 | "flash_self=run ramargs addip;" \ |
fe126d8b | 215 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
7e6bf358 | 216 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b WD |
217 | "bootm ${kernel_addr}\0" \ |
218 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
89c02e2c | 219 | "bootfile=/tftpboot/tqm5200/uImage\0" \ |
fe126d8b | 220 | "load=tftp 200000 ${u-boot}\0" \ |
89c02e2c WD |
221 | "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \ |
222 | "update=protect off FC000000 FC05FFFF;" \ | |
223 | "erase FC000000 FC05FFFF;" \ | |
fe126d8b | 224 | "cp.b 200000 FC000000 ${filesize};" \ |
e6325153 | 225 | "protect on FC000000 FC05FFFF\0" \ |
7e6bf358 | 226 | "" |
56523f12 WD |
227 | |
228 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
229 | ||
230 | /* | |
231 | * IPB Bus clocking configuration. | |
232 | */ | |
81050926 | 233 | #define CFG_IPBSPEED_133 /* define for 133MHz speed */ |
56523f12 WD |
234 | |
235 | #if defined(CFG_IPBSPEED_133) | |
236 | /* | |
237 | * PCI Bus clocking configuration | |
238 | * | |
239 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
240 | * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't | |
241 | * been tested with a IPB Bus Clock of 66 MHz. | |
242 | */ | |
243 | #define CFG_PCISPEED_66 /* define for 66MHz speed */ | |
244 | #endif | |
245 | ||
246 | /* | |
247 | * I2C configuration | |
248 | */ | |
249 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
8f0b7cbe WD |
250 | #ifdef CONFIG_TQM5200_REV100 |
251 | #define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ | |
56523f12 | 252 | #else |
8f0b7cbe | 253 | #define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ |
56523f12 WD |
254 | #endif |
255 | ||
256 | /* | |
257 | * I2C clock frequency | |
258 | * | |
259 | * Please notice, that the resulting clock frequency could differ from the | |
260 | * configured value. This is because the I2C clock is derived from system | |
261 | * clock over a frequency divider with only a few divider values. U-boot | |
262 | * calculates the best approximation for CFG_I2C_SPEED. However the calculated | |
263 | * approximation allways lies below the configured value, never above. | |
264 | */ | |
265 | #define CFG_I2C_SPEED 100000 /* 100 kHz */ | |
266 | #define CFG_I2C_SLAVE 0x7F | |
267 | ||
268 | /* | |
269 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work | |
270 | * also). For other EEPROMs configuration should be verified. On Mini-FAP the | |
271 | * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the | |
272 | * same configuration could be used. | |
273 | */ | |
274 | #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ | |
275 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
276 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
277 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
278 | ||
279 | /* | |
280 | * HW-Monitor configuration on Mini-FAP | |
281 | */ | |
282 | #if defined (CONFIG_MINIFAP) | |
283 | #define CFG_I2C_HWMON_ADDR 0x2C | |
284 | #endif | |
285 | ||
286 | /* List of I2C addresses to be verified by POST */ | |
287 | #if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB) | |
288 | #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ | |
289 | CFG_I2C_SLAVE } | |
290 | #elif defined (CONFIG_TQM5200_AC) | |
291 | #define I2C_ADDR_LIST { CFG_I2C_SLAVE } | |
292 | #endif | |
293 | ||
294 | #if defined (CONFIG_MINIFAP) | |
295 | #undef I2C_ADDR_LIST | |
296 | #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ | |
297 | CFG_I2C_HWMON_ADDR, \ | |
298 | CFG_I2C_SLAVE } | |
299 | #endif | |
300 | ||
301 | /* | |
302 | * Flash configuration | |
303 | */ | |
304 | #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ | |
305 | ||
7e6bf358 WD |
306 | /* use CFI flash driver if no module variant is spezified */ |
307 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ | |
308 | #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
309 | #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } | |
310 | #define CFG_FLASH_EMPTY_INFO | |
8f0b7cbe WD |
311 | #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ |
312 | #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
313 | #undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ | |
56523f12 WD |
314 | |
315 | #if !defined(CFG_LOWBOOT) | |
89c02e2c | 316 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) |
56523f12 | 317 | #else /* CFG_LOWBOOT */ |
89c02e2c | 318 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) |
56523f12 WD |
319 | #endif /* CFG_LOWBOOT */ |
320 | #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks | |
321 | (= chip selects) */ | |
81050926 WD |
322 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
323 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
56523f12 | 324 | |
d534f5cc WD |
325 | /* Dynamic MTD partition support */ |
326 | #define CONFIG_JFFS2_CMDLINE | |
327 | #define MTDIDS_DEFAULT "nor0=TQM5200-0" | |
328 | #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ | |
329 | "1408k(kernel)," \ | |
330 | "2m(initrd)," \ | |
331 | "4m(small-fs)," \ | |
332 | "16m(big-fs)," \ | |
333 | "8m(misc)" | |
56523f12 WD |
334 | |
335 | /* | |
336 | * Environment settings | |
337 | */ | |
338 | #define CFG_ENV_IS_IN_FLASH 1 | |
339 | #define CFG_ENV_SIZE 0x10000 | |
340 | #define CFG_ENV_SECT_SIZE 0x20000 | |
89c02e2c WD |
341 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) |
342 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
56523f12 WD |
343 | |
344 | /* | |
345 | * Memory map | |
346 | */ | |
347 | #define CFG_MBAR 0xF0000000 | |
348 | #define CFG_SDRAM_BASE 0x00000000 | |
349 | #define CFG_DEFAULT_MBAR 0x80000000 | |
350 | ||
351 | /* Use ON-Chip SRAM until RAM will be available */ | |
352 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM | |
353 | #ifdef CONFIG_POST | |
354 | /* preserve space for the post_word at end of on-chip SRAM */ | |
355 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE | |
356 | #else | |
357 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE | |
358 | #endif | |
359 | ||
360 | ||
361 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
362 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
363 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
364 | ||
89c02e2c | 365 | #define CFG_MONITOR_BASE TEXT_BASE |
56523f12 WD |
366 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
367 | # define CFG_RAMBOOT 1 | |
368 | #endif | |
369 | ||
89c02e2c | 370 | #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
d00de23b | 371 | #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ |
56523f12 WD |
372 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
373 | ||
374 | /* | |
375 | * Ethernet configuration | |
376 | */ | |
377 | #define CONFIG_MPC5xxx_FEC 1 | |
378 | /* | |
379 | * Define CONFIG_FEC_10MBIT to force FEC at 10Mb | |
380 | */ | |
381 | /* #define CONFIG_FEC_10MBIT 1 */ | |
382 | #define CONFIG_PHY_ADDR 0x00 | |
383 | ||
384 | /* | |
385 | * GPIO configuration | |
386 | * | |
387 | * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): | |
388 | * Bit 0 (mask: 0x80000000): 1 | |
389 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): | |
8f0b7cbe | 390 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. |
8f0b7cbe | 391 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. |
83e40ba7 WD |
392 | * Use for REV200 STK52XX boards. Do not use with REV100 modules |
393 | * (because, there I2C1 is used as I2C bus) | |
56523f12 | 394 | * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 |
83e40ba7 WD |
395 | * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) |
396 | * 000 -> All PSC2 pins are GIOPs | |
397 | * 001 -> CAN1/2 on PSC2 pins | |
398 | * Use for REV100 STK52xx boards | |
7e6bf358 WD |
399 | * use PSC6: |
400 | * on STK52xx: | |
8f0b7cbe WD |
401 | * use as UART. Pins PSC6_0 to PSC6_3 are used. |
402 | * Bits 9:11 (mask: 0x00700000): | |
7e6bf358 WD |
403 | * 101 -> PSC6 : Extended POST test is not available |
404 | * on MINI-FAP and TQM5200_IB: | |
8f0b7cbe WD |
405 | * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): |
406 | * 000 -> PSC6 could not be used as UART, CODEC or IrDA | |
407 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST | |
408 | * tests. | |
56523f12 WD |
409 | */ |
410 | #if defined (CONFIG_MINIFAP) | |
8f0b7cbe | 411 | # define CFG_GPS_PORT_CONFIG 0x91000004 |
7e6bf358 | 412 | #elif defined (CONFIG_STK52XX) |
83e40ba7 WD |
413 | # if defined (CONFIG_STK52XX_REV100) |
414 | # define CFG_GPS_PORT_CONFIG 0x81500014 | |
415 | # else /* STK52xx REV200 and above */ | |
416 | # if defined (CONFIG_TQM5200_REV100) | |
417 | # error TQM5200 REV100 not supported on STK52XX REV200 or above | |
418 | # else/* TQM5200 REV200 and above */ | |
419 | # define CFG_GPS_PORT_CONFIG 0x91500004 | |
420 | # endif | |
8f0b7cbe | 421 | # endif |
83e40ba7 | 422 | #else /* TMQ5200 Inbetriebnahme-Board */ |
8f0b7cbe | 423 | # define CFG_GPS_PORT_CONFIG 0x81000004 |
56523f12 WD |
424 | #endif |
425 | ||
426 | /* | |
427 | * RTC configuration | |
428 | */ | |
4f562f14 WD |
429 | #if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100) |
430 | # define CONFIG_RTC_M41T11 1 | |
431 | # define CFG_I2C_RTC_ADDR 0x68 | |
432 | #else | |
433 | # define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
434 | #endif | |
56523f12 WD |
435 | |
436 | /* | |
437 | * Miscellaneous configurable options | |
438 | */ | |
439 | #define CFG_LONGHELP /* undef to save memory */ | |
440 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
441 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
442 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
443 | #else | |
444 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
445 | #endif | |
446 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
447 | #define CFG_MAXARGS 16 /* max number of command args */ | |
448 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
449 | ||
450 | /* Enable an alternate, more extensive memory test */ | |
451 | #define CFG_ALT_MEMTEST | |
452 | ||
453 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
454 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
455 | ||
456 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
457 | ||
458 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
459 | ||
460 | /* | |
461 | * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, | |
462 | * which is normally part of the default commands (CFV_CMD_DFL) | |
463 | */ | |
464 | #define CONFIG_LOOPW | |
465 | ||
466 | /* | |
467 | * Various low-level settings | |
468 | */ | |
469 | #if defined(CONFIG_MPC5200) | |
470 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI | |
471 | #define CFG_HID0_FINAL HID0_ICE | |
472 | #else | |
473 | #define CFG_HID0_INIT 0 | |
474 | #define CFG_HID0_FINAL 0 | |
475 | #endif | |
476 | ||
477 | #define CFG_BOOTCS_START CFG_FLASH_BASE | |
478 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE | |
479 | #ifdef CFG_PCISPEED_66 | |
480 | #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ | |
481 | #else | |
482 | #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ | |
483 | #endif | |
484 | #define CFG_CS0_START CFG_FLASH_BASE | |
485 | #define CFG_CS0_SIZE CFG_FLASH_SIZE | |
486 | ||
7e6bf358 WD |
487 | /* automatic configuration of chip selects */ |
488 | #ifdef CONFIG_CS_AUTOCONF | |
489 | #define CONFIG_LAST_STAGE_INIT | |
490 | #endif | |
491 | ||
56523f12 WD |
492 | /* |
493 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
494 | * for SDRAM autosizing. | |
495 | */ | |
7e6bf358 | 496 | #if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF) |
56523f12 | 497 | #define CFG_CS2_START 0xE5000000 |
7e6bf358 | 498 | #ifdef CONFIG_TQM5200_AB |
56523f12 | 499 | #define CFG_CS2_SIZE 0x80000 /* 512 kByte */ |
7e6bf358 WD |
500 | #else /* CONFIG_CS_AUTOCONF */ |
501 | #define CFG_CS2_SIZE 0x100000 /* 1 MByte */ | |
502 | #endif | |
56523f12 WD |
503 | #define CFG_CS2_CFG 0x0004D930 |
504 | #endif | |
505 | ||
506 | /* | |
507 | * Grafic controller - Do not map below 2 GB in address space, because this | |
508 | * area is used for SDRAM autosizing. | |
509 | */ | |
7e6bf358 WD |
510 | #if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \ |
511 | defined (CONFIG_CS_AUTOCONF) | |
8f0b7cbe WD |
512 | #define SM501_FB_BASE 0xE0000000 |
513 | #define CFG_CS1_START (SM501_FB_BASE) | |
56523f12 | 514 | #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ |
89394047 | 515 | #define CFG_CS1_CFG 0x8F48FF70 |
56523f12 WD |
516 | #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 |
517 | #endif | |
518 | ||
519 | #define CFG_CS_BURST 0x00000000 | |
8f0b7cbe | 520 | #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ |
56523f12 WD |
521 | |
522 | #define CFG_RESET_ADDRESS 0xff000000 | |
523 | ||
524 | /*----------------------------------------------------------------------- | |
525 | * USB stuff | |
526 | *----------------------------------------------------------------------- | |
527 | */ | |
528 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
529 | #define CONFIG_USB_CONFIG 0x00001000 | |
530 | ||
531 | /*----------------------------------------------------------------------- | |
532 | * IDE/ATA stuff Supports IDE harddisk | |
533 | *----------------------------------------------------------------------- | |
534 | */ | |
535 | ||
81050926 | 536 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
56523f12 | 537 | |
81050926 WD |
538 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
539 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
56523f12 | 540 | |
81050926 | 541 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
56523f12 WD |
542 | #define CONFIG_IDE_PREINIT |
543 | ||
544 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
8f0b7cbe | 545 | #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ |
56523f12 WD |
546 | |
547 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
548 | ||
549 | #define CFG_ATA_BASE_ADDR MPC5XXX_ATA | |
550 | ||
551 | /* Offset for data I/O */ | |
552 | #define CFG_ATA_DATA_OFFSET (0x0060) | |
553 | ||
554 | /* Offset for normal register accesses */ | |
555 | #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) | |
556 | ||
557 | /* Offset for alternate registers */ | |
558 | #define CFG_ATA_ALT_OFFSET (0x005C) | |
559 | ||
81050926 WD |
560 | /* Interval between registers */ |
561 | #define CFG_ATA_STRIDE 4 | |
56523f12 WD |
562 | |
563 | #endif /* __CONFIG_H */ |