[people/ms/u-boot.git] / include / configs / TQM834x.h

/*
 * (C) Copyright 2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * TQM8349 board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */
#define CONFIG_MPC834x		1	/* MPC834x specific */
#define CONFIG_MPC8349		1	/* MPC8349 specific */

#define	CONFIG_SYS_TEXT_BASE	0x80000000

/* IMMR Base Address Register, use Freescale default: 0xff400000 */
#define CONFIG_SYS_IMMR		0xff400000

/* System clock. Primary input clock when in PCI host mode */
#define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */

/*
 * Local Bus LCRR
 *    LCRR:  DLL bypass, Clock divider is 8
 *
 *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
 *
 * External Local Bus rate is
 *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8

/* board pre init: do not call, nothing to do */

/* detect the number of flash banks */
#define CONFIG_BOARD_EARLY_INIT_R

/*
 * DDR Setup
 */
				/* DDR is system memory*/
#define CONFIG_SYS_DDR_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define DDR_CASLAT_25		/* CASLAT set to 2.5 */
#undef CONFIG_DDR_ECC		/* only for ECC DDR module */
#undef CONFIG_SPD_EEPROM	/* do not use SPD EEPROM for DDR setup */

#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00100000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_BASE		0x80000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		8		/* FLASH size in MB */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/*
 * FLASH bank number detection
 */

/*
 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
 * Flash banks has to be determined at runtime and stored in a gloabl variable
 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
 * flash_info, and should be made sufficiently large to accomodate the number
 * of banks that might actually be detected.  Since most (all?) Flash related
 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
 * the board, it is defined as tqm834x_num_flash_banks.
 */
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2

#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */

/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA) \
				| BR_MS_GPCM \
				| BR_PS_32 \
				| BR_V)

/* FLASH timing (0x0000_0c54) */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_GPCM_CSNT \
					| OR_GPCM_ACS_DIV4 \
					| OR_GPCM_SCY_5 \
					| OR_GPCM_TRLX)

#define CONFIG_SYS_PRELIM_OR_AM		OR_AM_1GB /* OR addr mask: 1 GiB */

#define CONFIG_SYS_OR0_PRELIM		(CONFIG_SYS_PRELIM_OR_AM  \
					| CONFIG_SYS_OR_TIMING_FLASH)

#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_1GB)

					/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE

/* disable remaining mappings */
#define CONFIG_SYS_BR1_PRELIM		0x00000000
#define CONFIG_SYS_OR1_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR1_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR1_PRELIM	0x00000000

#define CONFIG_SYS_BR2_PRELIM		0x00000000
#define CONFIG_SYS_OR2_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR2_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR2_PRELIM	0x00000000

#define CONFIG_SYS_BR3_PRELIM		0x00000000
#define CONFIG_SYS_OR3_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR3_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR3_PRELIM	0x00000000

/*
 * Monitor config
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#else
# undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

				/* Reserve 384 kB = 3 sect. for Mon */
#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)
				/* Reserve 512 kB for malloc */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000

/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16 bit */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes/write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20% */

/* I2C RTC */
#define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68 */

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_MII

#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

#if defined(CONFIG_PCI)

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

/* PCI1 host bridge */
#define CONFIG_SYS_PCI1_MEM_BASE	0x90000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	\
			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0xe2000000
#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE		0x1000000	/* 16M */

#undef CONFIG_EEPRO100
#define CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BASE
	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_MEM_BASE
	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
#endif

#define CONFIG_SYS_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */

#endif	/* CONFIG_PCI */

/*
 * Environment
 */
#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K (one sector) for env */
#define CONFIG_ENV_SIZE		0x8000	/*  32K max size */
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define CONFIG_LOADS_ECHO		1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1 /* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)

#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CORE_TO_CSB_2X1)

#if defined(PCI_64BIT)
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_64_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_32_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#endif

/* System IO Config */
#define CONFIG_SYS_SICRH	0
#define CONFIG_SYS_SICRL	SICRL_LDP_A

/* i-cache and d-cache disabled */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
				 HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2	HID2_HBE

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR 0 - 512M */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_BASE + 0x10000000 \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_BASE + 0x10000000 \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* stack in DCACHE @ 512M (no backing mem) */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATU_BL_128K \
				| BATU_VS \
				| BATU_VP)

/* PCI */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_IO_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_IO_BASE \
				| BATU_BL_16M \
				| BATU_VS \
				| BATU_VP)
#else
#define CONFIG_SYS_IBAT3L	(0)
#define CONFIG_SYS_IBAT3U	(0)
#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)
#define CONFIG_SYS_IBAT5L	(0)
#define CONFIG_SYS_IBAT5U	(0)
#endif

/* IMMRBAR */
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_IMMR \
				| BATU_BL_1M \
				| BATU_VS \
				| BATU_VP)

/* FLASH */
#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_FLASH_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		400000

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=tqm834x\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	"flash_nfs_old=run nfsargs addip addcons;"			\
		"bootm ${kernel_addr}\0"				\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"flash_self_old=run ramargs addip addcons;"			\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_self=run ramargs addip addcons;"				\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"net_nfs_old=tftp 400000 ${bootfile};"				\
		"run nfsargs addip addcons;bootm\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"tftp ${fdt_addr_r} ${fdt_file}; "			\
		"run nfsargs addip addcons; "				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=tqm834x/uImage\0"					\
	"fdtfile=tqm834x/tqm834x.dtb\0"					\
	"kernel_addr_r=400000\0"					\
	"fdt_addr_r=600000\0"						\
	"ramdisk_addr_r=800000\0"					\
	"kernel_addr=800C0000\0"					\
	"fdt_addr=800A0000\0"						\
	"ramdisk_addr=80300000\0"					\
	"u-boot=tqm834x/u-boot.bin\0"					\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=protect off 80000000 +${filesize};"			\
		"era 80000000 +${filesize};"				\
		"cp.b 200000 80000000 ${filesize}\0"			\
	"upd=run load update\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * JFFS2 partitions
 */
/* mtdparts command line support */
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD

/* default mtd partition table */
#endif	/* __CONFIG_H */
Commit	Line	Data
e6f2e902 MB	1	/*
	2	* (C) Copyright 2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
e6f2e902 MB	6	*/
	7
	8	/*
	9	* TQM8349 board configuration file
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
e6f2e902 MB	15	/*
	16	* High Level Configuration Options
	17	*/
	18	#define CONFIG_E300 1 /* E300 Family */
2c7920af	19	#define CONFIG_MPC834x 1 /* MPC834x specific */
9ca880a2	20	#define CONFIG_MPC8349 1 /* MPC8349 specific */
e6f2e902	21
2ae18241 WD	22	#define CONFIG_SYS_TEXT_BASE 0x80000000
2ae18241 WD	23
16263087	24	/* IMMR Base Address Register, use Freescale default: 0xff400000 */
6d0f6bcf	25	#define CONFIG_SYS_IMMR 0xff400000
e6f2e902 MB	26
	27	/* System clock. Primary input clock when in PCI host mode */
	28	#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
	29
	30	/*
	31	* Local Bus LCRR
	32	* LCRR: DLL bypass, Clock divider is 8
	33	*
	34	* for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
	35	*
	36	* External Local Bus rate is
	37	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	38	*/
c7190f02 KP	39	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
c7190f02 KP	40	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
e6f2e902 MB	41
e6f2e902 MB	42	/* board pre init: do not call, nothing to do */
e6f2e902 MB	43
	44	/* detect the number of flash banks */
	45	#define CONFIG_BOARD_EARLY_INIT_R
	46
	47	/*
	48	* DDR Setup
	49	*/
df939e16 JH	50	/* DDR is system memory*/
	51	#define CONFIG_SYS_DDR_BASE 0x00000000
	52	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
6d0f6bcf	53	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
df939e16 JH	54	#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
	55	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	56	#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
e6f2e902	57
df939e16	58	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
6d0f6bcf JCPV	59	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
6d0f6bcf JCPV	60	#define CONFIG_SYS_MEMTEST_END 0x00100000
e6f2e902 MB	61
	62	/*
	63	* FLASH on the Local Bus
	64	*/
df939e16 JH	65	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
df939e16 JH	66	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
6d0f6bcf JCPV	67	#undef CONFIG_SYS_FLASH_CHECKSUM
	68	#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
	69	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
df939e16	70	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
a3455c00	71	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
e6f2e902 MB	72
	73	/*
	74	* FLASH bank number detection
	75	*/
	76
	77	/*
df939e16 JH	78	* When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
	79	* Flash banks has to be determined at runtime and stored in a gloabl variable
	80	* tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
	81	* only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
	82	* flash_info, and should be made sufficiently large to accomodate the number
	83	* of banks that might actually be detected. Since most (all?) Flash related
	84	* functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
	85	* the board, it is defined as tqm834x_num_flash_banks.
e6f2e902	86	*/
6d0f6bcf	87	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
e6f2e902	88
df939e16	89	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
e6f2e902 MB	90
e6f2e902 MB	91	/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
df939e16 JH	92	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
	93	\| BR_MS_GPCM \
	94	\| BR_PS_32 \
	95	\| BR_V)
e6f2e902 MB	96
e6f2e902 MB	97	/* FLASH timing (0x0000_0c54) */
df939e16 JH	98	#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
	99	\| OR_GPCM_ACS_DIV4 \
	100	\| OR_GPCM_SCY_5 \
	101	\| OR_GPCM_TRLX)
e6f2e902	102
7d6a0982	103	#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
e6f2e902	104
df939e16 JH	105	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
df939e16 JH	106	\| CONFIG_SYS_OR_TIMING_FLASH)
e6f2e902	107
7d6a0982	108	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_1GB)
6902df56	109
df939e16 JH	110	/* Window base at flash base */
df939e16 JH	111	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
e6f2e902 MB	112
e6f2e902 MB	113	/* disable remaining mappings */
6d0f6bcf JCPV	114	#define CONFIG_SYS_BR1_PRELIM 0x00000000
	115	#define CONFIG_SYS_OR1_PRELIM 0x00000000
	116	#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
	117	#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
	118
	119	#define CONFIG_SYS_BR2_PRELIM 0x00000000
	120	#define CONFIG_SYS_OR2_PRELIM 0x00000000
	121	#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
	122	#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
	123
	124	#define CONFIG_SYS_BR3_PRELIM 0x00000000
	125	#define CONFIG_SYS_OR3_PRELIM 0x00000000
	126	#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
	127	#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
e6f2e902 MB	128
	129	/*
	130	* Monitor config
	131	*/
14d0a02a	132	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
e6f2e902	133
6d0f6bcf	134	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
4681e673	135	# define CONFIG_SYS_RAMBOOT
e6f2e902	136	#else
4681e673	137	# undef CONFIG_SYS_RAMBOOT
e6f2e902 MB	138	#endif
e6f2e902 MB	139
6d0f6bcf	140	#define CONFIG_SYS_INIT_RAM_LOCK 1
df939e16 JH	141	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
df939e16 JH	142	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
e6f2e902	143
df939e16 JH	144	#define CONFIG_SYS_GBL_DATA_OFFSET \
df939e16 JH	145	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	146	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e6f2e902	147
df939e16 JH	148	/* Reserve 384 kB = 3 sect. for Mon */
	149	#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
	150	/* Reserve 512 kB for malloc */
	151	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
e6f2e902 MB	152
	153	/*
	154	* Serial Port
	155	*/
	156	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	157	#define CONFIG_SYS_NS16550_SERIAL
	158	#define CONFIG_SYS_NS16550_REG_SIZE 1
	159	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
e6f2e902	160
6d0f6bcf	161	#define CONFIG_SYS_BAUDRATE_TABLE \
df939e16	162	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
e6f2e902	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
6d0f6bcf JCPV	165	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
e6f2e902 MB	166
	167	/*
	168	* I2C
	169	*/
00f792e0 HS	170	#define CONFIG_SYS_I2C
	171	#define CONFIG_SYS_I2C_FSL
	172	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	173	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	174	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
e6f2e902 MB	175
e6f2e902 MB	176	/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
df939e16 JH	177	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	178	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
	179	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
	180	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
e6f2e902 MB	181
e6f2e902 MB	182	/* I2C RTC */
df939e16 JH	183	#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
df939e16 JH	184	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
e6f2e902	185
e6f2e902 MB	186	/*
	187	* TSEC
	188	*/
53677ef1	189	#define CONFIG_TSEC_ENET /* tsec ethernet support */
e6f2e902 MB	190	#define CONFIG_MII
e6f2e902 MB	191
6d0f6bcf	192	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
df939e16	193	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
6d0f6bcf	194	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
df939e16	195	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
e6f2e902 MB	196
	197	#if defined(CONFIG_TSEC_ENET)
	198
255a3577 KP	199	#define CONFIG_TSEC1 1
	200	#define CONFIG_TSEC1_NAME "TSEC0"
	201	#define CONFIG_TSEC2 1
	202	#define CONFIG_TSEC2_NAME "TSEC1"
df939e16 JH	203	#define TSEC1_PHY_ADDR 2
	204	#define TSEC2_PHY_ADDR 1
	205	#define TSEC1_PHYIDX 0
	206	#define TSEC2_PHYIDX 0
3a79013e AF	207	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	208	#define TSEC2_FLAGS TSEC_GIGABIT
e6f2e902 MB	209
e6f2e902 MB	210	/* Options are: TSEC[0-1] */
df939e16	211	#define CONFIG_ETHPRIME "TSEC0"
e6f2e902 MB	212
	213	#endif /* CONFIG_TSEC_ENET */
	214
e6f2e902 MB	215	#if defined(CONFIG_PCI)
e6f2e902 MB	216
df939e16	217	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6902df56 RJ	218
6902df56 RJ	219	/* PCI1 host bridge */
df939e16 JH	220	#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
	221	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	222	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	223	#define CONFIG_SYS_PCI1_MMIO_BASE \
	224	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
	225	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	226	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	227	#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
	228	#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
	229	#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
e6f2e902	230
e6f2e902	231	#undef CONFIG_EEPRO100
63ff004c	232	#define CONFIG_EEPRO100
e6f2e902 MB	233	#undef CONFIG_TULIP
	234
	235	#if !defined(CONFIG_PCI_PNP)
6d0f6bcf JCPV	236	#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
6d0f6bcf JCPV	237	#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
6902df56	238	#define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
e6f2e902 MB	239	#endif
e6f2e902 MB	240
6d0f6bcf	241	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
e6f2e902 MB	242
	243	#endif /* CONFIG_PCI */
	244
	245	/*
	246	* Environment
	247	*/
df939e16 JH	248	#define CONFIG_ENV_ADDR \
	249	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	250	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
	251	#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
929b79a0 WD	252	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	253	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	254
df939e16 JH	255	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
df939e16 JH	256	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
e6f2e902	257
a1aa0bb5 JL	258	/*
	259	* BOOTP options
	260	*/
	261	#define CONFIG_BOOTP_BOOTFILESIZE
	262	#define CONFIG_BOOTP_BOOTPATH
	263	#define CONFIG_BOOTP_GATEWAY
	264	#define CONFIG_BOOTP_HOSTNAME
	265
e6f2e902 MB	266	/*
	267	* Miscellaneous configurable options
	268	*/
df939e16 JH	269	#define CONFIG_SYS_LONGHELP /* undef to save memory */
df939e16 JH	270	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
e6f2e902	271
df939e16 JH	272	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
df939e16 JH	273	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
a059e90e	274
df939e16	275	#undef CONFIG_WATCHDOG /* watchdog disabled */
e6f2e902 MB	276
	277	/*
	278	* For booting Linux, the board info and command line data
9f530d59	279	* have to be in the first 256 MB of memory, since this is
e6f2e902 MB	280	* the maximum mapped by the Linux kernel during initialization.
e6f2e902 MB	281	*/
df939e16 JH	282	/* Initial Memory map for Linux */
df939e16 JH	283	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
e6f2e902	284
6d0f6bcf	285	#define CONFIG_SYS_HRCW_LOW (\
e6f2e902 MB	286	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	287	HRCWL_DDR_TO_SCB_CLK_1X1 \|\
	288	HRCWL_CSB_TO_CLKIN_4X1 \|\
	289	HRCWL_VCO_1X2 \|\
	290	HRCWL_CORE_TO_CSB_2X1)
	291
	292	#if defined(PCI_64BIT)
6d0f6bcf	293	#define CONFIG_SYS_HRCW_HIGH (\
e6f2e902 MB	294	HRCWH_PCI_HOST \|\
	295	HRCWH_64_BIT_PCI \|\
	296	HRCWH_PCI1_ARBITER_ENABLE \|\
	297	HRCWH_PCI2_ARBITER_DISABLE \|\
	298	HRCWH_CORE_ENABLE \|\
	299	HRCWH_FROM_0X00000100 \|\
	300	HRCWH_BOOTSEQ_DISABLE \|\
	301	HRCWH_SW_WATCHDOG_DISABLE \|\
	302	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	303	HRCWH_TSEC1M_IN_GMII \|\
df939e16	304	HRCWH_TSEC2M_IN_GMII)
e6f2e902	305	#else
6d0f6bcf	306	#define CONFIG_SYS_HRCW_HIGH (\
e6f2e902 MB	307	HRCWH_PCI_HOST \|\
	308	HRCWH_32_BIT_PCI \|\
	309	HRCWH_PCI1_ARBITER_ENABLE \|\
6902df56	310	HRCWH_PCI2_ARBITER_DISABLE \|\
e6f2e902 MB	311	HRCWH_CORE_ENABLE \|\
	312	HRCWH_FROM_0X00000100 \|\
	313	HRCWH_BOOTSEQ_DISABLE \|\
	314	HRCWH_SW_WATCHDOG_DISABLE \|\
	315	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	316	HRCWH_TSEC1M_IN_GMII \|\
df939e16	317	HRCWH_TSEC2M_IN_GMII)
e6f2e902 MB	318	#endif
e6f2e902 MB	319
9260a561	320	/* System IO Config */
3c9b1ee1	321	#define CONFIG_SYS_SICRH 0
6d0f6bcf	322	#define CONFIG_SYS_SICRL SICRL_LDP_A
9260a561	323
e6f2e902	324	/* i-cache and d-cache disabled */
6d0f6bcf	325	#define CONFIG_SYS_HID0_INIT 0x000000000
1a2e203b KP	326	#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT \| \
1a2e203b KP	327	HID0_ENABLE_INSTRUCTION_CACHE)
6d0f6bcf	328	#define CONFIG_SYS_HID2 HID2_HBE
e6f2e902	329
31d82672 BB	330	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	331
2688e2f9	332	/* DDR 0 - 512M */
df939e16	333	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087	334	\| BATL_PP_RW \
df939e16 JH	335	\| BATL_MEMCOHERENCE)
	336	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	337	\| BATU_BL_256M \
	338	\| BATU_VS \
	339	\| BATU_VP)
	340	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
72cd4087	341	\| BATL_PP_RW \
df939e16 JH	342	\| BATL_MEMCOHERENCE)
	343	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
	344	\| BATU_BL_256M \
	345	\| BATU_VS \
	346	\| BATU_VP)
2688e2f9 KG	347
2688e2f9 KG	348	/* stack in DCACHE @ 512M (no backing mem) */
df939e16	349	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
72cd4087	350	\| BATL_PP_RW \
df939e16 JH	351	\| BATL_MEMCOHERENCE)
	352	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
	353	\| BATU_BL_128K \
	354	\| BATU_VS \
	355	\| BATU_VP)
2688e2f9 KG	356
2688e2f9 KG	357	/* PCI */
6fe16a87	358	#ifdef CONFIG_PCI
842033e6	359	#define CONFIG_PCI_INDIRECT_BRIDGE
df939e16	360	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
72cd4087	361	\| BATL_PP_RW \
df939e16 JH	362	\| BATL_MEMCOHERENCE)
	363	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
	364	\| BATU_BL_256M \
	365	\| BATU_VS \
	366	\| BATU_VP)
	367	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
72cd4087	368	\| BATL_PP_RW \
df939e16 JH	369	\| BATL_MEMCOHERENCE \
	370	\| BATL_GUARDEDSTORAGE)
	371	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
	372	\| BATU_BL_256M \
	373	\| BATU_VS \
	374	\| BATU_VP)
	375	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
72cd4087	376	\| BATL_PP_RW \
df939e16 JH	377	\| BATL_CACHEINHIBIT \
	378	\| BATL_GUARDEDSTORAGE)
	379	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
	380	\| BATU_BL_16M \
	381	\| BATU_VS \
	382	\| BATU_VP)
6fe16a87	383	#else
6d0f6bcf JCPV	384	#define CONFIG_SYS_IBAT3L (0)
	385	#define CONFIG_SYS_IBAT3U (0)
	386	#define CONFIG_SYS_IBAT4L (0)
	387	#define CONFIG_SYS_IBAT4U (0)
	388	#define CONFIG_SYS_IBAT5L (0)
	389	#define CONFIG_SYS_IBAT5U (0)
6fe16a87	390	#endif
2688e2f9 KG	391
2688e2f9 KG	392	/* IMMRBAR */
df939e16	393	#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
72cd4087	394	\| BATL_PP_RW \
df939e16 JH	395	\| BATL_CACHEINHIBIT \
	396	\| BATL_GUARDEDSTORAGE)
	397	#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
	398	\| BATU_BL_1M \
	399	\| BATU_VS \
	400	\| BATU_VP)
2688e2f9 KG	401
2688e2f9 KG	402	/* FLASH */
df939e16	403	#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
72cd4087	404	\| BATL_PP_RW \
df939e16 JH	405	\| BATL_CACHEINHIBIT \
	406	\| BATL_GUARDEDSTORAGE)
	407	#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
	408	\| BATU_BL_256M \
	409	\| BATU_VS \
	410	\| BATU_VP)
6d0f6bcf JCPV	411
	412	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	413	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	414	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	415	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	416	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	417	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	418	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	419	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	420	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	421	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	422	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	423	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	424	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	425	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	426	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	427	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
2688e2f9	428
2694690e	429	#if defined(CONFIG_CMD_KGDB)
e6f2e902	430	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
e6f2e902 MB	431	#endif
	432
	433	/*
	434	* Environment Configuration
	435	*/
	436
df939e16 JH	437	/* default location for tftp and bootm */
df939e16 JH	438	#define CONFIG_LOADADDR 400000
e6f2e902	439
e6f2e902	440	#define CONFIG_PREBOOT "echo;" \
32bf3d14	441	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
e6f2e902 MB	442	"echo"
e6f2e902 MB	443
e6f2e902 MB	444	#define CONFIG_EXTRA_ENV_SETTINGS \
e6f2e902 MB	445	"netdev=eth0\0" \
b931b3a9	446	"hostname=tqm834x\0" \
e6f2e902	447	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	448	"nfsroot=${serverip}:${rootpath}\0" \
e6f2e902	449	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	450	"addip=setenv bootargs ${bootargs} " \
	451	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	452	":${hostname}:${netdev}:off panic=1\0" \
df939e16	453	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
4681e673	454	"flash_nfs_old=run nfsargs addip addcons;" \
fe126d8b	455	"bootm ${kernel_addr}\0" \
4681e673 WD	456	"flash_nfs=run nfsargs addip addcons;" \
	457	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	458	"flash_self_old=run ramargs addip addcons;" \
fe126d8b	459	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
4681e673 WD	460	"flash_self=run ramargs addip addcons;" \
	461	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	462	"net_nfs_old=tftp 400000 ${bootfile};" \
	463	"run nfsargs addip addcons;bootm\0" \
	464	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	465	"tftp ${fdt_addr_r} ${fdt_file}; " \
	466	"run nfsargs addip addcons; " \
	467	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
e6f2e902	468	"rootpath=/opt/eldk/ppc_6xx\0" \
4681e673 WD	469	"bootfile=tqm834x/uImage\0" \
	470	"fdtfile=tqm834x/tqm834x.dtb\0" \
	471	"kernel_addr_r=400000\0" \
	472	"fdt_addr_r=600000\0" \
	473	"ramdisk_addr_r=800000\0" \
	474	"kernel_addr=800C0000\0" \
	475	"fdt_addr=800A0000\0" \
	476	"ramdisk_addr=80300000\0" \
	477	"u-boot=tqm834x/u-boot.bin\0" \
	478	"load=tftp 200000 ${u-boot}\0" \
	479	"update=protect off 80000000 +${filesize};" \
	480	"era 80000000 +${filesize};" \
	481	"cp.b 200000 80000000 ${filesize}\0" \
d8ab58b2	482	"upd=run load update\0" \
e6f2e902 MB	483	""
	484
	485	#define CONFIG_BOOTCOMMAND "run flash_self"
	486
	487	/*
	488	* JFFS2 partitions
	489	*/
	490	/* mtdparts command line support */
942556a9 SR	491	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	492	#define CONFIG_FLASH_CFI_MTD
e6f2e902 MB	493
e6f2e902 MB	494	/* default mtd partition table */
e6f2e902	495	#endif /* __CONFIG_H */