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f12e568c | 1 | /* |
23c5d253 | 2 | * (C) Copyright 2000-2014 |
f12e568c WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
f12e568c WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ | |
21 | #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ | |
22 | ||
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
24 | ||
f12e568c | 25 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
3cb7a480 WD |
26 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
27 | #define CONFIG_SYS_MAXIDLE 10 | |
f12e568c | 28 | |
ae3af05e | 29 | #define CONFIG_BOOTCOUNT_LIMIT |
f12e568c | 30 | |
f12e568c WD |
31 | |
32 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
33 | ||
34 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 35 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
f12e568c WD |
36 | "echo" |
37 | ||
38 | #undef CONFIG_BOOTARGS | |
39 | ||
40 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
41 | "netdev=eth0\0" \ | |
42 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 43 | "nfsroot=${serverip}:${rootpath}\0" \ |
f12e568c | 44 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
45 | "addip=setenv bootargs ${bootargs} " \ |
46 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
47 | ":${hostname}:${netdev}:off panic=1\0" \ | |
f12e568c | 48 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 49 | "bootm ${kernel_addr}\0" \ |
f12e568c | 50 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
51 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
52 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
f12e568c | 53 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
29f8f58f WD |
54 | "hostname=TQM855M\0" \ |
55 | "bootfile=TQM855M/uImage\0" \ | |
eb6da805 WD |
56 | "fdt_addr=40080000\0" \ |
57 | "kernel_addr=400A0000\0" \ | |
58 | "ramdisk_addr=40280000\0" \ | |
29f8f58f WD |
59 | "u-boot=TQM855M/u-image.bin\0" \ |
60 | "load=tftp 200000 ${u-boot}\0" \ | |
61 | "update=prot off 40000000 +${filesize};" \ | |
62 | "era 40000000 +${filesize};" \ | |
63 | "cp.b 200000 40000000 ${filesize};" \ | |
64 | "sete filesize;save\0" \ | |
f12e568c WD |
65 | "" |
66 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
67 | ||
68 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 69 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
f12e568c WD |
70 | |
71 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
72 | ||
f12e568c WD |
73 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
74 | ||
d4ca31c4 | 75 | /* enable I2C and select the hardware/software driver */ |
ea818dbb HS |
76 | #define CONFIG_SYS_I2C |
77 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
78 | #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ | |
79 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE | |
d4ca31c4 WD |
80 | /* |
81 | * Software (bit-bang) I2C driver configuration | |
82 | */ | |
83 | #define PB_SCL 0x00000020 /* PB 26 */ | |
84 | #define PB_SDA 0x00000010 /* PB 27 */ | |
85 | ||
86 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
87 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
88 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
89 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
90 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
91 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
92 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
93 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
94 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ | |
d4ca31c4 | 95 | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ |
97 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
d4ca31c4 | 98 | #if 0 |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ |
100 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 | |
101 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
d4ca31c4 WD |
102 | #endif |
103 | ||
37d4bb70 JL |
104 | /* |
105 | * BOOTP options | |
106 | */ | |
107 | #define CONFIG_BOOTP_SUBNETMASK | |
108 | #define CONFIG_BOOTP_GATEWAY | |
109 | #define CONFIG_BOOTP_HOSTNAME | |
110 | #define CONFIG_BOOTP_BOOTPATH | |
111 | #define CONFIG_BOOTP_BOOTFILESIZE | |
112 | ||
f12e568c WD |
113 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
114 | ||
2694690e JL |
115 | /* |
116 | * Command line configuration. | |
117 | */ | |
f12e568c | 118 | |
29f8f58f WD |
119 | #define CONFIG_NETCONSOLE |
120 | ||
f12e568c WD |
121 | /* |
122 | * Miscellaneous configurable options | |
123 | */ | |
6d0f6bcf | 124 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
f12e568c | 125 | |
2751a95a | 126 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
f12e568c | 127 | |
2694690e | 128 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 129 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
f12e568c | 130 | #else |
6d0f6bcf | 131 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
f12e568c | 132 | #endif |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
134 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
135 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
f12e568c | 136 | |
6d0f6bcf JCPV |
137 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
138 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
f12e568c | 139 | |
6d0f6bcf | 140 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
f12e568c | 141 | |
f12e568c WD |
142 | /* |
143 | * Low Level Configuration Settings | |
144 | * (address mappings, register initial values, etc.) | |
145 | * You should know what you are doing if you make changes here. | |
146 | */ | |
147 | /*----------------------------------------------------------------------- | |
148 | * Internal Memory Mapped Register | |
149 | */ | |
6d0f6bcf | 150 | #define CONFIG_SYS_IMMR 0xFFF00000 |
f12e568c WD |
151 | |
152 | /*----------------------------------------------------------------------- | |
153 | * Definitions for initial stack pointer and data area (in DPRAM) | |
154 | */ | |
6d0f6bcf | 155 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 156 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 157 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 158 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
f12e568c WD |
159 | |
160 | /*----------------------------------------------------------------------- | |
161 | * Start addresses for the final memory configuration | |
162 | * (Set up by the startup code) | |
6d0f6bcf | 163 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
f12e568c | 164 | */ |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
166 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
167 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
168 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
169 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
f12e568c WD |
170 | |
171 | /* | |
172 | * For booting Linux, the board info and command line data | |
173 | * have to be in the first 8 MB of memory, since this is | |
174 | * the maximum mapped by the Linux kernel during initialization. | |
175 | */ | |
6d0f6bcf | 176 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
f12e568c WD |
177 | |
178 | /*----------------------------------------------------------------------- | |
179 | * FLASH organization | |
180 | */ | |
f12e568c | 181 | |
e318d9e9 | 182 | /* use CFI flash driver */ |
6d0f6bcf | 183 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 184 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
186 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
187 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
188 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
189 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
f12e568c | 190 | |
5a1aceb0 | 191 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
192 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
193 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ | |
194 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ | |
f12e568c WD |
195 | |
196 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
197 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
198 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
f12e568c | 199 | |
6d0f6bcf | 200 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
67c31036 | 201 | |
7c803be2 WD |
202 | #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
203 | ||
29f8f58f WD |
204 | /*----------------------------------------------------------------------- |
205 | * Dynamic MTD partition support | |
206 | */ | |
68d7d651 | 207 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
208 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
209 | #define CONFIG_FLASH_CFI_MTD | |
29f8f58f WD |
210 | #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" |
211 | ||
212 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ | |
213 | "128k(dtb)," \ | |
214 | "1920k(kernel)," \ | |
215 | "5632(rootfs)," \ | |
cd82919e | 216 | "4m(data)" |
29f8f58f | 217 | |
f12e568c WD |
218 | /*----------------------------------------------------------------------- |
219 | * Hardware Information Block | |
220 | */ | |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
222 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
223 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
f12e568c WD |
224 | |
225 | /*----------------------------------------------------------------------- | |
226 | * Cache Configuration | |
227 | */ | |
6d0f6bcf | 228 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
2694690e | 229 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 230 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
f12e568c WD |
231 | #endif |
232 | ||
233 | /*----------------------------------------------------------------------- | |
234 | * SYPCR - System Protection Control 11-9 | |
235 | * SYPCR can only be written once after reset! | |
236 | *----------------------------------------------------------------------- | |
237 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
238 | */ | |
239 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 240 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
f12e568c WD |
241 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
242 | #else | |
6d0f6bcf | 243 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
f12e568c WD |
244 | #endif |
245 | ||
246 | /*----------------------------------------------------------------------- | |
247 | * SIUMCR - SIU Module Configuration 11-6 | |
248 | *----------------------------------------------------------------------- | |
249 | * PCMCIA config., multi-function pin tri-state | |
250 | */ | |
251 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 252 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
f12e568c | 253 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 254 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
f12e568c WD |
255 | #endif /* CONFIG_CAN_DRIVER */ |
256 | ||
257 | /*----------------------------------------------------------------------- | |
258 | * TBSCR - Time Base Status and Control 11-26 | |
259 | *----------------------------------------------------------------------- | |
260 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
261 | */ | |
6d0f6bcf | 262 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
f12e568c WD |
263 | |
264 | /*----------------------------------------------------------------------- | |
265 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
266 | *----------------------------------------------------------------------- | |
267 | */ | |
6d0f6bcf | 268 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
f12e568c WD |
269 | |
270 | /*----------------------------------------------------------------------- | |
271 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
272 | *----------------------------------------------------------------------- | |
273 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
274 | */ | |
6d0f6bcf | 275 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
f12e568c WD |
276 | |
277 | /*----------------------------------------------------------------------- | |
278 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
279 | *----------------------------------------------------------------------- | |
280 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
281 | * interrupt status bit | |
f12e568c | 282 | */ |
6d0f6bcf | 283 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
f12e568c WD |
284 | |
285 | /*----------------------------------------------------------------------- | |
286 | * SCCR - System Clock and reset Control Register 15-27 | |
287 | *----------------------------------------------------------------------- | |
288 | * Set clock output, timebase and RTC source and divider, | |
289 | * power management and some other internal clocks | |
290 | */ | |
291 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 292 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
f12e568c WD |
293 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
294 | SCCR_DFALCD00) | |
f12e568c WD |
295 | |
296 | /*----------------------------------------------------------------------- | |
297 | * PCMCIA stuff | |
298 | *----------------------------------------------------------------------- | |
299 | * | |
300 | */ | |
6d0f6bcf JCPV |
301 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
302 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
303 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
304 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
305 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
306 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
307 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
308 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
f12e568c WD |
309 | |
310 | /*----------------------------------------------------------------------- | |
311 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
312 | *----------------------------------------------------------------------- | |
313 | */ | |
314 | ||
8d1165e1 | 315 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
f12e568c WD |
316 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
317 | ||
318 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
319 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
320 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
321 | ||
6d0f6bcf JCPV |
322 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
323 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
f12e568c | 324 | |
6d0f6bcf | 325 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
f12e568c | 326 | |
6d0f6bcf | 327 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
f12e568c WD |
328 | |
329 | /* Offset for data I/O */ | |
6d0f6bcf | 330 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
f12e568c WD |
331 | |
332 | /* Offset for normal register accesses */ | |
6d0f6bcf | 333 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
f12e568c WD |
334 | |
335 | /* Offset for alternate registers */ | |
6d0f6bcf | 336 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
f12e568c WD |
337 | |
338 | /*----------------------------------------------------------------------- | |
339 | * | |
340 | *----------------------------------------------------------------------- | |
341 | * | |
342 | */ | |
6d0f6bcf | 343 | #define CONFIG_SYS_DER 0 |
f12e568c WD |
344 | |
345 | /* | |
346 | * Init Memory Controller: | |
347 | * | |
348 | * BR0/1 and OR0/1 (FLASH) | |
349 | */ | |
350 | ||
351 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
352 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
353 | ||
354 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
355 | * restrict access enough to keep SRAM working (if any) | |
356 | * but not too much to meddle with FLASH accesses | |
357 | */ | |
6d0f6bcf JCPV |
358 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
359 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
f12e568c WD |
360 | |
361 | /* | |
362 | * FLASH timing: | |
363 | */ | |
6d0f6bcf | 364 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
f12e568c | 365 | OR_SCY_3_CLK | OR_EHTR | OR_BI) |
f12e568c | 366 | |
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
368 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
369 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
f12e568c | 370 | |
6d0f6bcf JCPV |
371 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
372 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
373 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
f12e568c WD |
374 | |
375 | /* | |
376 | * BR2/3 and OR2/3 (SDRAM) | |
377 | * | |
378 | */ | |
379 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
380 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
381 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
382 | ||
383 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 384 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
f12e568c | 385 | |
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
387 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
f12e568c WD |
388 | |
389 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf JCPV |
390 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
391 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
f12e568c | 392 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
6d0f6bcf JCPV |
393 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
394 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
395 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
396 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
f12e568c WD |
397 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
398 | #endif /* CONFIG_CAN_DRIVER */ | |
399 | ||
400 | /* | |
401 | * Memory Periodic Timer Prescaler | |
402 | * | |
403 | * The Divider for PTA (refresh timer) configuration is based on an | |
404 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
405 | * the number of chip selects (NCS) and the actually needed refresh | |
406 | * rate is done by setting MPTPR. | |
407 | * | |
408 | * PTA is calculated from | |
409 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
410 | * | |
411 | * gclk CPU clock (not bus clock!) | |
412 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
413 | * | |
414 | * 4096 Rows from SDRAM example configuration | |
415 | * 1000 factor s -> ms | |
416 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
417 | * 4 Number of refresh cycles per period | |
418 | * 64 Refresh cycle in ms per number of rows | |
419 | * -------------------------------------------- | |
420 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
421 | * | |
422 | * 50 MHz => 50.000.000 / Divider = 98 | |
423 | * 66 Mhz => 66.000.000 / Divider = 129 | |
424 | * 80 Mhz => 80.000.000 / Divider = 156 | |
425 | */ | |
e9132ea9 | 426 | |
6d0f6bcf JCPV |
427 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
428 | #define CONFIG_SYS_MAMR_PTA 98 | |
f12e568c WD |
429 | |
430 | /* | |
431 | * For 16 MBit, refresh rates could be 31.3 us | |
432 | * (= 64 ms / 2K = 125 / quad bursts). | |
433 | * For a simpler initialization, 15.6 us is used instead. | |
434 | * | |
6d0f6bcf JCPV |
435 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
436 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
f12e568c | 437 | */ |
6d0f6bcf JCPV |
438 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
439 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
f12e568c WD |
440 | |
441 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
442 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
443 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
f12e568c WD |
444 | |
445 | /* | |
446 | * MAMR settings for SDRAM | |
447 | */ | |
448 | ||
449 | /* 8 column SDRAM */ | |
6d0f6bcf | 450 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
f12e568c WD |
451 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
452 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
453 | /* 9 column SDRAM */ | |
6d0f6bcf | 454 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
f12e568c WD |
455 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
456 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
457 | ||
f12e568c WD |
458 | #define CONFIG_SCC1_ENET |
459 | #define CONFIG_FEC_ENET | |
48690d80 | 460 | #define CONFIG_ETHPRIME "SCC" |
f12e568c | 461 | |
7026ead0 HS |
462 | #define CONFIG_HWCONFIG 1 |
463 | ||
f12e568c | 464 | #endif /* __CONFIG_H */ |