[people/ms/u-boot.git] / include / configs / TQM885D.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2006
 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC885		1	/* This is a MPC885 CPU		*/
#define CONFIG_TQM885D		1	/* ...on a TQM88D module	*/

#define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
#define CFG_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
#define CFG_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
#define CONFIG_8xx_CPUCLK_DEFAULT	66000000	/*  50 MHz - CPU default clock	*/
						/* (it will be used if there is no	*/
						/* 'cpuclk' variable with valid value)	*/

#define CFG_MEASURE_CPUCLK			/* Measure real cpu clock	*/
						/* (function measure_gclk()	*/
						/* will be called)		*/
#ifdef CFG_MEASURE_CPUCLK
#define CFG_8XX_XIN		10000000	/* measure_gclk() needs this	*/
#endif

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define CONFIG_BOOTCOUNT_LIMIT

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"bootfile=/tftpboot/TQM866M/uImage\0"				\
	"kernel_addr=40080000\0"					\
	"ramdisk_addr=40180000\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/* enable I2C and select the hardware/software driver */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/

#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
#define CFG_I2C_SLAVE		0xFE

#ifdef CONFIG_SOFT_I2C
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
#endif	/* CONFIG_SOFT_I2C */

#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C??	*/
#define CFG_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

# define CONFIG_RTC_DS1337 1
# define CFG_I2C_RTC_ADDR 0x68

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/

#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0300000	/* 1 ... 3 MB in DRAM	*/
#define CFG_ALT_MEMTEST				/* alternate, more extensive
						   memory test.*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
 * which is normally part of the default commands (CFV_CMD_DFL)
 */
#define CONFIG_LOOPW

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
#define CFG_ENV_SIZE		0x08000 /* Total Size of Environment Sector	*/
#define CFG_ENV_SECT_SIZE	0x20000 /* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef CONFIG_CAN_DRIVER
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing: Default value of OR0 after reset
 */
#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
				 OR_SCY_6_CLK | OR_TRLX)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CFG_OR1_REMAP	CFG_OR0_REMAP
#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	0x00000A00

#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef CONFIG_CAN_DRIVER
#define CFG_OR3_PRELIM	CFG_OR2_PRELIM
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * 4096	Rows from SDRAM example configuration
 * 1000	factor s -> ms
 * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
 * 4	Number of refresh cycles per period
 * 64	Refresh cycle in ms per number of rows
 */
#define CFG_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))

/*
 * Memory Periodic Timer Prescaler
 * Periodic timer for refresh, start with refresh rate for 40 MHz clock
 * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
 */
#define CFG_MAMR_PTA		39

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 10 column SDRAM */
#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/*
 * Network configuration
 */
#define CONFIG_SCC2_ENET		/* enable ethernet on SCC2 */
#define CONFIG_FEC_ENET			/* enable ethernet on FEC */
#define CONFIG_ETHER_ON_FEC1		/* ... for FEC1 */
#define CONFIG_ETHER_ON_FEC2		/* ... for FEC2 */

#if defined(CONFIG_CMD_MII)
#define CFG_DISCOVER_PHY
#endif

#define CONFIG_NET_RETRY_COUNT 1	/* reduce max. timeout before
					   switching to another netwok (if the
					   tried network is unreachable) */

#define CONFIG_ETHPRIME		"SCC ETHERNET"

#endif	/* __CONFIG_H */
Commit	Line	Data
090eb735 MK	1	/*
	2	* (C) Copyright 2000-2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2006
	6	* Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/*
	28	* board/config.h - configuration options, board specific
	29	*/
	30
	31	#ifndef __CONFIG_H
	32	#define __CONFIG_H
	33
	34	/*
	35	* High Level Configuration Options
	36	* (easy to change)
	37	*/
	38
	39	#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
	40	#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
	41
	42	#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
	43	#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
	44	#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
	45	#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */
	46	/* (it will be used if there is no */
	47	/* 'cpuclk' variable with valid value) */
	48
	49	#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */
	50	/* (function measure_gclk() */
	51	/* will be called) */
	52	#ifdef CFG_MEASURE_CPUCLK
	53	#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
	54	#endif
	55
	56	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	57
	58	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	59
	60	#define CONFIG_BOOTCOUNT_LIMIT
	61
	62	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	63
	64	#define CONFIG_BOARD_TYPES 1 /* support board types */
65
66	#define CONFIG_PREBOOT "echo;" \
67	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
68	"echo"
69
70	#undef CONFIG_BOOTARGS
71
72	#define CONFIG_EXTRA_ENV_SETTINGS \
73	"netdev=eth0\0" \
74	"nfsargs=setenv bootargs root=/dev/nfs rw " \
75	"nfsroot=${serverip}:${rootpath}\0" \
76	"ramargs=setenv bootargs root=/dev/ram rw\0" \
77	"addip=setenv bootargs ${bootargs} " \
78	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
79	":${hostname}:${netdev}:off panic=1\0" \
80	"flash_nfs=run nfsargs addip;" \
81	"bootm ${kernel_addr}\0" \
82	"flash_self=run ramargs addip;" \
83	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
84	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
85	"rootpath=/opt/eldk/ppc_8xx\0" \
86	"bootfile=/tftpboot/TQM866M/uImage\0" \
87	"kernel_addr=40080000\0" \
88	"ramdisk_addr=40180000\0" \
89	""
90	#define CONFIG_BOOTCOMMAND "run flash_self"
91
92	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
93	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
94
95	#undef CONFIG_WATCHDOG /* watchdog disabled */
96
97	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
98
99	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
100
101	/* enable I2C and select the hardware/software driver */
102	#undef CONFIG_HARD_I2C /* I2C with hardware support */
103	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
104
105	#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
106	#define CFG_I2C_SLAVE 0xFE
107
108	#ifdef CONFIG_SOFT_I2C
109	/*
110	* Software (bit-bang) I2C driver configuration
111	*/
112	#define PB_SCL 0x00000020 /* PB 26 */
113	#define PB_SDA 0x00000010 /* PB 27 */
114
115	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
116	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
117	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
118	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
119	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
120	else immr->im_cpm.cp_pbdat &= ~PB_SDA
121	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
122	else immr->im_cpm.cp_pbdat &= ~PB_SCL
123	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
124	#endif /* CONFIG_SOFT_I2C */
125
126	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
127	#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
128	#define CFG_EEPROM_PAGE_WRITE_BITS 4
129	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
130
131	# define CONFIG_RTC_DS1337 1
132	# define CFG_I2C_RTC_ADDR 0x68
133
134	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
135
136	#define CONFIG_MAC_PARTITION
137	#define CONFIG_DOS_PARTITION
138
139	#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
140
141	#define CONFIG_TIMESTAMP /* but print image timestmps */
142
2694690e JL	143
	144	/*
	145	* Command line configuration.
	146	*/
	147	#include <config_cmd_default.h>
	148
	149	#define CONFIG_CMD_ASKENV
	150	#define CONFIG_CMD_DATE
	151	#define CONFIG_CMD_DHCP
	152	#define CONFIG_CMD_EEPROM
	153	#define CONFIG_CMD_I2C
	154	#define CONFIG_CMD_IDE
	155	#define CONFIG_CMD_MII
	156	#define CONFIG_CMD_NFS
	157	#define CONFIG_CMD_PING
	158
090eb735 MK	159
	160	/*
	161	* Miscellaneous configurable options
	162	*/
	163	#define CFG_LONGHELP /* undef to save memory */
	164	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	165
2751a95a WD	166	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
2751a95a WD	167	#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
090eb735	168	#ifdef CFG_HUSH_PARSER
2751a95a	169	#define CFG_PROMPT_HUSH_PS2 "> "
090eb735 MK	170	#endif
090eb735 MK	171
2694690e	172	#if defined(CONFIG_CMD_KGDB)
090eb735 MK	173	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	174	#else
	175	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	176	#endif
	177	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	178	#define CFG_MAXARGS 16 /* max number of command args */
	179	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	180
	181	#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
	182	#define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
	183	#define CFG_ALT_MEMTEST /* alternate, more extensive
	184	memory test.*/
	185
	186	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	187
	188	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	189
	190	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	191
	192	/*
	193	* Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
	194	* which is normally part of the default commands (CFV_CMD_DFL)
	195	*/
	196	#define CONFIG_LOOPW
	197
	198	/*
	199	* Low Level Configuration Settings
	200	* (address mappings, register initial values, etc.)
	201	* You should know what you are doing if you make changes here.
	202	*/
	203	/*-----------------------------------------------------------------------
	204	* Internal Memory Mapped Register
	205	*/
	206	#define CFG_IMMR 0xFFF00000
	207
	208	/*-----------------------------------------------------------------------
	209	* Definitions for initial stack pointer and data area (in DPRAM)
	210	*/
	211	#define CFG_INIT_RAM_ADDR CFG_IMMR
	212	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	213	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	214	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	215	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	216
	217	/*-----------------------------------------------------------------------
	218	* Start addresses for the final memory configuration
	219	* (Set up by the startup code)
	220	* Please note that CFG_SDRAM_BASE _must_ start at 0
	221	*/
	222	#define CFG_SDRAM_BASE 0x00000000
	223	#define CFG_FLASH_BASE 0x40000000
	224	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	225	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	226	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	227
	228	/*
	229	* For booting Linux, the board info and command line data
	230	* have to be in the first 8 MB of memory, since this is
	231	* the maximum mapped by the Linux kernel during initialization.
	232	*/
	233	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	234
	235	/*-----------------------------------------------------------------------
	236	* FLASH organization
237	*/
238	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
239	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
240
241	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
242	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
243
244	#define CFG_ENV_IS_IN_FLASH 1
245	#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
246	#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
247	#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
248
249	/* Address and size of Redundant Environment Sector */
250	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
251	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
252
253	/*-----------------------------------------------------------------------
254	* Hardware Information Block
255	*/
256	#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
257	#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
258	#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
259
260	/*-----------------------------------------------------------------------
261	* Cache Configuration
262	*/
263	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
2694690e	264	#if defined(CONFIG_CMD_KGDB)
090eb735 MK	265	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	266	#endif
	267
	268	/*-----------------------------------------------------------------------
	269	* SYPCR - System Protection Control 11-9
	270	* SYPCR can only be written once after reset!
	271	*-----------------------------------------------------------------------
	272	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	273	*/
	274	#if defined(CONFIG_WATCHDOG)
	275	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	276	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	277	#else
	278	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	279	#endif
	280
	281	/*-----------------------------------------------------------------------
	282	* SIUMCR - SIU Module Configuration 11-6
	283	*-----------------------------------------------------------------------
	284	* PCMCIA config., multi-function pin tri-state
	285	*/
	286	#ifndef CONFIG_CAN_DRIVER
	287	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	288	#else /* we must activate GPL5 in the SIUMCR for CAN */
	289	#define CFG_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	290	#endif /* CONFIG_CAN_DRIVER */
	291
	292	/*-----------------------------------------------------------------------
	293	* TBSCR - Time Base Status and Control 11-26
	294	*-----------------------------------------------------------------------
	295	* Clear Reference Interrupt Status, Timebase freezing enabled
	296	*/
	297	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	298
	299	/*-----------------------------------------------------------------------
	300	* PISCR - Periodic Interrupt Status and Control 11-31
	301	*-----------------------------------------------------------------------
	302	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	303	*/
	304	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	305
	306	/*-----------------------------------------------------------------------
	307	* SCCR - System Clock and reset Control Register 15-27
	308	*-----------------------------------------------------------------------
	309	* Set clock output, timebase and RTC source and divider,
	310	* power management and some other internal clocks
	311	*/
	312	#define SCCR_MASK SCCR_EBDF11
	313	#define CFG_SCCR (SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	314	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	315	SCCR_DFALCD00)
	316
	317	/*-----------------------------------------------------------------------
	318	* PCMCIA stuff
	319	*-----------------------------------------------------------------------
	320	*
	321	*/
	322	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
	323	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
	324	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
	325	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
	326	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
	327	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	328	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
329	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
330
331	/*-----------------------------------------------------------------------
332	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
333	*-----------------------------------------------------------------------
334	*/
335
336	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
337
338	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
339	#undef CONFIG_IDE_LED /* LED for ide not supported */
340	#undef CONFIG_IDE_RESET /* reset for ide not supported */
341
342	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
343	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
344
345	#define CFG_ATA_IDE0_OFFSET 0x0000
346
347	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
348
349	/* Offset for data I/O */
350	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
351
352	/* Offset for normal register accesses */
353	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
354
355	/* Offset for alternate registers */
356	#define CFG_ATA_ALT_OFFSET 0x0100
357
358	/*-----------------------------------------------------------------------
359	*
360	*-----------------------------------------------------------------------
361	*
362	*/
363	#define CFG_DER 0
364
365	/*
366	* Init Memory Controller:
367	*
368	* BR0/1 and OR0/1 (FLASH)
369	*/
370
371	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
372	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
373
374	/* used to re-map FLASH both when starting from SRAM or FLASH:
375	* restrict access enough to keep SRAM working (if any)
376	* but not too much to meddle with FLASH accesses
377	*/
378	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
379	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
380
381	/*
382	* FLASH timing: Default value of OR0 after reset
383	*/
384	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_MSK \| OR_BI \| \
385	OR_SCY_6_CLK \| OR_TRLX)
386
387	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
388	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
389	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
390
391	#define CFG_OR1_REMAP CFG_OR0_REMAP
392	#define CFG_OR1_PRELIM CFG_OR0_PRELIM
393	#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
394
395	/*
396	* BR2/3 and OR2/3 (SDRAM)
397	*
398	*/
399	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
400	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
401	#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
402
403	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
404	#define CFG_OR_TIMING_SDRAM 0x00000A00
405
406	#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_SDRAM )
407	#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
408
409	#ifndef CONFIG_CAN_DRIVER
410	#define CFG_OR3_PRELIM CFG_OR2_PRELIM
411	#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
412	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
413	#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
414	#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
415	#define CFG_OR3_CAN (CFG_CAN_OR_AM \| OR_G5LA \| OR_BI)
416	#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) \| \
417	BR_PS_8 \| BR_MS_UPMB \| BR_V )
418	#endif /* CONFIG_CAN_DRIVER */
419
420	/*
421	* 4096 Rows from SDRAM example configuration
422	* 1000 factor s -> ms
423	* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
424	* 4 Number of refresh cycles per period
425	* 64 Refresh cycle in ms per number of rows
426	*/
427	#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
428
429	/*
430	* Memory Periodic Timer Prescaler
431	* Periodic timer for refresh, start with refresh rate for 40 MHz clock
432	* (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
433	*/
434	#define CFG_MAMR_PTA 39
435
436	/*
437	* For 16 MBit, refresh rates could be 31.3 us
438	* (= 64 ms / 2K = 125 / quad bursts).
439	* For a simpler initialization, 15.6 us is used instead.
440	*
441	* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
442	* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
443	*/
444	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
445	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
446
447	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
448	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
449	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
450
451	/*
452	* MAMR settings for SDRAM
453	*/
454
455	/* 8 column SDRAM */
456	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
457	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
458	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
459	/* 9 column SDRAM */
460	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
461	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
462	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
463	/* 10 column SDRAM */
464	#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
465	MAMR_AMA_TYPE_2 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A9 \| \
466	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
467
468	/*
469	* Internal Definitions
470	*
471	* Boot Flags
472	*/
473	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
474	#define BOOTFLAG_WARM 0x02 /* Software reboot */
475
476	/*
477	* Network configuration
478	*/
479	#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
480	#define CONFIG_FEC_ENET /* enable ethernet on FEC */
481	#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
482	#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
483
2694690e	484	#if defined(CONFIG_CMD_MII)
090eb735 MK	485	#define CFG_DISCOVER_PHY
	486	#endif
	487
	488	#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
	489	switching to another netwok (if the
	490	tried network is unreachable) */
	491
	492	#define CONFIG_ETHPRIME "SCC ETHERNET"
	493
	494	#endif /* __CONFIG_H */