]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/VCMA9.h
cmd: Convert CONFIG_CMD_ELF to Kconfig
[people/ms/u-boot.git] / include / configs / VCMA9.h
CommitLineData
1cb8e980 1/*
531716e1 2 * (C) Copyright 2002, 2003
1cb8e980
WD
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
792a09eb 5 * Gary Jennejohn <garyj@denx.de>
1cb8e980
WD
6 * David Mueller <d.mueller@elsoft.ch>
7 *
8 * Configuation settings for the MPL VCMA9 board.
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
1cb8e980
WD
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
c686537f
DMEA
16
17#define MACH_TYPE_MPL_VCMA9 227
18
1cb8e980
WD
19/*
20 * High Level Configuration Options
21 * (easy to change)
22 */
f2168440 23#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
f3108304
DMEA
24#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
25#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
c686537f 26#define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */
1cb8e980 27
0bf42fec
DMEA
28#define CONFIG_SYS_TEXT_BASE 0x0
29
13bd4d87
DMEA
30#define CONFIG_SYS_GENERIC_BOARD
31
f3108304 32#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
1cb8e980 33
f3108304
DMEA
34/* input clock of PLL (VCMA9 has 12MHz input clock) */
35#define CONFIG_SYS_CLK_FREQ 12000000
1cb8e980 36
f3108304
DMEA
37#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
38#define CONFIG_SETUP_MEMORY_TAGS
39#define CONFIG_INITRD_TAG
a5562901 40
a1aa0bb5
JL
41/*
42 * BOOTP options
43 */
44#define CONFIG_BOOTP_BOOTFILESIZE
45#define CONFIG_BOOTP_BOOTPATH
46#define CONFIG_BOOTP_GATEWAY
47#define CONFIG_BOOTP_HOSTNAME
48
a5562901
JL
49/*
50 * Command line configuration.
51 */
a5562901
JL
52#define CONFIG_CMD_CACHE
53#define CONFIG_CMD_EEPROM
54#define CONFIG_CMD_I2C
55#define CONFIG_CMD_USB
56#define CONFIG_CMD_REGINFO
a5562901 57#define CONFIG_CMD_DATE
a5562901
JL
58#define CONFIG_CMD_DHCP
59#define CONFIG_CMD_PING
60#define CONFIG_CMD_BSP
f3108304 61#define CONFIG_CMD_NAND
a5562901 62
9660e442 63#define CONFIG_BOARD_LATE_INIT
1cb8e980 64
6d0f6bcf 65#define CONFIG_SYS_HUSH_PARSER
f3108304
DMEA
66#define CONFIG_CMDLINE_EDITING
67
68/*
1cb8e980
WD
69 * I2C stuff:
70 * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
71 * address 0x50 with 16bit addressing
f3108304 72 */
2d8f1e27 73#define CONFIG_SYS_I2C
1cb8e980 74
f3108304 75/* we use the built-in I2C controller */
2d8f1e27
PW
76#define CONFIG_SYS_I2C_S3C24X0
77#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */
78#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */
f3108304 79
6d0f6bcf
JCPV
80#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
81#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
f3108304
DMEA
82/* use EEPROM for environment vars */
83#define CONFIG_ENV_IS_IN_EEPROM 1
84/* environment starts at offset 0 */
85#define CONFIG_ENV_OFFSET 0x000
86/* 2KB should be more than enough */
87#define CONFIG_ENV_SIZE 0x800
1cb8e980 88
6d0f6bcf 89#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
f3108304
DMEA
90/* 64 bytes page write mode on 24C256 */
91#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
6d0f6bcf 92#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
1cb8e980 93
1cb8e980
WD
94/*
95 * Hardware drivers
96 */
f3108304
DMEA
97#define CONFIG_CS8900 /* we have a CS8900 on-board */
98#define CONFIG_CS8900_BASE 0x20000300
99#define CONFIG_CS8900_BUS16
1cb8e980
WD
100
101/*
102 * select serial console configuration
103 */
300f99f4 104#define CONFIG_S3C24X0_SERIAL
f3108304 105#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
1cb8e980 106
f3108304
DMEA
107/* USB support (currently only works with D-cache off) */
108#define CONFIG_USB_OHCI
fb24ffc0 109#define CONFIG_USB_OHCI_S3C24XX
f3108304
DMEA
110#define CONFIG_USB_KEYBOARD
111#define CONFIG_USB_STORAGE
112#define CONFIG_DOS_PARTITION
48b42616
WD
113
114/* Enable needed helper functions */
f3108304 115#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
48b42616 116
f3108304
DMEA
117/* RTC */
118#define CONFIG_RTC_S3C24X0
48b42616
WD
119
120
1cb8e980
WD
121/* allow to overwrite serial and ethaddr */
122#define CONFIG_ENV_OVERWRITE
123
f3108304 124#define CONFIG_BAUDRATE 9600
1cb8e980 125
f3108304
DMEA
126#define CONFIG_BOOTDELAY 5
127#define CONFIG_BOOT_RETRY_TIME -1
128#define CONFIG_RESET_TO_RETRY
129#define CONFIG_ZERO_BOOTDELAY_CHECK
a2663ea4 130
f3108304
DMEA
131#define CONFIG_NETMASK 255.255.255.0
132#define CONFIG_IPADDR 10.0.0.110
133#define CONFIG_SERVERIP 10.0.0.1
1cb8e980 134
a5562901 135#if defined(CONFIG_CMD_KGDB)
f3108304
DMEA
136/* speed to run kgdb serial port */
137#define CONFIG_KGDB_BAUDRATE 115200
1cb8e980
WD
138#endif
139
f3108304
DMEA
140/* Miscellaneous configurable options */
141#define CONFIG_SYS_LONGHELP /* undef to save memory */
f3108304
DMEA
142#define CONFIG_SYS_CBSIZE 256
143/* Print Buffer Size */
144#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
145#define CONFIG_SYS_MAXARGS 16
146/* Boot Argument Buffer Size */
147#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
148
3d3206f1 149#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
f3108304 150#define CONFIG_DISPLAY_BOARDINFO /* Display board info */
1cb8e980 151
f3108304
DMEA
152#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
153#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */
531716e1 154
6d0f6bcf 155#define CONFIG_SYS_ALT_MEMTEST
f3108304 156#define CONFIG_SYS_LOAD_ADDR 0x30800000
1cb8e980 157
f3108304 158/* we configure PWM Timer 4 to 1ms 1000Hz */
1cb8e980 159
f3108304
DMEA
160/* support additional compression methods */
161#define CONFIG_BZIP2
162#define CONFIG_LZO
163#define CONFIG_LZMA
a2663ea4 164
f3108304 165/* Ident */
48b42616
WD
166/*#define VERSION_TAG "released"*/
167#define VERSION_TAG "unstable"
f3108304
DMEA
168#define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \
169 "MEV-10080-001 " VERSION_TAG
48b42616 170
f3108304
DMEA
171/* Physical Memory Map */
172#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
173#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
174#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
1cb8e980 175
6d754843 176#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
1cb8e980 177
f3108304 178/* FLASH and environment organization */
1cb8e980 179
6d754843
DMEA
180#define CONFIG_SYS_FLASH_CFI
181#define CONFIG_FLASH_CFI_DRIVER
182#define CONFIG_FLASH_CFI_LEGACY
183#define CONFIG_SYS_FLASH_LEGACY_512Kx16
184#define CONFIG_FLASH_SHOW_PROGRESS 45
6d0f6bcf 185#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
f3108304 186#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
6d754843 187#define CONFIG_SYS_MAX_FLASH_SECT (19)
1cb8e980 188
f3108304
DMEA
189/*
190 * Size of malloc() pool
191 * BZIP2 / LZO / LZMA need a lot of RAM
192 */
193#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
194#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
195#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
1cb8e980 196
f3108304
DMEA
197/* NAND configuration */
198#ifdef CONFIG_CMD_NAND
199#define CONFIG_NAND_S3C2410
200#define CONFIG_SYS_S3C2410_NAND_HWECC
201#define CONFIG_SYS_MAX_NAND_DEVICE 1
f3108304
DMEA
202#define CONFIG_SYS_NAND_BASE 0x4E000000
203#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
204#define CONFIG_S3C24XX_TACLS 1
205#define CONFIG_S3C24XX_TWRPH0 5
206#define CONFIG_S3C24XX_TWRPH1 3
207#endif
48b42616 208
f3108304 209#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
48b42616 210
f3108304
DMEA
211/* File system */
212#define CONFIG_CMD_FAT
f3108304
DMEA
213#define CONFIG_CMD_UBI
214#define CONFIG_CMD_UBIFS
215#define CONFIG_CMD_JFFS2
216#define CONFIG_YAFFS2
217#define CONFIG_RBTREE
218#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
219#define CONFIG_MTD_PARTITIONS
220#define CONFIG_CMD_MTDPARTS
221#define CONFIG_LZO
48b42616 222
d2d94571
DMEA
223#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
224#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
225 GENERATED_GBL_DATA_SIZE)
226
f3108304 227#define CONFIG_BOARD_EARLY_INIT_F
d2d94571 228
f3108304 229#endif /* __CONFIG_H */