[people/ms/u-boot.git] / include / configs / VOH405.h

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_VOH405		1	/* ...on a VOH405 board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#undef	CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_NET_MULTI	1
#undef  CONFIG_HAS_ETH1

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_SUPPORT_VFAT

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
#define CFG_BASE_BAUD       691200
#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * NAND-FLASH stuff
 *-----------------------------------------------------------------------
 */
#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
#define NAND_MAX_CHIPS          1
#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
#define NAND_BIG_DELAY_US	25

#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */

#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
#define CFG_NAND_QUIET          1

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */

#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define CFG_IDE_MAXBUS		2		/* max. 2 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	0xF0100000
#define CFG_ATA_IDE0_OFFSET	0x0000
#define CFG_ATA_IDE1_OFFSET	0x0010

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFF80000
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CFG_MALLOC_LEN		(2 * 1024*1024)	/* Reserve 2 MB for malloc()	*/

#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
# define CFG_RAMBOOT		1
#else
# undef CFG_RAMBOOT
#endif

/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC16 is 2048 bytes */

#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
#define CFG_EEPROM_WREN         1

/* CAT24WC32/64... */
#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
					/* 32 byte page write mode using*/
					/* last 5 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
#define VGA_BA		0xF1000000	    /* Epson VGA Base Address		*/
#define CFG_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
#define CFG_EBC_PB0AP		0x92015480
/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
#define CFG_EBC_PB1AP		0x92015480
#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 4 (Epson VGA) initialization					*/
#define CFG_EBC_PB4AP	0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
#define CFG_EBC_PB4CR	VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */

/*-----------------------------------------------------------------------
 * LCD Setup
 */

#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
#define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
#define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */

#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)

/*-----------------------------------------------------------------------
 * FPGA stuff
 */

#define CFG_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/

/* FPGA internal regs */
#define CFG_FPGA_CTRL		0x000

/* FPGA Control Reg */
#define CFG_FPGA_CTRL_CF_RESET	0x0001
#define CFG_FPGA_CTRL_WDI	0x0002
#define CFG_FPGA_CTRL_PS2_RESET 0x0020

#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/

/* FPGA program pin configuration */
#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/

#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * GPIO0[0]	- External Bus Controller BLAST output
 * GPIO0[1-9]	- Instruction trace outputs -> GPIO
 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[24-27] - UART0 control signal inputs/outputs
 * GPIO0[28-29] - UART1 data signal input/output
 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
 */
#define CFG_GPIO0_OSRH		0x00000550
#define CFG_GPIO0_OSRL		0x00000110
#define CFG_GPIO0_ISR1H		0x00000000
#define CFG_GPIO0_ISR1L		0x15555440
#define CFG_GPIO0_TSRH		0x00000000
#define CFG_GPIO0_TSRL		0x00000000
#define CFG_GPIO0_TCR		0x777E0017

#define CFG_DUART_RST		(0x80000000 >> 14)
#define CFG_LCD_ENDIAN		(0x80000000 >> 7)
#define CFG_IIC_ON		(0x80000000 >> 8)
#define CFG_LCD0_RST		(0x80000000 >> 30)
#define CFG_LCD1_RST		(0x80000000 >> 31)
#define CFG_EEPROM_WP		(0x80000000 >> 0)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/*
 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 * This value will be set if iic boot eprom is disabled.
 */
#if 1
#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
#endif
#if 0
#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
#endif
#if 0
#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
13fdf8a6 SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
c837dcb1 WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	38	#define CONFIG_VOH405 1 /* ...on a VOH405 board */
13fdf8a6	39
c837dcb1 WD	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c837dcb1 WD	41	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
13fdf8a6	42
a20b27a3	43	#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
13fdf8a6 SR	44
	45	#define CONFIG_BAUDRATE 9600
	46	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	47
	48	#undef CONFIG_BOOTARGS
a20b27a3 SR	49	#undef CONFIG_BOOTCOMMAND
	50
	51	#define CONFIG_PREBOOT /* enable preboot variable */
	52
13fdf8a6 SR	53	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
13fdf8a6 SR	54
b56bd0fc MF	55	#define CONFIG_NET_MULTI 1
	56	#undef CONFIG_HAS_ETH1
	57
13fdf8a6	58	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	59	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	60	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
b56bd0fc	61	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
a20b27a3 SR	62
a20b27a3 SR	63	#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
13fdf8a6	64
a5562901	65
a1aa0bb5 JL	66	/*
	67	* BOOTP options
	68	*/
	69	#define CONFIG_BOOTP_BOOTFILESIZE
	70	#define CONFIG_BOOTP_BOOTPATH
	71	#define CONFIG_BOOTP_GATEWAY
	72	#define CONFIG_BOOTP_HOSTNAME
	73
	74
a5562901 JL	75	/*
	76	* Command line configuration.
	77	*/
	78	#include <config_cmd_default.h>
	79
	80	#define CONFIG_CMD_DHCP
	81	#define CONFIG_CMD_PCI
	82	#define CONFIG_CMD_IRQ
	83	#define CONFIG_CMD_IDE
	84	#define CONFIG_CMD_FAT
	85	#define CONFIG_CMD_ELF
	86	#define CONFIG_CMD_NAND
	87	#define CONFIG_CMD_DATE
	88	#define CONFIG_CMD_I2C
	89	#define CONFIG_CMD_MII
	90	#define CONFIG_CMD_PING
	91	#define CONFIG_CMD_EEPROM
	92
13fdf8a6 SR	93
	94	#define CONFIG_MAC_PARTITION
	95	#define CONFIG_DOS_PARTITION
	96
a20b27a3 SR	97	#define CONFIG_SUPPORT_VFAT
a20b27a3 SR	98
c837dcb1	99	#undef CONFIG_WATCHDOG /* watchdog disabled */
13fdf8a6	100
c837dcb1 WD	101	#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
c837dcb1 WD	102	#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
13fdf8a6	103
c837dcb1	104	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
13fdf8a6 SR	105
	106	/*
	107	* Miscellaneous configurable options
	108	*/
	109	#define CFG_LONGHELP /* undef to save memory */
	110	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	111
	112	#undef CFG_HUSH_PARSER /* use "hush" command parser */
	113	#ifdef CFG_HUSH_PARSER
c837dcb1	114	#define CFG_PROMPT_HUSH_PS2 "> "
13fdf8a6 SR	115	#endif
13fdf8a6 SR	116
a5562901	117	#if defined(CONFIG_CMD_KGDB)
c837dcb1	118	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
13fdf8a6	119	#else
c837dcb1	120	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
13fdf8a6 SR	121	#endif
	122	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	123	#define CFG_MAXARGS 16 /* max number of command args */
	124	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	125
c837dcb1	126	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
13fdf8a6	127
c837dcb1	128	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
13fdf8a6	129
a20b27a3 SR	130	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
a20b27a3 SR	131
13fdf8a6 SR	132	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	133	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	134
a20b27a3 SR	135	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	136	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	137	#define CFG_BASE_BAUD 691200
	138	#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
13fdf8a6 SR	139
13fdf8a6 SR	140	/* The following table includes the supported baudrates */
c837dcb1	141	#define CFG_BAUDRATE_TABLE \
13fdf8a6 SR	142	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	143	57600, 115200, 230400, 460800, 921600 }
	144
	145	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	146	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	147
c837dcb1	148	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
13fdf8a6 SR	149
	150	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	151
c837dcb1	152	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
13fdf8a6	153
c837dcb1	154	#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
13fdf8a6 SR	155
	156	/*-----------------------------------------------------------------------
	157	* NAND-FLASH stuff
	158	*-----------------------------------------------------------------------
	159	*/
bd84ee4c MF	160	#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
	161	#define NAND_MAX_CHIPS 1
	162	#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
	163	#define NAND_BIG_DELAY_US 25
	164
	165	#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
	166	#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
	167	#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
	168	#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
13fdf8a6	169
c750d2e6 MF	170	#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
c750d2e6 MF	171	#define CFG_NAND_QUIET 1
a20b27a3	172
13fdf8a6 SR	173	/*-----------------------------------------------------------------------
	174	* PCI stuff
	175	*-----------------------------------------------------------------------
	176	*/
a20b27a3 SR	177	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	178	#define PCI_HOST_FORCE 1 /* configure as pci host */
	179	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	180
	181	#define CONFIG_PCI /* include pci support */
	182	#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
	183	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	184	/* resource configuration */
	185
	186	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	187
	188	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
	189
	190	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	191	#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	192	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	193	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	194	#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	195	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	196	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	197	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	198	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
13fdf8a6 SR	199
	200	/*-----------------------------------------------------------------------
	201	* IDE/ATA stuff
	202	*-----------------------------------------------------------------------
	203	*/
c837dcb1 WD	204	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
c837dcb1 WD	205	#undef CONFIG_IDE_LED /* no led for ide supported */
13fdf8a6 SR	206	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
13fdf8a6 SR	207
c837dcb1 WD	208	#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
c837dcb1 WD	209	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS2) / max. 2 drives per IDE bus */
13fdf8a6	210
c837dcb1 WD	211	#define CFG_ATA_BASE_ADDR 0xF0100000
	212	#define CFG_ATA_IDE0_OFFSET 0x0000
	213	#define CFG_ATA_IDE1_OFFSET 0x0010
13fdf8a6 SR	214
13fdf8a6 SR	215	#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
c837dcb1	216	#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
13fdf8a6 SR	217	#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
	218
	219	/*
	220	* For booting Linux, the board info and command line data
	221	* have to be in the first 8 MB of memory, since this is
	222	* the maximum mapped by the Linux kernel during initialization.
	223	*/
	224	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	225	/*-----------------------------------------------------------------------
	226	* FLASH organization
	227	*/
	228	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	229
	230	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	231	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	232
	233	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	234	#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
	235
c837dcb1 WD	236	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	237	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	238	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
13fdf8a6 SR	239	/*
	240	* The following defines are added for buggy IOP480 byte interface.
	241	* All other boards should use the standard values (CPCI405 etc.)
	242	*/
c837dcb1 WD	243	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	244	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	245	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
13fdf8a6	246
c837dcb1	247	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
13fdf8a6	248
13fdf8a6 SR	249	/*-----------------------------------------------------------------------
	250	* Start addresses for the final memory configuration
	251	* (Set up by the startup code)
	252	* Please note that CFG_SDRAM_BASE _must_ start at 0
	253	*/
	254	#define CFG_SDRAM_BASE 0x00000000
a20b27a3	255	#define CFG_FLASH_BASE 0xFFF80000
13fdf8a6	256	#define CFG_MONITOR_BASE TEXT_BASE
a20b27a3 SR	257	#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
a20b27a3 SR	258	#define CFG_MALLOC_LEN (2 * 10241024) / Reserve 2 MB for malloc() */
13fdf8a6 SR	259
	260	#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
	261	# define CFG_RAMBOOT 1
	262	#else
	263	# undef CFG_RAMBOOT
	264	#endif
	265
	266	/*-----------------------------------------------------------------------
	267	* Environment Variable setup
	268	*/
bb1f8b4f	269	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	270	#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	271	#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
13fdf8a6 SR	272	/* total size of a CAT24WC16 is 2048 bytes */
	273
	274	#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
c837dcb1	275	#define CFG_NVRAM_SIZE 242 /* NVRAM size */
13fdf8a6 SR	276
	277	/*-----------------------------------------------------------------------
	278	* I2C EEPROM (CAT24WC16) for environment
	279	*/
	280	#define CONFIG_HARD_I2C /* I2c with hardware support */
b56bd0fc	281	#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
13fdf8a6 SR	282	#define CFG_I2C_SLAVE 0x7F
	283
	284	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
b56bd0fc MF	285	#define CFG_EEPROM_WREN 1
b56bd0fc MF	286
13fdf8a6	287	/* CAT24WC32/64... */
c837dcb1 WD	288	#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
c837dcb1 WD	289	/* mask of address bits that overflow into the "EEPROM chip address" */
13fdf8a6 SR	290	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
	291	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
	292	/* 32 byte page write mode using*/
c837dcb1	293	/* last 5 bits of the address */
13fdf8a6 SR	294	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	295	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	296
13fdf8a6 SR	297	/*-----------------------------------------------------------------------
	298	* External Bus Controller (EBC) Setup
	299	*/
	300
c837dcb1 WD	301	#define CAN_BA 0xF0000000 /* CAN Base Address */
	302	#define DUART0_BA 0xF0000400 /* DUART Base Address */
	303	#define DUART1_BA 0xF0000408 /* DUART Base Address */
	304	#define RTC_BA 0xF0000500 /* RTC Base Address */
	305	#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
	306	#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
13fdf8a6	307
c837dcb1 WD	308	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
	309	#define CFG_EBC_PB0AP 0x92015480
	310	/#define CFG_EBC_PB0AP 0x08055880 /XXX TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
	311	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
13fdf8a6	312
c837dcb1 WD	313	/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
	314	#define CFG_EBC_PB1AP 0x92015480
	315	#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
13fdf8a6	316
c837dcb1 WD	317	/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
	318	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	319	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
13fdf8a6	320
c837dcb1 WD	321	/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
	322	#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	323	#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
13fdf8a6	324
c837dcb1 WD	325	/* Memory Bank 4 (Epson VGA) initialization */
	326	#define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
	327	#define CFG_EBC_PB4CR VGA_BA \| 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
13fdf8a6	328
a20b27a3 SR	329	/*-----------------------------------------------------------------------
	330	* LCD Setup
	331	*/
	332
	333	#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
	334	#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
	335	#define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
	336	#define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
	337
c29ab9d7	338	#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
a20b27a3	339
13fdf8a6 SR	340	/*-----------------------------------------------------------------------
	341	* FPGA stuff
	342	*/
	343
c837dcb1	344	#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
13fdf8a6 SR	345
13fdf8a6 SR	346	/* FPGA internal regs */
c837dcb1	347	#define CFG_FPGA_CTRL 0x000
13fdf8a6 SR	348
13fdf8a6 SR	349	/* FPGA Control Reg */
c837dcb1 WD	350	#define CFG_FPGA_CTRL_CF_RESET 0x0001
c837dcb1 WD	351	#define CFG_FPGA_CTRL_WDI 0x0002
13fdf8a6 SR	352	#define CFG_FPGA_CTRL_PS2_RESET 0x0020
13fdf8a6 SR	353
c837dcb1 WD	354	#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
c837dcb1 WD	355	#define CFG_FPGA_MAX_SIZE 1281024 / 128kByte is enough for XC2S50E*/
13fdf8a6 SR	356
13fdf8a6 SR	357	/* FPGA program pin configuration */
c837dcb1 WD	358	#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	359	#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	360	#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	361	#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
	362	#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
13fdf8a6 SR	363
	364	/*-----------------------------------------------------------------------
	365	* Definitions for initial stack pointer and data area (in data cache)
	366	*/
	367	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
c837dcb1	368	#define CFG_TEMP_STACK_OCM 1
13fdf8a6 SR	369
	370	/* On Chip Memory location */
	371	#define CFG_OCM_DATA_ADDR 0xF8000000
	372	#define CFG_OCM_DATA_SIZE 0x1000
	373	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	374	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	375
	376	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	377	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	378	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
13fdf8a6 SR	379
	380	/*-----------------------------------------------------------------------
	381	* Definitions for GPIO setup (PPC405EP specific)
	382	*
c837dcb1 WD	383	* GPIO0[0] - External Bus Controller BLAST output
c837dcb1 WD	384	* GPIO0[1-9] - Instruction trace outputs -> GPIO
13fdf8a6 SR	385	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	386	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
	387	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	388	* GPIO0[24-27] - UART0 control signal inputs/outputs
	389	* GPIO0[28-29] - UART1 data signal input/output
a20b27a3	390	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
13fdf8a6	391	*/
b56bd0fc	392	#define CFG_GPIO0_OSRH 0x00000550
c837dcb1 WD	393	#define CFG_GPIO0_OSRL 0x00000110
c837dcb1 WD	394	#define CFG_GPIO0_ISR1H 0x00000000
a20b27a3	395	#define CFG_GPIO0_ISR1L 0x15555440
c837dcb1 WD	396	#define CFG_GPIO0_TSRH 0x00000000
c837dcb1 WD	397	#define CFG_GPIO0_TSRL 0x00000000
b56bd0fc	398	#define CFG_GPIO0_TCR 0x777E0017
13fdf8a6	399
c837dcb1	400	#define CFG_DUART_RST (0x80000000 >> 14)
a20b27a3	401	#define CFG_LCD_ENDIAN (0x80000000 >> 7)
b56bd0fc	402	#define CFG_IIC_ON (0x80000000 >> 8)
a20b27a3 SR	403	#define CFG_LCD0_RST (0x80000000 >> 30)
a20b27a3 SR	404	#define CFG_LCD1_RST (0x80000000 >> 31)
b56bd0fc	405	#define CFG_EEPROM_WP (0x80000000 >> 0)
13fdf8a6 SR	406
	407	/*
	408	* Internal Definitions
	409	*
	410	* Boot Flags
	411	*/
	412	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	413	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	414
	415	/*
	416	* Default speed selection (cpu_plb_opb_ebc) in mhz.
	417	* This value will be set if iic boot eprom is disabled.
	418	*/
	419	#if 1
c837dcb1 WD	420	#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
c837dcb1 WD	421	#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
13fdf8a6 SR	422	#endif
13fdf8a6 SR	423	#if 0
c837dcb1 WD	424	#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
c837dcb1 WD	425	#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
13fdf8a6 SR	426	#endif
13fdf8a6 SR	427	#if 0
c837dcb1 WD	428	#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
c837dcb1 WD	429	#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
13fdf8a6 SR	430	#endif
	431
	432	#endif /* __CONFIG_H */