[people/ms/u-boot.git] / include / configs / VoVPN-GW.h

/*
 * (C) Copyright 2004
 * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
 *
 * Support for the Elmeg VoVPN Gateway Module
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* define cpu used */
#define	CONFIG_MPC8272			1

/* define busmode: 8260 */
#undef	CONFIG_BUSMODE_60x

#define	CONFIG_SYS_TEXT_BASE		0xfff00000

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#ifdef	CONFIG_CLKIN_66MHz
#define	CONFIG_8260_CLKIN		66666666	/* in Hz */
#else
#define	CONFIG_8260_CLKIN		100000000	/* in Hz */
#endif

/* call board_early_init_f */
#define	CONFIG_BOARD_EARLY_INIT_F	1

/* have misc_init_r() function */
#define CONFIG_MISC_INIT_R		1

/* have reset_phy_r() function */
#define CONFIG_RESET_PHY_R		1

/* have special reset function */
#define	CONFIG_HAVE_OWN_RESET		1

/* allow serial and ethaddr to be overwritten */
#define	CONFIG_ENV_OVERWRITE

/* watchdog disabled */
#undef	CONFIG_WATCHDOG

/* include support for bzip2 compressed images */
#undef	CONFIG_BZIP2

/* status led */
#undef	CONFIG_STATUS_LED		/* XXX jse */

/* vendor parameter protection */
#define CONFIG_ENV_OVERWRITE

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 */
#define	CONFIG_CONS_ON_SMC
#undef	CONFIG_CONS_ON_SCC
#undef	CONFIG_CONS_NONE
#define	CONFIG_CONS_INDEX		1

/* serial port default baudrate */
#define CONFIG_BAUDRATE			115200

/* echo on for serial download	*/
#define CONFIG_LOADS_ECHO		1

/* don't allow baudrate change	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE

/* supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC
#define	CONFIG_ETHER_ON_FCC
#undef	CONFIG_ETHER_NONE

#ifdef	CONFIG_ETHER_ON_FCC

/* which SCC/FCC channel for ethernet */
#define	CONFIG_ETHER_INDEX		1

/* Marvell Switch SMI base addr */
#define CONFIG_SYS_PHY_ADDR			0x10

/* FCC1 RMII REFCLK is CLK10 */
#define CONFIG_SYS_CMXFCR_VALUE		CMXFCR_TF1CS_CLK10
#define CONFIG_SYS_CMXFCR_MASK			(CMXFCR_FC1|CMXFCR_TF1CS_MSK)

/* BDs and buffers on 60x bus */
#define CONFIG_SYS_CPMFCR_RAMTYPE		0

/* Local Protect, Full duplex, Flowcontrol, RMII */
#define CONFIG_SYS_FCC_PSMR			(FCC_PSMR_LPB|FCC_PSMR_FDE|\
					 FCC_PSMR_FCE|FCC_PSMR_RMII)

/* bit-bang MII PHY management	*/
#define CONFIG_BITBANGMII

#define MDIO_PORT			1		/* Port B */

#define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
#define MDC_DECLARE		MDIO_DECLARE

#define CONFIG_SYS_MDIO_PIN			0x00002000	/* PB18 */
#define CONFIG_SYS_MDC_PIN			0x00001000	/* PB19 */
#define MDIO_ACTIVE			(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
#define MDIO_TRISTATE			(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
#define MDIO_READ			((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
#define MDIO(bit)			if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
					else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
#define MDC(bit)			if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
					else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
#define MIIDELAY			udelay(1)

#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */

#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IMLS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SOURCE


/*
 * boot options & environment
 */
#define CONFIG_BOOTDELAY		3
#define CONFIG_BOOTCOMMAND		"run flash_self"
#undef  CONFIG_BOOTARGS
#define	CONFIG_EXTRA_ENV_SETTINGS	\
"clean_nv=erase fff20000 ffffffff\0" \
"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
"fstype=cramfs\0" \
"rootpath=/root_fs\0" \
"uboot=PPC/u-boot.bin\0" \
"kernel=PPC/uImage\0" \
"kernel_addr=ffe00000\0" \
"fs=PPC/root_fs\0" \
"console=ttyS0\0" \
"netdev=eth0\0" \
"rootdev=31:3\0" \
"ethaddr=00:09:4f:01:02:03\0" \
"ipaddr=10.0.0.201\0" \
"netmask=255.255.255.0\0" \
"serverip=10.0.0.136\0" \
"gatewayip=10.0.0.10\0" \
"hostname=bastard\0" \
""


/*
 * miscellaneous configurable options
 */

/* undef to save memory */
#define	CONFIG_SYS_LONGHELP

/* monitor command prompt */
#define	CONFIG_SYS_PROMPT			"=> "

/* console i/o buffer size */
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE			1024
#else
#define	CONFIG_SYS_CBSIZE			256
#endif

/* print buffer size */
#define	CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

/* max number of command args */
#define	CONFIG_SYS_MAXARGS			16

/* boot argument buffer size */
#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START		0x00100000
/* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_MEMTEST_END			0x00f00000
/* full featured memtest */
#define CONFIG_SYS_ALT_MEMTEST

/* default load address */
#define	CONFIG_SYS_LOAD_ADDR			0x00100000

/* decrementer freq: 1 ms ticks	*/
#define	CONFIG_SYS_HZ				1000

/* configure flash */
#define CONFIG_SYS_FLASH_BASE			0xff800000
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_MAX_FLASH_SECT		64
#define CONFIG_SYS_FLASH_SIZE			8
#undef	CONFIG_SYS_FLASH_16BIT
#define CONFIG_SYS_FLASH_ERASE_TOUT		240000
#define CONFIG_SYS_FLASH_WRITE_TOUT		500
#define CONFIG_SYS_FLASH_LOCK_TOUT		500
#define CONFIG_SYS_FLASH_UNLOCK_TOUT		10000
#define CONFIG_SYS_FLASH_PROTECTION

/* monitor in flash */
#define CONFIG_SYS_MONITOR_OFFSET		0x00700000

/* environment in flash */
#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x00020000)
#define CONFIG_ENV_SIZE			0x00020000
#define CONFIG_ENV_SECT_SIZE		0x00020000

/*
 * Initial memory map for linux
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ			(8 << 20)

/* hard reset configuration words */
#ifdef	CONFIG_CLKIN_66MHz
#define CONFIG_SYS_HRCW_MASTER			0x04643050
#else
#error NO HRCW FOR 100MHZ SPECIFIED !!!
#endif
#define CONFIG_SYS_HRCW_SLAVE1			0x00000000
#define CONFIG_SYS_HRCW_SLAVE2			0x00000000
#define CONFIG_SYS_HRCW_SLAVE3			0x00000000
#define CONFIG_SYS_HRCW_SLAVE4			0x00000000
#define CONFIG_SYS_HRCW_SLAVE5			0x00000000
#define CONFIG_SYS_HRCW_SLAVE6			0x00000000
#define CONFIG_SYS_HRCW_SLAVE7			0x00000000

/* internal memory mapped register */
#define CONFIG_SYS_IMMR			0xF0000000

/* definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE		0x2000
#define CONFIG_SYS_GBL_DATA_OFFSET		(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET		CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE			0x00000000
#define CONFIG_SYS_SDRAM_SIZE			(32*1024*1024)
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_FLASH		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
#define CONFIG_SYS_MONITOR_LEN			0x00020000
#define CONFIG_SYS_MALLOC_LEN			0x00020000

/* cache configuration */
#define CONFIG_SYS_CACHELINE_SIZE		32      /* for MPC8260 */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT		5	/* log base 2 of above */
#endif

/*
 * HIDx - Hardware Implementation-dependent Registers
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT			(HID0_ICE|HID0_DCE|\
					 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL			(HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID2			0

/* RMR - reset mode register - turn on checkstop reset enable */
#define CONFIG_SYS_RMR				RMR_CSRE

/* BCR - bus configuration */
#define CONFIG_SYS_BCR				0x00000000

/* SIUMCR - siu module configuration */
#define CONFIG_SYS_SIUMCR			0x4905c000

/* SYPCR - system protection control */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR			0xffffff87
#else
#define CONFIG_SYS_SYPCR			0xffffff83
#endif

/* TMCNTSC - time counter status and control */
/* clear interrupts XXX jse */
/*#define CONFIG_SYS_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR) */
#define CONFIG_SYS_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR|\
					 TMCNTSC_TCF|TMCNTSC_TCE)

/* PISCR - periodic interrupt status and control */
/* clear interrupts XXX jse */
/*#define CONFIG_SYS_PISCR			(PISCR_PS) */
#define CONFIG_SYS_PISCR			(PISCR_PS|PISCR_PTF|PISCR_PTE)

/* SCCR - system clock control */
#define CONFIG_SYS_SCCR			0x000001a9

/* RCCR - risc controller configuration */
#define CONFIG_SYS_RCCR			0

/*
 * MEMORY MAP
 * ----------
 * CS0 - FLASH    8MB/8Bit	base=0xff800000 (boot: 0xfe000000, 8x mirrored)
 * CS1 - SDRAM   32MB/64Bit	base=0x00000000
 * CS2 - DSP/SL1  1MB/16Bit	base=0xf0100000
 * CS3 - DSP/SL2  1MB/16Bit	base=0xf0200000
 * CS4 - DSP/SL3  1MB/16Bit	base=0xf0300000
 * CS5 - DSP/SL4  1MB/16Bit	base=0xf0400000
 * CS7 - DPRAM    1KB/8Bit	base=0xf0500000, size=32KB (32x mirrored)
 *  x  - IMMR     384KB		base=0xf0000000
 */
/* XXX jse 100MHz TODO */
#define CONFIG_SYS_BR0_PRELIM			0xff800801
#define CONFIG_SYS_OR0_PRELIM			0xff801e44
#define CONFIG_SYS_BR1_PRELIM			0x00000041
#define CONFIG_SYS_OR1_PRELIM			0xfe002ec0
#if 1
#define CONFIG_SYS_BR2_PRELIM			0xf0101001
#define CONFIG_SYS_OR2_PRELIM			0xfff00ef4
#define CONFIG_SYS_BR3_PRELIM			0xf0201001
#define CONFIG_SYS_OR3_PRELIM			0xfff00ef4
#define CONFIG_SYS_BR4_PRELIM			0xf0301001
#define CONFIG_SYS_OR4_PRELIM			0xfff00ef4
#define CONFIG_SYS_BR5_PRELIM			0xf0401001
#define CONFIG_SYS_OR5_PRELIM			0xfff00ef4
#else
#define CONFIG_SYS_BR2_PRELIM			0xf0101081
#define CONFIG_SYS_OR2_PRELIM			0xfff00104
#define CONFIG_SYS_BR3_PRELIM			0xf0201081
#define CONFIG_SYS_OR3_PRELIM			0xfff00104
#define CONFIG_SYS_BR4_PRELIM			0xf0301081
#define CONFIG_SYS_OR4_PRELIM			0xfff00104
#define CONFIG_SYS_BR5_PRELIM			0xf0401081
#define CONFIG_SYS_OR5_PRELIM			0xfff00104
#endif
#define CONFIG_SYS_BR7_PRELIM			0xf0500881
#define CONFIG_SYS_OR7_PRELIM			0xffff8104
#define CONFIG_SYS_MPTPR			0x2700
#define CONFIG_SYS_PSDMR			0x822a2452	/* optimal */
/*#define CONFIG_SYS_PSDMR			0x822a48a3 */	/* relaxed */
#define CONFIG_SYS_PSRT			0x1a

/* "bad" address */
#define	CONFIG_SYS_RESET_ADDRESS		0x40000000

#endif	/* __CONFIG_H */
Commit	Line	Data
ba91e26a WD	1	/*
	2	* (C) Copyright 2004
	3	* Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
	4	*
	5	* Support for the Elmeg VoVPN Gateway Module
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#ifndef __CONFIG_H
	24	#define __CONFIG_H
	25
	26	/* define cpu used */
	27	#define CONFIG_MPC8272 1
	28
	29	/* define busmode: 8260 */
	30	#undef CONFIG_BUSMODE_60x
	31
2ae18241 WD	32	#define CONFIG_SYS_TEXT_BASE 0xfff00000
2ae18241 WD	33
ba91e26a WD	34	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	35	#ifdef CONFIG_CLKIN_66MHz
	36	#define CONFIG_8260_CLKIN 66666666 /* in Hz */
	37	#else
	38	#define CONFIG_8260_CLKIN 100000000 /* in Hz */
	39	#endif
	40
	41	/* call board_early_init_f */
	42	#define CONFIG_BOARD_EARLY_INIT_F 1
	43
	44	/* have misc_init_r() function */
	45	#define CONFIG_MISC_INIT_R 1
	46
	47	/* have reset_phy_r() function */
	48	#define CONFIG_RESET_PHY_R 1
	49
	50	/* have special reset function */
	51	#define CONFIG_HAVE_OWN_RESET 1
	52
	53	/* allow serial and ethaddr to be overwritten */
	54	#define CONFIG_ENV_OVERWRITE
	55
	56	/* watchdog disabled */
	57	#undef CONFIG_WATCHDOG
	58
	59	/* include support for bzip2 compressed images */
	60	#undef CONFIG_BZIP2
	61
	62	/* status led */
	63	#undef CONFIG_STATUS_LED /* XXX jse */
	64
	65	/* vendor parameter protection */
	66	#define CONFIG_ENV_OVERWRITE
	67
	68	/*
	69	* select serial console configuration
	70	*
	71	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	72	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	73	* for SCC).
	74	*/
	75	#define CONFIG_CONS_ON_SMC
	76	#undef CONFIG_CONS_ON_SCC
	77	#undef CONFIG_CONS_NONE
	78	#define CONFIG_CONS_INDEX 1
	79
	80	/* serial port default baudrate */
	81	#define CONFIG_BAUDRATE 115200
	82
	83	/* echo on for serial download */
	84	#define CONFIG_LOADS_ECHO 1
	85
	86	/* don't allow baudrate change */
6d0f6bcf	87	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
ba91e26a WD	88
ba91e26a WD	89	/* supported baudrates */
6d0f6bcf	90	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
ba91e26a WD	91
	92	/*
	93	* select ethernet configuration
	94	*
	95	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	96	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	97	* for FCC)
	98	*
	99	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	100	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
ba91e26a WD	101	*/
	102	#undef CONFIG_ETHER_ON_SCC
	103	#define CONFIG_ETHER_ON_FCC
	104	#undef CONFIG_ETHER_NONE
	105
	106	#ifdef CONFIG_ETHER_ON_FCC
	107
	108	/* which SCC/FCC channel for ethernet */
	109	#define CONFIG_ETHER_INDEX 1
	110
	111	/* Marvell Switch SMI base addr */
6d0f6bcf	112	#define CONFIG_SYS_PHY_ADDR 0x10
ba91e26a WD	113
ba91e26a WD	114	/* FCC1 RMII REFCLK is CLK10 */
6d0f6bcf JCPV	115	#define CONFIG_SYS_CMXFCR_VALUE CMXFCR_TF1CS_CLK10
6d0f6bcf JCPV	116	#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1\|CMXFCR_TF1CS_MSK)
ba91e26a WD	117
ba91e26a WD	118	/* BDs and buffers on 60x bus */
6d0f6bcf	119	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
ba91e26a WD	120
ba91e26a WD	121	/* Local Protect, Full duplex, Flowcontrol, RMII */
6d0f6bcf	122	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_LPB\|FCC_PSMR_FDE\|\
ba91e26a WD	123	FCC_PSMR_FCE\|FCC_PSMR_RMII)
	124
	125	/* bit-bang MII PHY management */
	126	#define CONFIG_BITBANGMII
	127
	128	#define MDIO_PORT 1 /* Port B */
be225442 LCM	129
	130	#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
	131	(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
	132	#define MDC_DECLARE MDIO_DECLARE
	133
6d0f6bcf JCPV	134	#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PB18 */
	135	#define CONFIG_SYS_MDC_PIN 0x00001000 /* PB19 */
	136	#define MDIO_ACTIVE (iop->pdir \|= CONFIG_SYS_MDIO_PIN)
	137	#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
	138	#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
	139	#define MDIO(bit) if(bit) iop->pdat \|= CONFIG_SYS_MDIO_PIN; \
	140	else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
	141	#define MDC(bit) if(bit) iop->pdat \|= CONFIG_SYS_MDC_PIN; \
	142	else iop->pdat &= ~CONFIG_SYS_MDC_PIN
ba91e26a WD	143	#define MIIDELAY udelay(1)
	144
	145	#endif
	146
a1aa0bb5 JL	147	/*
	148	* BOOTP options
	149	*/
	150	#define CONFIG_BOOTP_BOOTFILESIZE
	151	#define CONFIG_BOOTP_BOOTPATH
	152	#define CONFIG_BOOTP_GATEWAY
	153	#define CONFIG_BOOTP_HOSTNAME
	154
	155
a5562901 JL	156	/*
	157	* Command line configuration.
	158	*/
	159
a5562901 JL	160	#define CONFIG_CMD_BDI
	161	#define CONFIG_CMD_CONSOLE
	162	#define CONFIG_CMD_ECHO
a5562901 JL	163	#define CONFIG_CMD_FLASH
	164	#define CONFIG_CMD_IMI
	165	#define CONFIG_CMD_IMLS
	166	#define CONFIG_CMD_LOADB
	167	#define CONFIG_CMD_MEMORY
	168	#define CONFIG_CMD_MISC
	169	#define CONFIG_CMD_NET
	170	#define CONFIG_CMD_PING
	171	#define CONFIG_CMD_RUN
74de7aef WD	172	#define CONFIG_CMD_SAVEENV
74de7aef WD	173	#define CONFIG_CMD_SOURCE
a5562901	174
ba91e26a WD	175
	176	/*
	177	* boot options & environment
	178	*/
	179	#define CONFIG_BOOTDELAY 3
	180	#define CONFIG_BOOTCOMMAND "run flash_self"
	181	#undef CONFIG_BOOTARGS
	182	#define CONFIG_EXTRA_ENV_SETTINGS \
	183	"clean_nv=erase fff20000 ffffffff\0" \
fe126d8b WD	184	"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
	185	"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
	186	"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
	187	"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
	188	"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
	189	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
	190	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
	191	"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
	192	"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
	193	"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
	194	"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
	195	"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
ba91e26a WD	196	"fstype=cramfs\0" \
	197	"rootpath=/root_fs\0" \
	198	"uboot=PPC/u-boot.bin\0" \
	199	"kernel=PPC/uImage\0" \
	200	"kernel_addr=ffe00000\0" \
	201	"fs=PPC/root_fs\0" \
	202	"console=ttyS0\0" \
	203	"netdev=eth0\0" \
	204	"rootdev=31:3\0" \
	205	"ethaddr=00:09:4f:01:02:03\0" \
	206	"ipaddr=10.0.0.201\0" \
	207	"netmask=255.255.255.0\0" \
	208	"serverip=10.0.0.136\0" \
	209	"gatewayip=10.0.0.10\0" \
	210	"hostname=bastard\0" \
	211	""
	212
	213
	214	/*
	215	* miscellaneous configurable options
	216	*/
	217
	218	/* undef to save memory */
6d0f6bcf	219	#define CONFIG_SYS_LONGHELP
ba91e26a WD	220
ba91e26a WD	221	/* monitor command prompt */
6d0f6bcf	222	#define CONFIG_SYS_PROMPT "=> "
ba91e26a WD	223
ba91e26a WD	224	/* console i/o buffer size */
a5562901	225	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	226	#define CONFIG_SYS_CBSIZE 1024
ba91e26a	227	#else
6d0f6bcf	228	#define CONFIG_SYS_CBSIZE 256
ba91e26a WD	229	#endif
	230
	231	/* print buffer size */
6d0f6bcf	232	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
ba91e26a WD	233
ba91e26a WD	234	/* max number of command args */
6d0f6bcf	235	#define CONFIG_SYS_MAXARGS 16
ba91e26a WD	236
ba91e26a WD	237	/* boot argument buffer size */
6d0f6bcf	238	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
ba91e26a WD	239
ba91e26a WD	240	/* memtest works on */
6d0f6bcf	241	#define CONFIG_SYS_MEMTEST_START 0x00100000
ba91e26a	242	/* 1 ... 15 MB in DRAM */
6d0f6bcf	243	#define CONFIG_SYS_MEMTEST_END 0x00f00000
ba91e26a	244	/* full featured memtest */
6d0f6bcf	245	#define CONFIG_SYS_ALT_MEMTEST
ba91e26a WD	246
ba91e26a WD	247	/* default load address */
6d0f6bcf	248	#define CONFIG_SYS_LOAD_ADDR 0x00100000
ba91e26a WD	249
ba91e26a WD	250	/* decrementer freq: 1 ms ticks */
6d0f6bcf	251	#define CONFIG_SYS_HZ 1000
ba91e26a WD	252
ba91e26a WD	253	/* configure flash */
6d0f6bcf JCPV	254	#define CONFIG_SYS_FLASH_BASE 0xff800000
	255	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	256	#define CONFIG_SYS_MAX_FLASH_SECT 64
	257	#define CONFIG_SYS_FLASH_SIZE 8
	258	#undef CONFIG_SYS_FLASH_16BIT
	259	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
	260	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
	261	#define CONFIG_SYS_FLASH_LOCK_TOUT 500
	262	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
	263	#define CONFIG_SYS_FLASH_PROTECTION
ba91e26a WD	264
ba91e26a WD	265	/* monitor in flash */
6d0f6bcf	266	#define CONFIG_SYS_MONITOR_OFFSET 0x00700000
ba91e26a WD	267
ba91e26a WD	268	/* environment in flash */
5a1aceb0	269	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	270	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00020000)
0e8d1586 JCPV	271	#define CONFIG_ENV_SIZE 0x00020000
0e8d1586 JCPV	272	#define CONFIG_ENV_SECT_SIZE 0x00020000
ba91e26a WD	273
	274	/*
	275	* Initial memory map for linux
	276	* For booting Linux, the board info and command line data
	277	* have to be in the first 8 MB of memory, since this is
	278	* the maximum mapped by the Linux kernel during initialization.
	279	*/
6d0f6bcf	280	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
ba91e26a WD	281
	282	/* hard reset configuration words */
	283	#ifdef CONFIG_CLKIN_66MHz
6d0f6bcf	284	#define CONFIG_SYS_HRCW_MASTER 0x04643050
ba91e26a WD	285	#else
	286	#error NO HRCW FOR 100MHZ SPECIFIED !!!
	287	#endif
6d0f6bcf JCPV	288	#define CONFIG_SYS_HRCW_SLAVE1 0x00000000
	289	#define CONFIG_SYS_HRCW_SLAVE2 0x00000000
	290	#define CONFIG_SYS_HRCW_SLAVE3 0x00000000
	291	#define CONFIG_SYS_HRCW_SLAVE4 0x00000000
	292	#define CONFIG_SYS_HRCW_SLAVE5 0x00000000
	293	#define CONFIG_SYS_HRCW_SLAVE6 0x00000000
	294	#define CONFIG_SYS_HRCW_SLAVE7 0x00000000
ba91e26a WD	295
ba91e26a WD	296	/* internal memory mapped register */
6d0f6bcf	297	#define CONFIG_SYS_IMMR 0xF0000000
ba91e26a WD	298
ba91e26a WD	299	/* definitions for initial stack pointer and data area (in DPRAM) */
6d0f6bcf	300	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	301	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
25ddd1fb	302	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	303	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
ba91e26a WD	304
	305	/*
	306	* Start addresses for the final memory configuration
	307	* (Set up by the startup code)
6d0f6bcf	308	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
ba91e26a	309	*/
6d0f6bcf JCPV	310	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	311	#define CONFIG_SYS_SDRAM_SIZE (3210241024)
14d0a02a	312	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	313	#define CONFIG_SYS_MONITOR_FLASH (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
	314	#define CONFIG_SYS_MONITOR_LEN 0x00020000
	315	#define CONFIG_SYS_MALLOC_LEN 0x00020000
ba91e26a	316
ba91e26a	317	/* cache configuration */
6d0f6bcf	318	#define CONFIG_SYS_CACHELINE_SIZE 32 /* for MPC8260 */
a5562901	319	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	320	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of above */
ba91e26a WD	321	#endif
	322
	323	/*
	324	* HIDx - Hardware Implementation-dependent Registers
	325	*-----------------------------------------------------------------------
	326	* HID0 also contains cache control - initially enable both caches and
	327	* invalidate contents, then the final state leaves only the instruction
	328	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	329	* but Soft reset does not.
	330	*
	331	* HID1 has only read-only information - nothing to set.
	332	*/
6d0f6bcf	333	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|\
ba91e26a	334	HID0_ICFI\|HID0_DCI\|HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	335	#define CONFIG_SYS_HID0_FINAL (HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	336	#define CONFIG_SYS_HID2 0
ba91e26a WD	337
ba91e26a WD	338	/* RMR - reset mode register - turn on checkstop reset enable */
6d0f6bcf	339	#define CONFIG_SYS_RMR RMR_CSRE
ba91e26a WD	340
ba91e26a WD	341	/* BCR - bus configuration */
6d0f6bcf	342	#define CONFIG_SYS_BCR 0x00000000
ba91e26a WD	343
ba91e26a WD	344	/* SIUMCR - siu module configuration */
6d0f6bcf	345	#define CONFIG_SYS_SIUMCR 0x4905c000
ba91e26a WD	346
	347	/* SYPCR - system protection control */
	348	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	349	#define CONFIG_SYS_SYPCR 0xffffff87
ba91e26a	350	#else
6d0f6bcf	351	#define CONFIG_SYS_SYPCR 0xffffff83
ba91e26a WD	352	#endif
	353
	354	/* TMCNTSC - time counter status and control */
	355	/* clear interrupts XXX jse */
6d0f6bcf JCPV	356	/#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR) /
6d0f6bcf JCPV	357	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|\
ba91e26a WD	358	TMCNTSC_TCF\|TMCNTSC_TCE)
	359
	360	/* PISCR - periodic interrupt status and control */
	361	/* clear interrupts XXX jse */
6d0f6bcf JCPV	362	/#define CONFIG_SYS_PISCR (PISCR_PS) /
6d0f6bcf JCPV	363	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
ba91e26a WD	364
ba91e26a WD	365	/* SCCR - system clock control */
6d0f6bcf	366	#define CONFIG_SYS_SCCR 0x000001a9
ba91e26a WD	367
ba91e26a WD	368	/* RCCR - risc controller configuration */
6d0f6bcf	369	#define CONFIG_SYS_RCCR 0
ba91e26a WD	370
	371	/*
	372	* MEMORY MAP
	373	* ----------
53677ef1	374	* CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
ba91e26a WD	375	* CS1 - SDRAM 32MB/64Bit base=0x00000000
	376	* CS2 - DSP/SL1 1MB/16Bit base=0xf0100000
	377	* CS3 - DSP/SL2 1MB/16Bit base=0xf0200000
	378	* CS4 - DSP/SL3 1MB/16Bit base=0xf0300000
	379	* CS5 - DSP/SL4 1MB/16Bit base=0xf0400000
	380	* CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored)
	381	* x - IMMR 384KB base=0xf0000000
	382	*/
	383	/* XXX jse 100MHz TODO */
6d0f6bcf JCPV	384	#define CONFIG_SYS_BR0_PRELIM 0xff800801
	385	#define CONFIG_SYS_OR0_PRELIM 0xff801e44
	386	#define CONFIG_SYS_BR1_PRELIM 0x00000041
	387	#define CONFIG_SYS_OR1_PRELIM 0xfe002ec0
ba91e26a	388	#if 1
6d0f6bcf JCPV	389	#define CONFIG_SYS_BR2_PRELIM 0xf0101001
	390	#define CONFIG_SYS_OR2_PRELIM 0xfff00ef4
	391	#define CONFIG_SYS_BR3_PRELIM 0xf0201001
	392	#define CONFIG_SYS_OR3_PRELIM 0xfff00ef4
	393	#define CONFIG_SYS_BR4_PRELIM 0xf0301001
	394	#define CONFIG_SYS_OR4_PRELIM 0xfff00ef4
	395	#define CONFIG_SYS_BR5_PRELIM 0xf0401001
	396	#define CONFIG_SYS_OR5_PRELIM 0xfff00ef4
ba91e26a	397	#else
6d0f6bcf JCPV	398	#define CONFIG_SYS_BR2_PRELIM 0xf0101081
	399	#define CONFIG_SYS_OR2_PRELIM 0xfff00104
	400	#define CONFIG_SYS_BR3_PRELIM 0xf0201081
	401	#define CONFIG_SYS_OR3_PRELIM 0xfff00104
	402	#define CONFIG_SYS_BR4_PRELIM 0xf0301081
	403	#define CONFIG_SYS_OR4_PRELIM 0xfff00104
	404	#define CONFIG_SYS_BR5_PRELIM 0xf0401081
	405	#define CONFIG_SYS_OR5_PRELIM 0xfff00104
ba91e26a	406	#endif
6d0f6bcf JCPV	407	#define CONFIG_SYS_BR7_PRELIM 0xf0500881
	408	#define CONFIG_SYS_OR7_PRELIM 0xffff8104
	409	#define CONFIG_SYS_MPTPR 0x2700
	410	#define CONFIG_SYS_PSDMR 0x822a2452 /* optimal */
	411	/#define CONFIG_SYS_PSDMR 0x822a48a3 / /* relaxed */
	412	#define CONFIG_SYS_PSRT 0x1a
ba91e26a WD	413
ba91e26a WD	414	/* "bad" address */
6d0f6bcf	415	#define CONFIG_SYS_RESET_ADDRESS 0x40000000
ba91e26a WD	416
ba91e26a WD	417	#endif /* __CONFIG_H */