projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| e2211743 WD |
1 | /* |
| 2 | * (C) Copyright 2001 | |
| 3 | * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | * (easy to change) | |
| 34 | */ | |
| 35 | ||
| 36 | #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ | |
| 37 | #define CONFIG_4xx 1 /* ...member of PPC405 family */ | |
| 38 | #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ | |
| 39 | #define CONFIG_W7OLMG 1 /* ...specifically an LMG */ | |
| 40 | ||
| c837dcb1 WD |
41 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 42 | #define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ | |
| e2211743 WD |
43 | |
| 44 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
| 45 | ||
| 46 | #define CONFIG_BAUDRATE 9600 | |
| 47 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
| 48 | ||
| 49 | #if 1 | |
| 50 | #define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ | |
| 51 | #else | |
| 52 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ | |
| 53 | #endif | |
| 54 | ||
| 55 | #undef CONFIG_BOOTARGS | |
| 56 | ||
| 57 | #define CONFIG_LOADADDR F0080000 | |
| 58 | ||
| 59 | #define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ | |
| 60 | #define CONFIG_OVERWRITE_ETHADDR_ONCE | |
| 61 | #define CONFIG_IPADDR 192.168.1.1 | |
| 62 | #define CONFIG_NETMASK 255.255.255.0 | |
| 63 | #define CONFIG_SERVERIP 192.168.1.2 | |
| 64 | ||
| 65 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 66 | #undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */ | |
| 67 | ||
| 68 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 69 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
| 70 | ||
| 71 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
| 72 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
| 73 | #define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */ | |
| 74 | #define CFG_DTT_MAX_TEMP 70 | |
| 75 | #define CFG_DTT_LOW_TEMP -30 | |
| 76 | #define CFG_DTT_HYSTERESIS 3 | |
| 77 | ||
| e2211743 | 78 | |
| a1aa0bb5 JL |
79 | /* |
| 80 | * BOOTP options | |
| 81 | */ | |
| 82 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 83 | #define CONFIG_BOOTP_BOOTPATH | |
| 84 | #define CONFIG_BOOTP_GATEWAY | |
| 85 | #define CONFIG_BOOTP_HOSTNAME | |
| 86 | ||
| 87 | ||
| a5562901 JL |
88 | /* |
| 89 | * Command line configuration. | |
| 90 | */ | |
| 91 | #include <config_cmd_default.h> | |
| 92 | ||
| 93 | #define CONFIG_CMD_PCI | |
| 94 | #define CONFIG_CMD_IRQ | |
| 95 | #define CONFIG_CMD_ASKENV | |
| 96 | #define CONFIG_CMD_DHCP | |
| 97 | #define CONFIG_CMD_BEDBUG | |
| 98 | #define CONFIG_CMD_DATE | |
| 99 | #define CONFIG_CMD_I2C | |
| 100 | #define CONFIG_CMD_EEPROM | |
| 101 | #define CONFIG_CMD_ELF | |
| 102 | #define CONFIG_CMD_BSP | |
| 103 | #define CONFIG_CMD_REGINFO | |
| 104 | #define CONFIG_CMD_DTT | |
| 105 | ||
| e2211743 WD |
106 | |
| 107 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 108 | #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ | |
| 109 | ||
| 110 | #define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ | |
| db2f721f | 111 | #define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ |
| e2211743 WD |
112 | /* |
| 113 | * Miscellaneous configurable options | |
| 114 | */ | |
| 115 | #define CFG_LONGHELP /* undef to save memory */ | |
| 116 | #define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ | |
| 117 | #undef CFG_HUSH_PARSER /* No hush parse for U-Boot */ | |
| 118 | #ifdef CFG_HUSH_PARSER | |
| 119 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 120 | #endif | |
| a5562901 | 121 | #if defined(CONFIG_CMD_KGDB) |
| e2211743 WD |
122 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 123 | #else | |
| 124 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 125 | #endif | |
| 126 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 127 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 128 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 129 | ||
| 130 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
| 131 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 132 | ||
| 133 | #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ | |
| 134 | #define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
| 135 | #define CFG_BASE_BAUD 384000 | |
| 136 | ||
| 137 | ||
| 138 | /* The following table includes the supported baudrates */ | |
| 139 | #define CFG_BAUDRATE_TABLE {9600} | |
| 140 | ||
| 141 | #define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ | |
| 142 | ||
| 143 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
| 144 | #define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */ | |
| 145 | ||
| 146 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 147 | ||
| 148 | /*----------------------------------------------------------------------- | |
| 149 | * PCI stuff | |
| 150 | *----------------------------------------------------------------------- | |
| 151 | */ | |
| 152 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
| 153 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
| 154 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
| 155 | ||
| 156 | #define CONFIG_PCI /* include pci support */ | |
| 157 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ | |
| 158 | #define CONFIG_PCI_PNP /* pci plug-and-play */ | |
| 159 | /* resource configuration */ | |
| 160 | #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ | |
| 161 | #define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ | |
| 162 | #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
| 163 | #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
| 53677ef1 WD |
164 | #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| 165 | #define CFG_PCI_PTM2LA 0x00000000 /* disabled */ | |
| 166 | #define CFG_PCI_PTM2MS 0x00000000 /* disabled */ | |
| 167 | #define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
| e2211743 WD |
168 | |
| 169 | /*----------------------------------------------------------------------- | |
| 170 | * Set up values for external bus controller | |
| 171 | * used by cpu_init.c | |
| 172 | *----------------------------------------------------------------------- | |
| 173 | */ | |
| 174 | /* use PerWE instead of PCI_INT ( these functions share a pin ) */ | |
| 175 | #define CONFIG_USE_PERWE 1 | |
| 176 | ||
| 177 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
| 178 | #define CFG_TEMP_STACK_OCM 1 | |
| 179 | ||
| 180 | /* bank 0 is boot flash */ | |
| 181 | /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ | |
| 182 | #define CFG_W7O_EBC_PB0AP 0x03050440 | |
| 183 | /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ | |
| 184 | #define CFG_W7O_EBC_PB0CR 0xFFE38000 | |
| 185 | ||
| 186 | /* bank 1 is main flash */ | |
| 187 | /* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ | |
| 188 | #define CFG_EBC_PB1AP 0x04850240 | |
| 189 | /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ | |
| 190 | #define CFG_EBC_PB1CR 0xF00FC000 | |
| 191 | ||
| 192 | /* bank 2 is RTC/NVRAM */ | |
| 193 | /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ | |
| 194 | #define CFG_EBC_PB2AP 0x03000440 | |
| 195 | /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ | |
| 196 | #define CFG_EBC_PB2CR 0xFC018000 | |
| 197 | ||
| 198 | /* bank 3 is FPGA 0 */ | |
| 199 | /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ | |
| 200 | #define CFG_EBC_PB3AP 0x02000400 | |
| 201 | /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ | |
| 202 | #define CFG_EBC_PB3CR 0xFD01A000 | |
| 203 | ||
| 204 | /* bank 4 is SAM 8 bit range */ | |
| 205 | /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ | |
| 206 | #define CFG_EBC_PB4AP 0x02840380 | |
| 207 | /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ | |
| 208 | #define CFG_EBC_PB4CR 0xFE878000 | |
| 209 | ||
| 210 | /* bank 5 is SAM 16 bit range */ | |
| 211 | /* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */ | |
| 212 | #define CFG_EBC_PB5AP 0x05040d80 | |
| 213 | /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ | |
| 214 | #define CFG_EBC_PB5CR 0xFD87A000 | |
| 215 | ||
| 216 | /* bank 6 is unused */ | |
| 217 | /* pb6ap = 0 */ | |
| 218 | #define CFG_EBC_PB6AP 0x00000000 | |
| 219 | /* pb6cr = 0 */ | |
| 220 | #define CFG_EBC_PB6CR 0x00000000 | |
| 221 | ||
| 222 | /* bank 7 is LED register */ | |
| 223 | /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ | |
| 224 | #define CFG_W7O_EBC_PB7AP 0x03050440 | |
| 225 | /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ | |
| 226 | #define CFG_W7O_EBC_PB7CR 0xFE01C000 | |
| 227 | ||
| 228 | /*----------------------------------------------------------------------- | |
| 229 | * Start addresses for the final memory configuration | |
| 230 | * (Set up by the startup code) | |
| 231 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 232 | */ | |
| 233 | #define CFG_SDRAM_BASE 0x00000000 | |
| 234 | #define CFG_FLASH_BASE 0xFFFC0000 | |
| 235 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
| 236 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */ | |
| 237 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
| 238 | ||
| 239 | /* | |
| 240 | * For booting Linux, the board info and command line data | |
| 241 | * have to be in the first 8 MB of memory, since this is | |
| 242 | * the maximum mapped by the Linux kernel during initialization. | |
| 243 | */ | |
| 244 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 245 | /*----------------------------------------------------------------------- | |
| 246 | * FLASH organization | |
| 247 | */ | |
| 248 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
| 249 | #define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ | |
| 250 | ||
| 251 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ | |
| 252 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ | |
| 253 | #define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */ | |
| 254 | ||
| 255 | #if 1 /* Use NVRAM for environment variables */ | |
| 256 | /*----------------------------------------------------------------------- | |
| 257 | * NVRAM organization | |
| 258 | */ | |
| 9314cee6 | 259 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ |
| e2211743 WD |
260 | #define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ |
| 261 | #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
| 262 | #define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ | |
| 263 | /*define CFG_ENV_ADDR \ | |
| 264 | (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */ | |
| 265 | #define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR | |
| 266 | ||
| 267 | #else /* Use Boot Flash for environment variables */ | |
| 268 | /*----------------------------------------------------------------------- | |
| 269 | * Flash EEPROM for environment | |
| 270 | */ | |
| 5a1aceb0 | 271 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| e2211743 WD |
272 | #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
| 273 | #define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */ | |
| 274 | ||
| 275 | #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ | |
| 276 | #endif | |
| 277 | ||
| 278 | /*----------------------------------------------------------------------- | |
| 279 | * I2C EEPROM (ATMEL 24C04N) | |
| 280 | */ | |
| 281 | #define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */ | |
| 282 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 283 | #define CFG_I2C_SLAVE 0x7F | |
| 284 | ||
| 285 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */ | |
| 286 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
| 287 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
| 288 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
| 289 | #define CFG_I2C_MULTI_EEPROMS | |
| 290 | /*----------------------------------------------------------------------- | |
| 291 | * Definitions for Serial Presence Detect EEPROM address | |
| 292 | * (to get SDRAM settings) | |
| 293 | */ | |
| 294 | #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ | |
| 295 | ||
| e2211743 WD |
296 | /* |
| 297 | * Init Memory Controller: | |
| 298 | */ | |
| 299 | #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ | |
| 300 | #define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ | |
| 301 | ||
| 302 | /* On Chip Memory location */ | |
| 303 | #define CFG_OCM_DATA_ADDR 0xF8000000 | |
| 304 | #define CFG_OCM_DATA_SIZE 0x1000 | |
| 305 | ||
| 306 | /*----------------------------------------------------------------------- | |
| 307 | * Definitions for initial stack pointer and data area (in RAM) | |
| 308 | */ | |
| 309 | #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ | |
| 310 | #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ | |
| 311 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
| 312 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 313 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 314 | ||
| 315 | ||
| 316 | /* | |
| 317 | * Internal Definitions | |
| 318 | * | |
| 319 | * Boot Flags | |
| 320 | */ | |
| 321 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 322 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 323 | ||
| a5562901 | 324 | #if defined(CONFIG_CMD_KGDB) |
| e2211743 WD |
325 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 326 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 327 | #endif | |
| 328 | ||
| 329 | /* | |
| 330 | * FPGA(s) configuration | |
| 331 | */ | |
| 332 | #define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ | |
| 333 | #define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */ | |
| 334 | #define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ | |
| 335 | #define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ | |
| 336 | #define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ | |
| 337 | ||
| 338 | #endif /* __CONFIG_H */ |