projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5da6f806 PT |
1 | /* |
| 2 | * Copyright 2009 Extreme Engineering Solutions, Inc. | |
| 3 | * Copyright 2007-2008 Freescale Semiconductor, Inc. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * xpedite5170 board configuration file | |
| 26 | */ | |
| 27 | #ifndef __CONFIG_H | |
| 28 | #define __CONFIG_H | |
| 29 | ||
| 30 | /* | |
| 31 | * High Level Configuration Options | |
| 32 | */ | |
| 33 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
| 34 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ | |
| 35 | #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ | |
| 36 | #define CONFIG_SYS_BOARD_NAME "XPedite5170" | |
| 37 | #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ | |
| 38 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ | |
| 39 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ | |
| 40 | #define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ | |
| 41 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ | |
| 42 | #define CONFIG_ALTIVEC 1 | |
| 43 | ||
| 44 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ | |
| 45 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
| 46 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ | |
| 47 | #define CONFIG_PCIE1 1 /* PCIE controler 1 */ | |
| 48 | #define CONFIG_PCIE2 1 /* PCIE controler 2 */ | |
| 49 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 50 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
| 51 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
| 52 | ||
| 53 | /* | |
| 54 | * DDR config | |
| 55 | */ | |
| 56 | #define CONFIG_FSL_DDR2 | |
| 57 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 58 | #define CONFIG_DDR_SPD | |
| 59 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 60 | #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ | |
| 61 | #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ | |
| 62 | #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ | |
| 63 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| 64 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 65 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 66 | #define CONFIG_DDR_ECC | |
| 67 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 68 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
| 69 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 70 | #define CONFIG_VERY_BIG_RAM | |
| 71 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ | |
| 72 | ||
| 73 | /* | |
| 74 | * virtual address to be used for temporary mappings. There | |
| 75 | * should be 128k free at this VA. | |
| 76 | */ | |
| 77 | #define CONFIG_SYS_SCRATCH_VA 0xe0000000 | |
| 78 | ||
| 79 | #ifndef __ASSEMBLY__ | |
| 80 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 81 | #endif | |
| 82 | ||
| 83 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ | |
| 84 | ||
| 85 | /* | |
| 86 | * L2CR setup | |
| 87 | */ | |
| 88 | #define CONFIG_SYS_L2 | |
| 89 | #define L2_INIT 0 | |
| 90 | #define L2_ENABLE (L2CR_L2E) | |
| 91 | ||
| 92 | /* | |
| 93 | * Base addresses -- Note these are effective addresses where the | |
| 94 | * actual resources get mapped (not physical addresses) | |
| 95 | */ | |
| 96 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
| 97 | #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ | |
| 98 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR | |
| 99 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 100 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 | |
| 101 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR | |
| 102 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) | |
| 103 | #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) | |
| 104 | ||
| 105 | /* | |
| 106 | * Diagnostics | |
| 107 | */ | |
| 108 | #define CONFIG_SYS_ALT_MEMTEST | |
| 109 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
| 110 | #define CONFIG_SYS_MEMTEST_END 0x20000000 | |
| 111 | ||
| 112 | /* | |
| 113 | * Memory map | |
| 114 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 115 | * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable | |
| 116 | * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable | |
| 117 | * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable | |
| 118 | * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable | |
| 119 | * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable | |
| 120 | * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable | |
| 121 | * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable | |
| 122 | * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable | |
| 123 | * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable | |
| 124 | */ | |
| 125 | ||
| 126 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3) | |
| 127 | ||
| 128 | /* | |
| 129 | * NAND flash configuration | |
| 130 | */ | |
| 131 | #define CONFIG_SYS_NAND_BASE 0xef800000 | |
| 132 | #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ | |
| 133 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} | |
| 134 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
| 135 | #define CONFIG_NAND_ACTL | |
| 136 | #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ | |
| 137 | #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ | |
| 138 | #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ | |
| 139 | #define CONFIG_SYS_NAND_ACTL_DELAY 25 | |
| 140 | #define CONFIG_SYS_NAND_QUIET_TEST | |
| 141 | #define CONFIG_JFFS2_NAND | |
| 142 | ||
| 143 | /* | |
| 144 | * NOR flash configuration | |
| 145 | */ | |
| 146 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 | |
| 147 | #define CONFIG_SYS_FLASH_BASE2 0xf0000000 | |
| 148 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} | |
| 149 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 150 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 151 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 152 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 153 | #define CONFIG_FLASH_CFI_DRIVER | |
| 154 | #define CONFIG_SYS_FLASH_CFI | |
| 155 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 156 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ | |
| 157 | {0xf7f00000, 0xc0000} } | |
| 158 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 159 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ | |
| 160 | ||
| 161 | /* | |
| 162 | * Chip select configuration | |
| 163 | */ | |
| 164 | /* NOR Flash 0 on CS0 */ | |
| 165 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ | |
| 166 | BR_PS_16 |\ | |
| 167 | BR_V) | |
| 168 | #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ | |
| 169 | OR_GPCM_CSNT |\ | |
| 170 | OR_GPCM_XACS |\ | |
| 171 | OR_GPCM_ACS_DIV2 |\ | |
| 172 | OR_GPCM_SCY_8 |\ | |
| 173 | OR_GPCM_TRLX |\ | |
| 174 | OR_GPCM_EHTR |\ | |
| 175 | OR_GPCM_EAD) | |
| 176 | ||
| 177 | /* NOR Flash 1 on CS1 */ | |
| 178 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ | |
| 179 | BR_PS_16 |\ | |
| 180 | BR_V) | |
| 181 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
| 182 | ||
| 183 | /* NAND flash on CS2 */ | |
| 184 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ | |
| 185 | BR_PS_8 |\ | |
| 186 | BR_V) | |
| 187 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ | |
| 188 | OR_GPCM_BCTLD |\ | |
| 189 | OR_GPCM_CSNT |\ | |
| 190 | OR_GPCM_ACS_DIV4 |\ | |
| 191 | OR_GPCM_SCY_4 |\ | |
| 192 | OR_GPCM_TRLX |\ | |
| 193 | OR_GPCM_EHTR) | |
| 194 | ||
| 195 | /* Optional NAND flash on CS3 */ | |
| 196 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ | |
| 197 | BR_PS_8 |\ | |
| 198 | BR_V) | |
| 199 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
| 200 | ||
| 201 | /* | |
| 202 | * Use L1 as initial stack | |
| 203 | */ | |
| 204 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
| 205 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 | |
| 206 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 | |
| 207 | ||
| 208 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
| 209 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 210 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 211 | ||
| 212 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
| 213 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
| 214 | ||
| 215 | /* | |
| 216 | * Serial Port | |
| 217 | */ | |
| 218 | #define CONFIG_CONS_INDEX 1 | |
| 219 | #define CONFIG_SYS_NS16550 | |
| 220 | #define CONFIG_SYS_NS16550_SERIAL | |
| 221 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 222 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 223 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 224 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 225 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 226 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
| 227 | #define CONFIG_BAUDRATE 115200 | |
| 228 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 229 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 230 | ||
| 231 | /* | |
| 232 | * Use the HUSH parser | |
| 233 | */ | |
| 234 | #define CONFIG_SYS_HUSH_PARSER | |
| 235 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 236 | ||
| 237 | /* | |
| 238 | * Pass open firmware flat tree | |
| 239 | */ | |
| 240 | #define CONFIG_OF_LIBFDT 1 | |
| 241 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 242 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 243 | ||
| 244 | #define CONFIG_SYS_64BIT_VSPRINTF 1 | |
| 245 | #define CONFIG_SYS_64BIT_STRTOUL 1 | |
| 246 | ||
| 247 | /* | |
| 248 | * I2C | |
| 249 | */ | |
| 250 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 251 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 252 | #define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */ | |
| 253 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 254 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 255 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 256 | #define CONFIG_I2C_MULTI_BUS | |
| 257 | #define CONFIG_I2C_CMD_TREE | |
| 258 | ||
| 259 | /* PEX8518 slave I2C interface */ | |
| 260 | #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 | |
| 261 | ||
| 262 | /* I2C DS1631 temperature sensor */ | |
| 263 | #define CONFIG_SYS_I2C_DS1621_ADDR 0x48 | |
| 264 | #define CONFIG_DTT_DS1621 | |
| 265 | #define CONFIG_DTT_SENSORS { 0 } | |
| 266 | ||
| 267 | /* I2C EEPROM - AT24C128B */ | |
| 268 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 | |
| 269 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 270 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
| 271 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
| 272 | ||
| 273 | /* I2C RTC */ | |
| 274 | #define CONFIG_RTC_M41T11 1 | |
| 275 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 276 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
| 277 | ||
| 278 | /* GPIO/EEPROM/SRAM */ | |
| 279 | #define CONFIG_DS4510 | |
| 280 | #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 | |
| 281 | ||
| 282 | /* GPIO */ | |
| 283 | #define CONFIG_PCA953X | |
| 284 | #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 | |
| 285 | #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c | |
| 286 | #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e | |
| 287 | #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f | |
| 288 | #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 | |
| 289 | ||
| 290 | /* | |
| 291 | * PU = pulled high, PD = pulled low | |
| 292 | * I = input, O = output, IO = input/output | |
| 293 | */ | |
| 294 | /* PCA9557 @ 0x18*/ | |
| 295 | #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ | |
| 296 | #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ | |
| 297 | #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ | |
| 298 | #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ | |
| 299 | #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ | |
| 300 | #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ | |
| 301 | ||
| 302 | /* PCA9557 @ 0x1c*/ | |
| 303 | #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ | |
| 304 | #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ | |
| 305 | #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ | |
| 306 | #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ | |
| 307 | #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ | |
| 308 | #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ | |
| 309 | #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ | |
| 310 | #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ | |
| 311 | ||
| 312 | /* PCA9557 @ 0x1e*/ | |
| 313 | #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ | |
| 314 | #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ | |
| 315 | #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ | |
| 316 | #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ | |
| 317 | #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ | |
| 318 | #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ | |
| 319 | #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ | |
| 320 | ||
| 321 | /* PCA9557 @ 0x1f */ | |
| 322 | #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ | |
| 323 | #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ | |
| 324 | #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ | |
| 325 | #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ | |
| 326 | ||
| 327 | /* | |
| 328 | * General PCI | |
| 329 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 330 | */ | |
| 331 | /* PCIE1 - PEX8518 */ | |
| 332 | #define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 | |
| 333 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE | |
| 334 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ | |
| 335 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
| 336 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 | |
| 337 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
| 338 | ||
| 339 | /* PCIE2 - VPX P1 */ | |
| 340 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 | |
| 341 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE | |
| 342 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
| 343 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
| 344 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 | |
| 345 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ | |
| 346 | ||
| 347 | /* | |
| 348 | * Networking options | |
| 349 | */ | |
| 350 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 351 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 352 | #define CONFIG_NET_MULTI 1 | |
| 353 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 354 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 355 | ||
| 356 | #define CONFIG_TSEC1 1 | |
| 357 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 358 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 359 | #define TSEC1_PHY_ADDR 1 | |
| 360 | #define TSEC1_PHYIDX 0 | |
| 361 | #define CONFIG_HAS_ETH0 | |
| 362 | ||
| 363 | #define CONFIG_TSEC2 1 | |
| 364 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 365 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 366 | #define TSEC2_PHY_ADDR 2 | |
| 367 | #define TSEC2_PHYIDX 0 | |
| 368 | #define CONFIG_HAS_ETH1 | |
| 369 | ||
| 370 | /* | |
| 371 | * BAT mappings | |
| 372 | */ | |
| 373 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) | |
| 374 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ | |
| 375 | BATL_PP_RW |\ | |
| 376 | BATL_CACHEINHIBIT |\ | |
| 377 | BATL_GUARDEDSTORAGE) | |
| 378 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ | |
| 379 | BATU_BL_1M |\ | |
| 380 | BATU_VS |\ | |
| 381 | BATU_VP) | |
| 382 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ | |
| 383 | BATL_PP_RW |\ | |
| 384 | BATL_CACHEINHIBIT) | |
| 385 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
| 386 | #endif | |
| 387 | ||
| 388 | /* | |
| 389 | * BAT0 2G Cacheable, non-guarded | |
| 390 | * 0x0000_0000 2G DDR | |
| 391 | */ | |
| 392 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 393 | #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) | |
| 394 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 395 | #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U | |
| 396 | ||
| 397 | /* | |
| 398 | * BAT1 1G Cache-inhibited, guarded | |
| 399 | * 0x8000_0000 1G PCI-Express 1 Memory | |
| 400 | */ | |
| 401 | #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ | |
| 402 | BATL_PP_RW |\ | |
| 403 | BATL_CACHEINHIBIT |\ | |
| 404 | BATL_GUARDEDSTORAGE) | |
| 405 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ | |
| 406 | BATU_BL_1G |\ | |
| 407 | BATU_VS |\ | |
| 408 | BATU_VP) | |
| 409 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ | |
| 410 | BATL_PP_RW |\ | |
| 411 | BATL_CACHEINHIBIT) | |
| 412 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U | |
| 413 | ||
| 414 | /* | |
| 415 | * BAT2 512M Cache-inhibited, guarded | |
| 416 | * 0xc000_0000 512M PCI-Express 2 Memory | |
| 417 | */ | |
| 418 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ | |
| 419 | BATL_PP_RW |\ | |
| 420 | BATL_CACHEINHIBIT |\ | |
| 421 | BATL_GUARDEDSTORAGE) | |
| 422 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ | |
| 423 | BATU_BL_512M |\ | |
| 424 | BATU_VS |\ | |
| 425 | BATU_VP) | |
| 426 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ | |
| 427 | BATL_PP_RW |\ | |
| 428 | BATL_CACHEINHIBIT) | |
| 429 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
| 430 | ||
| 431 | /* | |
| 432 | * BAT3 1M Cache-inhibited, guarded | |
| 433 | * 0xe000_0000 1M CCSR | |
| 434 | */ | |
| 435 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ | |
| 436 | BATL_PP_RW |\ | |
| 437 | BATL_CACHEINHIBIT |\ | |
| 438 | BATL_GUARDEDSTORAGE) | |
| 439 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ | |
| 440 | BATU_BL_1M |\ | |
| 441 | BATU_VS |\ | |
| 442 | BATU_VP) | |
| 443 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ | |
| 444 | BATL_PP_RW |\ | |
| 445 | BATL_CACHEINHIBIT) | |
| 446 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U | |
| 447 | ||
| 448 | /* | |
| 449 | * BAT4 32M Cache-inhibited, guarded | |
| 450 | * 0xe200_0000 16M PCI-Express 1 I/O | |
| 451 | * 0xe300_0000 16M PCI-Express 2 I/0 | |
| 452 | */ | |
| 453 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ | |
| 454 | BATL_PP_RW |\ | |
| 455 | BATL_CACHEINHIBIT |\ | |
| 456 | BATL_GUARDEDSTORAGE) | |
| 457 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ | |
| 458 | BATU_BL_32M |\ | |
| 459 | BATU_VS |\ | |
| 460 | BATU_VP) | |
| 461 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ | |
| 462 | BATL_PP_RW |\ | |
| 463 | BATL_CACHEINHIBIT) | |
| 464 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U | |
| 465 | ||
| 466 | /* | |
| 467 | * BAT5 128K Cacheable, non-guarded | |
| 468 | * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) | |
| 469 | */ | |
| 470 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ | |
| 471 | BATL_PP_RW |\ | |
| 472 | BATL_MEMCOHERENCE) | |
| 473 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ | |
| 474 | BATU_BL_128K |\ | |
| 475 | BATU_VS |\ | |
| 476 | BATU_VP) | |
| 477 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
| 478 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
| 479 | ||
| 480 | /* | |
| 481 | * BAT6 256M Cache-inhibited, guarded | |
| 482 | * 0xf000_0000 256M FLASH | |
| 483 | */ | |
| 484 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ | |
| 485 | BATL_PP_RW |\ | |
| 486 | BATL_CACHEINHIBIT |\ | |
| 487 | BATL_GUARDEDSTORAGE) | |
| 488 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ | |
| 489 | BATU_BL_256M |\ | |
| 490 | BATU_VS |\ | |
| 491 | BATU_VP) | |
| 492 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ | |
| 493 | BATL_PP_RW |\ | |
| 494 | BATL_MEMCOHERENCE) | |
| 495 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U | |
| 496 | ||
| 497 | /* Map the last 1M of flash where we're running from reset */ | |
| 498 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ | |
| 499 | BATL_PP_RW |\ | |
| 500 | BATL_CACHEINHIBIT |\ | |
| 501 | BATL_GUARDEDSTORAGE) | |
| 502 | #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\ | |
| 503 | BATU_BL_1M |\ | |
| 504 | BATU_VS |\ | |
| 505 | BATU_VP) | |
| 506 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ | |
| 507 | BATL_PP_RW |\ | |
| 508 | BATL_MEMCOHERENCE) | |
| 509 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
| 510 | ||
| 511 | /* | |
| 512 | * BAT7 64M Cache-inhibited, guarded | |
| 513 | * 0xe800_0000 64K NAND FLASH | |
| 514 | * 0xe804_0000 128K DUART Registers | |
| 515 | */ | |
| 516 | #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ | |
| 517 | BATL_PP_RW |\ | |
| 518 | BATL_CACHEINHIBIT |\ | |
| 519 | BATL_GUARDEDSTORAGE) | |
| 520 | #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ | |
| 521 | BATU_BL_512K |\ | |
| 522 | BATU_VS |\ | |
| 523 | BATU_VP) | |
| 524 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ | |
| 525 | BATL_PP_RW |\ | |
| 526 | BATL_CACHEINHIBIT) | |
| 527 | #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U | |
| 528 | ||
| 529 | /* | |
| 530 | * Command configuration. | |
| 531 | */ | |
| 532 | #include <config_cmd_default.h> | |
| 533 | ||
| 534 | #define CONFIG_CMD_ASKENV | |
| 535 | #define CONFIG_CMD_DATE | |
| 536 | #define CONFIG_CMD_DHCP | |
| 537 | #define CONFIG_CMD_DS4510 | |
| 538 | #define CONFIG_CMD_DS4510_INFO | |
| 539 | #define CONFIG_CMD_DTT | |
| 540 | #define CONFIG_CMD_EEPROM | |
| 541 | #define CONFIG_CMD_ELF | |
| 542 | #define CONFIG_CMD_SAVEENV | |
| 543 | #define CONFIG_CMD_FLASH | |
| 544 | #define CONFIG_CMD_I2C | |
| 545 | #define CONFIG_CMD_IRQ | |
| 546 | #define CONFIG_CMD_JFFS2 | |
| 547 | #define CONFIG_CMD_MII | |
| 548 | #define CONFIG_CMD_NAND | |
| 549 | #define CONFIG_CMD_NET | |
| 550 | #define CONFIG_CMD_PCA953X | |
| 551 | #define CONFIG_CMD_PCA953X_INFO | |
| 552 | #define CONFIG_CMD_PCI | |
| 553 | #define CONFIG_CMD_PING | |
| 554 | #define CONFIG_CMD_REGINFO | |
| 555 | #define CONFIG_CMD_SNTP | |
| 556 | ||
| 557 | /* | |
| 558 | * Miscellaneous configurable options | |
| 559 | */ | |
| 560 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 561 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 562 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 563 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 564 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
| 565 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 566 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 567 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 568 | #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ | |
| 569 | #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ | |
| 570 | #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ | |
| 571 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
| 572 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
| 573 | #define CONFIG_FIT 1 | |
| 574 | #define CONFIG_FIT_VERBOSE 1 | |
| 575 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ | |
| 576 | ||
| 577 | /* | |
| 578 | * For booting Linux, the board info and command line data | |
| 579 | * have to be in the first 16 MB of memory, since this is | |
| 580 | * the maximum mapped by the Linux kernel during initialization. | |
| 581 | */ | |
| 582 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
| 583 | ||
| 584 | /* | |
| 585 | * Boot Flags | |
| 586 | */ | |
| 587 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 588 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 589 | ||
| 590 | /* | |
| 591 | * Environment Configuration | |
| 592 | */ | |
| 593 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
| 594 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ | |
| 595 | #define CONFIG_ENV_SIZE 0x8000 | |
| 596 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
| 597 | ||
| 598 | /* | |
| 599 | * Flash memory map: | |
| 600 | * fffc0000 - ffffffff Pri FDT (256KB) | |
| 601 | * fff80000 - fffbffff Pri U-Boot Environment (256 KB) | |
| 602 | * fff00000 - fff7ffff Pri U-Boot (512 KB) | |
| 603 | * fef00000 - ffefffff Pri OS image (16MB) | |
| 604 | * f8000000 - feefffff Pri OS Use/Filesystem (111MB) | |
| 605 | * | |
| 606 | * f7fc0000 - f7ffffff Sec FDT (256KB) | |
| 607 | * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) | |
| 608 | * f7f00000 - f7f7ffff Sec U-Boot (512 KB) | |
| 609 | * f6f00000 - f7efffff Sec OS image (16MB) | |
| 610 | * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) | |
| 611 | */ | |
| 612 | #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000) | |
| 613 | #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000) | |
| 614 | #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000) | |
| 615 | #define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000) | |
| 616 | #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) | |
| 617 | #define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) | |
| 618 | ||
| 619 | #define CONFIG_PROG_UBOOT1 \ | |
| 620 | "$download_cmd $loadaddr $ubootfile; " \ | |
| 621 | "if test $? -eq 0; then " \ | |
| 622 | "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
| 623 | "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
| 624 | "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ | |
| 625 | "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
| 626 | "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ | |
| 627 | "if test $? -ne 0; then " \ | |
| 628 | "echo PROGRAM FAILED; " \ | |
| 629 | "else; " \ | |
| 630 | "echo PROGRAM SUCCEEDED; " \ | |
| 631 | "fi; " \ | |
| 632 | "else; " \ | |
| 633 | "echo DOWNLOAD FAILED; " \ | |
| 634 | "fi;" | |
| 635 | ||
| 636 | #define CONFIG_PROG_UBOOT2 \ | |
| 637 | "$download_cmd $loadaddr $ubootfile; " \ | |
| 638 | "if test $? -eq 0; then " \ | |
| 639 | "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
| 640 | "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
| 641 | "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ | |
| 642 | "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
| 643 | "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ | |
| 644 | "if test $? -ne 0; then " \ | |
| 645 | "echo PROGRAM FAILED; " \ | |
| 646 | "else; " \ | |
| 647 | "echo PROGRAM SUCCEEDED; " \ | |
| 648 | "fi; " \ | |
| 649 | "else; " \ | |
| 650 | "echo DOWNLOAD FAILED; " \ | |
| 651 | "fi;" | |
| 652 | ||
| 653 | #define CONFIG_BOOT_OS_NET \ | |
| 654 | "$download_cmd $osaddr $osfile; " \ | |
| 655 | "if test $? -eq 0; then " \ | |
| 656 | "if test -n $fdtaddr; then " \ | |
| 657 | "$download_cmd $fdtaddr $fdtfile; " \ | |
| 658 | "if test $? -eq 0; then " \ | |
| 659 | "bootm $osaddr - $fdtaddr; " \ | |
| 660 | "else; " \ | |
| 661 | "echo FDT DOWNLOAD FAILED; " \ | |
| 662 | "fi; " \ | |
| 663 | "else; " \ | |
| 664 | "bootm $osaddr; " \ | |
| 665 | "fi; " \ | |
| 666 | "else; " \ | |
| 667 | "echo OS DOWNLOAD FAILED; " \ | |
| 668 | "fi;" | |
| 669 | ||
| 670 | #define CONFIG_PROG_OS1 \ | |
| 671 | "$download_cmd $osaddr $osfile; " \ | |
| 672 | "if test $? -eq 0; then " \ | |
| 673 | "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ | |
| 674 | "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
| 675 | "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
| 676 | "if test $? -ne 0; then " \ | |
| 677 | "echo OS PROGRAM FAILED; " \ | |
| 678 | "else; " \ | |
| 679 | "echo OS PROGRAM SUCCEEDED; " \ | |
| 680 | "fi; " \ | |
| 681 | "else; " \ | |
| 682 | "echo OS DOWNLOAD FAILED; " \ | |
| 683 | "fi;" | |
| 684 | ||
| 685 | #define CONFIG_PROG_OS2 \ | |
| 686 | "$download_cmd $osaddr $osfile; " \ | |
| 687 | "if test $? -eq 0; then " \ | |
| 688 | "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ | |
| 689 | "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
| 690 | "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
| 691 | "if test $? -ne 0; then " \ | |
| 692 | "echo OS PROGRAM FAILED; " \ | |
| 693 | "else; " \ | |
| 694 | "echo OS PROGRAM SUCCEEDED; " \ | |
| 695 | "fi; " \ | |
| 696 | "else; " \ | |
| 697 | "echo OS DOWNLOAD FAILED; " \ | |
| 698 | "fi;" | |
| 699 | ||
| 700 | #define CONFIG_PROG_FDT1 \ | |
| 701 | "$download_cmd $fdtaddr $fdtfile; " \ | |
| 702 | "if test $? -eq 0; then " \ | |
| 703 | "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ | |
| 704 | "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
| 705 | "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
| 706 | "if test $? -ne 0; then " \ | |
| 707 | "echo FDT PROGRAM FAILED; " \ | |
| 708 | "else; " \ | |
| 709 | "echo FDT PROGRAM SUCCEEDED; " \ | |
| 710 | "fi; " \ | |
| 711 | "else; " \ | |
| 712 | "echo FDT DOWNLOAD FAILED; " \ | |
| 713 | "fi;" | |
| 714 | ||
| 715 | #define CONFIG_PROG_FDT2 \ | |
| 716 | "$download_cmd $fdtaddr $fdtfile; " \ | |
| 717 | "if test $? -eq 0; then " \ | |
| 718 | "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ | |
| 719 | "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
| 720 | "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
| 721 | "if test $? -ne 0; then " \ | |
| 722 | "echo FDT PROGRAM FAILED; " \ | |
| 723 | "else; " \ | |
| 724 | "echo FDT PROGRAM SUCCEEDED; " \ | |
| 725 | "fi; " \ | |
| 726 | "else; " \ | |
| 727 | "echo FDT DOWNLOAD FAILED; " \ | |
| 728 | "fi;" | |
| 729 | ||
| 730 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 731 | "autoload=yes\0" \ | |
| 732 | "download_cmd=tftp\0" \ | |
| 733 | "console_args=console=ttyS0,115200\0" \ | |
| 734 | "root_args=root=/dev/nfs rw\0" \ | |
| 735 | "misc_args=ip=on\0" \ | |
| 736 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ | |
| 737 | "bootfile=/home/user/file\0" \ | |
| 738 | "osfile=/home/user/uImage-XPedite5170\0" \ | |
| 739 | "fdtfile=/home/user/xpedite5170.dtb\0" \ | |
| 740 | "ubootfile=/home/user/u-boot.bin\0" \ | |
| 741 | "fdtaddr=c00000\0" \ | |
| 742 | "osaddr=0x1000000\0" \ | |
| 743 | "loadaddr=0x1000000\0" \ | |
| 744 | "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ | |
| 745 | "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ | |
| 746 | "prog_os1="CONFIG_PROG_OS1"\0" \ | |
| 747 | "prog_os2="CONFIG_PROG_OS2"\0" \ | |
| 748 | "prog_fdt1="CONFIG_PROG_FDT1"\0" \ | |
| 749 | "prog_fdt2="CONFIG_PROG_FDT2"\0" \ | |
| 750 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ | |
| 751 | "bootcmd_flash1=run set_bootargs; " \ | |
| 752 | "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ | |
| 753 | "bootcmd_flash2=run set_bootargs; " \ | |
| 754 | "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ | |
| 755 | "bootcmd=run bootcmd_flash1\0" | |
| 756 | #endif /* __CONFIG_H */ |