[people/ms/u-boot.git] / include / configs / acadia.h

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * acadia.h - configuration for AMCC Acadia (405EZ)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_ACADIA		1		/* Board is Acadia	*/
#define CONFIG_4xx		1		/* ... PPC4xx family	*/
#define CONFIG_405EZ		1		/* Specifc 405EZ support*/

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		acadia
#include "amcc-common.h"

/* Detect Acadia PLL input clock automatically via CPLD bit		*/
#define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
				66666666 : 33333000)

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
#define CONFIG_MISC_INIT_F	1		/* Call misc_init_f	*/

#define CONFIG_NO_SERIAL_EEPROM
/*#undef CONFIG_NO_SERIAL_EEPROM*/

#ifdef CONFIG_NO_SERIAL_EEPROM
/*----------------------------------------------------------------------------
 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
 * assuming a 66MHz input clock to the 405EZ.
 *---------------------------------------------------------------------------*/
/* #define PLLMR0_100_100_12 */
#define PLLMR0_200_133_66
/* #define PLLMR0_266_160_80 */
/* #define PLLMR0_333_166_83 */
#endif

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE		0xfe000000
#define CONFIG_SYS_CPLD_BASE		0x80000000
#define CONFIG_SYS_NAND_ADDR		0xd0000000
#define CONFIG_SYS_USB_HOST		0xef603000	/* USB OHCI 1.1 controller	*/

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM	1		/* OCM as init ram	*/

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xf8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x4000			/* 16K of onchip SRAM		*/
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of SRAM		*/
#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE	/* End of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_SIZE	128			/* size for initial data	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef	CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
#define CONFIG_SYS_BASE_BAUD		691200

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
#endif

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/

#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#else
#define	CONFIG_SYS_NO_FLASH		1	/* No NOR on Acadia when NAND-booting	*/
#endif

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif

/*
 * IPL (Initial Program Loader, integrated inside CPU)
 * Will load first 4k from NAND (SPL) into cache and execute it from there.
 *
 * SPL (Secondary Program Loader)
 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 * controller and the NAND controller so that the special U-Boot image can be
 * loaded from NAND to SDRAM.
 *
 * NUB (NAND U-Boot)
 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 *
 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 * set up. While still running from cache, I experienced problems accessing
 * the NAND controller.	sr - 2006-08-25
 */
#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)

/*
 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 */
#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/

/*
 * Now the NAND chip has to be defined (no autodetection used!)
 */
#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
#undef CONFIG_SYS_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/

#define CONFIG_SYS_NAND_ECCSIZE	256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
#define CONFIG_SYS_NAND_OOBSIZE	16
#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}

#ifdef CONFIG_ENV_IS_IN_NAND
/*
 * For NAND booting the environment is embedded in the U-Boot image. Please take
 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 */
#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#endif

/*-----------------------------------------------------------------------
 * RAM (CRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MBYTES_RAM		64		/* 64MB			*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/

#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
#define CONFIG_SYS_DTT_MAX_TEMP	70
#define CONFIG_SYS_DTT_LOW_TEMP	-30
#define CONFIG_SYS_DTT_HYSTERESIS	3

/*-----------------------------------------------------------------------
 * Ethernet
 *----------------------------------------------------------------------*/
#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_HAS_ETH0		1

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_PPC						\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
	"kernel_addr=fff10000\0"					\
	"ramdisk_addr=fff20000\0"					\
	"kozio=bootm ffc60000\0"					\
	""

#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#define CONFIG_SUPPORT_VFAT

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_DTT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_USB

/*
 * No NOR on Acadia when NAND-booting
 */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#endif

/*-----------------------------------------------------------------------
 * NAND FLASH
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS		1
#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS		3
/* Memory Bank 0 (Flash) initialization						*/
#define CONFIG_SYS_EBC_PB0AP		0x03337200
#define CONFIG_SYS_EBC_PB0CR		0xfe0bc000

/* Memory Bank 3 (NAND-FLASH) initialization					*/
#define CONFIG_SYS_EBC_PB3AP		0x018003c0
#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)

/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
/* Memory Bank 1 (CRAM) initialization						*/
#define CONFIG_SYS_EBC_PB1AP		0x030400c0
#define CONFIG_SYS_EBC_PB1CR		0x000bc000

/* Memory Bank 2 (CRAM) initialization						*/
#define CONFIG_SYS_EBC_PB2AP		0x030400c0
#define CONFIG_SYS_EBC_PB2CR		0x020bc000
#else
#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
/* Memory Bank 0 (NAND-FLASH) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x018003c0
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)

/*
 * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
 * NAND-SPL already initialized the CRAM and EBC to sync mode.
 */
/* Memory Bank 1 (CRAM) initialization						*/
#define CONFIG_SYS_EBC_PB1AP		0x9C0201C0
#define CONFIG_SYS_EBC_PB1CR		0x000bc000

/* Memory Bank 2 (CRAM) initialization						*/
#define CONFIG_SYS_EBC_PB2AP		0x9C0201C0
#define CONFIG_SYS_EBC_PB2CR		0x020bc000
#endif

/* Memory Bank 4 (CPLD) initialization						*/
#define CONFIG_SYS_EBC_PB4AP		0x04006000
#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_CPLD_BASE | 0x18000)

#define CONFIG_SYS_EBC_CFG		0xf8400000

/*-----------------------------------------------------------------------
 * GPIO Setup
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_GPIO_CRAM_CLK	8
#define CONFIG_SYS_GPIO_CRAM_WAIT	9		/* GPIO-In		*/
#define CONFIG_SYS_GPIO_CRAM_ADV	10
#define CONFIG_SYS_GPIO_CRAM_CRE	(32 + 21)	/* GPIO-Out		*/

/*-----------------------------------------------------------------------
 * Definitions for GPIO_0 setup (PPC405EZ specific)
 *
 * GPIO0[0-2]	- External Bus Controller CS_4 - CS_6 Outputs
 * GPIO0[3]	- NAND FLASH Controller CE3 (NFCE3) Output
 * GPIO0[4]	- External Bus Controller Hold Input
 * GPIO0[5]	- External Bus Controller Priority Input
 * GPIO0[6]	- External Bus Controller HLDA Output
 * GPIO0[7]	- External Bus Controller Bus Request Output
 * GPIO0[8]	- CRAM Clk Output
 * GPIO0[9]	- External Bus Controller Ready Input
 * GPIO0[10]	- CRAM Adv Output
 * GPIO0[11-24]	- NAND Flash Control Data -> Bypasses GPIO when enabled
 * GPIO0[25]	- External DMA Request Input
 * GPIO0[26]	- External DMA EOT I/O
 * GPIO0[25]	- External DMA Ack_n Output
 * GPIO0[17-23]	- External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[28-30]	- Trace Outputs / PWM Inputs
 * GPIO0[31]	- PWM_8 I/O
 */
#define CONFIG_SYS_GPIO0_TCR		0xC0A00000
#define CONFIG_SYS_GPIO0_OSRL		0x50004400
#define CONFIG_SYS_GPIO0_OSRH		0x02000055
#define CONFIG_SYS_GPIO0_ISR1L		0x00001000
#define CONFIG_SYS_GPIO0_ISR1H		0x00000055
#define CONFIG_SYS_GPIO0_TSRL		0x02000000
#define CONFIG_SYS_GPIO0_TSRH		0x00000055

/*-----------------------------------------------------------------------
 * Definitions for GPIO_1 setup (PPC405EZ specific)
 *
 * GPIO1[0-6]	- PWM_9 to PWM_15 I/O
 * GPIO1[7]	- PWM_DIV_CLK (Out) / IRQ4 Input
 * GPIO1[8]	- TS5 Output / DAC_IP_TRIG Input
 * GPIO1[9]	- TS6 Output / ADC_IP_TRIG Input
 * GPIO1[10-12]	- UART0 Control Inputs
 * GPIO1[13]	- UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
 * GPIO1[14]	- UART0_RTS_N Output/SPI_SS_2_N Output
 * GPIO1[15]	- SPI_SS_3_N Output/UART0_RI_N Input
 * GPIO1[16]	- SPI_SS_1_N Output
 * GPIO1[17-20]	- Trace Output/External Interrupts IRQ0 - IRQ3 inputs
 */
#define CONFIG_SYS_GPIO1_TCR		0xFFFF8414
#define CONFIG_SYS_GPIO1_OSRL		0x40000110
#define CONFIG_SYS_GPIO1_OSRH		0x55455555
#define CONFIG_SYS_GPIO1_ISR1L		0x15555445
#define CONFIG_SYS_GPIO1_ISR1H		0x00000000
#define CONFIG_SYS_GPIO1_TSRL		0x00000000
#define CONFIG_SYS_GPIO1_TSRH		0x00000000

#endif	/* __CONFIG_H */
Commit	Line	Data
16c0cc1c SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/************************************************************************
	25	* acadia.h - configuration for AMCC Acadia (405EZ)
	26	***********************************************************************/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*-----------------------------------------------------------------------
	32	* High Level Configuration Options
	33	----------------------------------------------------------------------/
3cb86f3e SR	34	#define CONFIG_ACADIA 1 /* Board is Acadia */
	35	#define CONFIG_4xx 1 /* ... PPC4xx family */
	36	#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
490f2040 SR	37
	38	/*
	39	* Include common defines/options for all AMCC eval boards
	40	*/
	41	#define CONFIG_HOSTNAME acadia
	42	#include "amcc-common.h"
	43
5d4a1790	44	/* Detect Acadia PLL input clock automatically via CPLD bit */
6d0f6bcf	45	#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
5d4a1790	46	66666666 : 33333000)
16c0cc1c	47
3cb86f3e SR	48	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
3cb86f3e SR	49	#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
16c0cc1c SR	50
	51	#define CONFIG_NO_SERIAL_EEPROM
	52	/#undef CONFIG_NO_SERIAL_EEPROM/
	53
	54	#ifdef CONFIG_NO_SERIAL_EEPROM
16c0cc1c SR	55	/*----------------------------------------------------------------------------
	56	* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
	57	* assuming a 66MHz input clock to the 405EZ.
	58	---------------------------------------------------------------------------/
	59	/* #define PLLMR0_100_100_12 */
	60	#define PLLMR0_200_133_66
	61	/* #define PLLMR0_266_160_80 */
	62	/* #define PLLMR0_333_166_83 */
	63	#endif
	64
	65	/*-----------------------------------------------------------------------
	66	* Base addresses -- Note these are effective addresses where the
	67	* actual resources get mapped (not physical addresses)
	68	----------------------------------------------------------------------/
6d0f6bcf JCPV	69	#define CONFIG_SYS_FLASH_BASE 0xfe000000
	70	#define CONFIG_SYS_CPLD_BASE 0x80000000
	71	#define CONFIG_SYS_NAND_ADDR 0xd0000000
	72	#define CONFIG_SYS_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
16c0cc1c	73
3cb86f3e SR	74	/*-----------------------------------------------------------------------
	75	* Initial RAM & stack pointer
	76	----------------------------------------------------------------------/
6d0f6bcf	77	#define CONFIG_SYS_TEMP_STACK_OCM 1 /* OCM as init ram */
3cb86f3e SR	78
3cb86f3e SR	79	/* On Chip Memory location */
6d0f6bcf JCPV	80	#define CONFIG_SYS_OCM_DATA_ADDR 0xf8000000
	81	#define CONFIG_SYS_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
	82	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SRAM */
	83	#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
3cb86f3e	84
6d0f6bcf JCPV	85	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size for initial data */
	86	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	87	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
3cb86f3e SR	88
	89	/*-----------------------------------------------------------------------
	90	* Serial Port
	91	----------------------------------------------------------------------/
6d0f6bcf JCPV	92	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
6d0f6bcf JCPV	93	#define CONFIG_SYS_BASE_BAUD 691200
3cb86f3e SR	94
	95	/*-----------------------------------------------------------------------
	96	* Environment
	97	----------------------------------------------------------------------/
16c0cc1c	98	#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
5a1aceb0	99	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
16c0cc1c	100	#else
51bfee19	101	#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
0e8d1586	102	#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
16c0cc1c SR	103	#endif
16c0cc1c SR	104
3cb86f3e SR	105	/*-----------------------------------------------------------------------
	106	* FLASH related
	107	----------------------------------------------------------------------/
c440bfe6	108	#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
6d0f6bcf	109	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	110	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
3cb86f3e	111
6d0f6bcf JCPV	112	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
	113	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	114	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
3cb86f3e	115
6d0f6bcf JCPV	116	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	117	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
3cb86f3e	118
6d0f6bcf JCPV	119	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
6d0f6bcf JCPV	120	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
3cb86f3e	121
c440bfe6	122	#else
6d0f6bcf	123	#define CONFIG_SYS_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
c440bfe6 SR	124	#endif
c440bfe6 SR	125
5a1aceb0	126	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	127	#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
6d0f6bcf	128	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586	129	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
3cb86f3e SR	130
3cb86f3e SR	131	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	132	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	133	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
3cb86f3e SR	134	#endif
3cb86f3e SR	135
c440bfe6 SR	136	/*
	137	* IPL (Initial Program Loader, integrated inside CPU)
	138	* Will load first 4k from NAND (SPL) into cache and execute it from there.
	139	*
	140	* SPL (Secondary Program Loader)
	141	* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
	142	* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
	143	* controller and the NAND controller so that the special U-Boot image can be
	144	* loaded from NAND to SDRAM.
	145	*
	146	* NUB (NAND U-Boot)
	147	* This NAND U-Boot (NUB) is a special U-Boot version which can be started
	148	* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
	149	*
	150	* On 440EPx the SPL is copied to SDRAM before the NAND controller is
	151	* set up. While still running from cache, I experienced problems accessing
	152	* the NAND controller. sr - 2006-08-25
	153	*/
6d0f6bcf JCPV	154	#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
	155	#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
	156	#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
	157	#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
	158	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
	159	#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
c440bfe6 SR	160
	161	/*
	162	* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
	163	*/
6d0f6bcf JCPV	164	#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
6d0f6bcf JCPV	165	#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
c440bfe6 SR	166
	167	/*
	168	* Now the NAND chip has to be defined (no autodetection used!)
	169	*/
6d0f6bcf JCPV	170	#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
	171	#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
	172	#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
	173	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
	174	#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
	175
	176	#define CONFIG_SYS_NAND_ECCSIZE 256
	177	#define CONFIG_SYS_NAND_ECCBYTES 3
	178	#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
	179	#define CONFIG_SYS_NAND_OOBSIZE 16
	180	#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
	181	#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
c440bfe6	182
51bfee19	183	#ifdef CONFIG_ENV_IS_IN_NAND
c440bfe6 SR	184	/*
	185	* For NAND booting the environment is embedded in the U-Boot image. Please take
	186	* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
	187	*/
6d0f6bcf JCPV	188	#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
6d0f6bcf JCPV	189	#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
0e8d1586	190	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
c440bfe6 SR	191	#endif
c440bfe6 SR	192
3cb86f3e SR	193	/*-----------------------------------------------------------------------
	194	* RAM (CRAM)
	195	----------------------------------------------------------------------/
6d0f6bcf	196	#define CONFIG_SYS_MBYTES_RAM 64 /* 64MB */
3cb86f3e SR	197
	198	/*-----------------------------------------------------------------------
	199	* I2C
	200	----------------------------------------------------------------------/
6d0f6bcf	201	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
3cb86f3e	202
6d0f6bcf JCPV	203	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	204	#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
	205	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	206	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	207	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
3cb86f3e SR	208
	209	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
	210	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	211	#define CONFIG_DTT_AD7414 1 /* use AD7414 */
	212	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
6d0f6bcf JCPV	213	#define CONFIG_SYS_DTT_MAX_TEMP 70
	214	#define CONFIG_SYS_DTT_LOW_TEMP -30
	215	#define CONFIG_SYS_DTT_HYSTERESIS 3
3cb86f3e	216
3cb86f3e SR	217	/*-----------------------------------------------------------------------
	218	* Ethernet
	219	----------------------------------------------------------------------/
3cb86f3e	220	#define CONFIG_PHY_ADDR 0 /* PHY address */
d1c1ba85	221	#define CONFIG_HAS_ETH0 1
3cb86f3e	222
490f2040 SR	223	/*
	224	* Default environment variables
	225	*/
16c0cc1c	226	#define CONFIG_EXTRA_ENV_SETTINGS \
490f2040 SR	227	CONFIG_AMCC_DEF_ENV \
	228	CONFIG_AMCC_DEF_ENV_PPC \
	229	CONFIG_AMCC_DEF_ENV_NOR_UPD \
	230	CONFIG_AMCC_DEF_ENV_NAND_UPD \
16c0cc1c SR	231	"kernel_addr=fff10000\0" \
16c0cc1c SR	232	"ramdisk_addr=fff20000\0" \
16c0cc1c SR	233	"kozio=bootm ffc60000\0" \
16c0cc1c SR	234	""
16c0cc1c	235
16c0cc1c SR	236	#define CONFIG_USB_OHCI
	237	#define CONFIG_USB_STORAGE
	238
16c0cc1c SR	239	/* Partitions */
	240	#define CONFIG_MAC_PARTITION
	241	#define CONFIG_DOS_PARTITION
	242	#define CONFIG_ISO_PARTITION
	243
	244	#define CONFIG_SUPPORT_VFAT
	245
079a136c	246	/*
490f2040	247	* Commands additional to the ones defined in amcc-common.h
079a136c	248	*/
0b361c91	249	#define CONFIG_CMD_DTT
0b361c91	250	#define CONFIG_CMD_NAND
0b361c91 JL	251	#define CONFIG_CMD_USB
	252
	253	/*
	254	* No NOR on Acadia when NAND-booting
	255	*/
	256	#if defined(CONFIG_NAND_U_BOOT) \|\| defined(CONFIG_NAND_SPL)
	257	#undef CONFIG_CMD_FLASH
	258	#undef CONFIG_CMD_IMLS
	259	#endif
	260
16c0cc1c SR	261	/*-----------------------------------------------------------------------
	262	* NAND FLASH
	263	----------------------------------------------------------------------/
6d0f6bcf	264	#define CONFIG_SYS_MAX_NAND_DEVICE 1
16c0cc1c	265	#define NAND_MAX_CHIPS 1
6d0f6bcf JCPV	266	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
6d0f6bcf JCPV	267	#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
16c0cc1c	268
16c0cc1c SR	269	/*-----------------------------------------------------------------------
16c0cc1c SR	270	* External Bus Controller (EBC) Setup
3cb86f3e	271	----------------------------------------------------------------------/
c440bfe6	272	#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
6d0f6bcf	273	#define CONFIG_SYS_NAND_CS 3
3cb86f3e	274	/* Memory Bank 0 (Flash) initialization */
6d0f6bcf JCPV	275	#define CONFIG_SYS_EBC_PB0AP 0x03337200
6d0f6bcf JCPV	276	#define CONFIG_SYS_EBC_PB0CR 0xfe0bc000
16c0cc1c	277
c440bfe6	278	/* Memory Bank 3 (NAND-FLASH) initialization */
6d0f6bcf JCPV	279	#define CONFIG_SYS_EBC_PB3AP 0x018003c0
6d0f6bcf JCPV	280	#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR \| 0x1c000)
c440bfe6	281
3cb86f3e SR	282	/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
3cb86f3e SR	283	/* Memory Bank 1 (CRAM) initialization */
6d0f6bcf JCPV	284	#define CONFIG_SYS_EBC_PB1AP 0x030400c0
6d0f6bcf JCPV	285	#define CONFIG_SYS_EBC_PB1CR 0x000bc000
16c0cc1c	286
3cb86f3e	287	/* Memory Bank 2 (CRAM) initialization */
6d0f6bcf JCPV	288	#define CONFIG_SYS_EBC_PB2AP 0x030400c0
6d0f6bcf JCPV	289	#define CONFIG_SYS_EBC_PB2CR 0x020bc000
c440bfe6	290	#else
6d0f6bcf	291	#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
c440bfe6	292	/* Memory Bank 0 (NAND-FLASH) initialization */
6d0f6bcf JCPV	293	#define CONFIG_SYS_EBC_PB0AP 0x018003c0
6d0f6bcf JCPV	294	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR \| 0x1c000)
16c0cc1c	295
c440bfe6 SR	296	/*
	297	* When NAND-booting the CRAM EBC setup must be done in sync mode, since the
	298	* NAND-SPL already initialized the CRAM and EBC to sync mode.
	299	*/
	300	/* Memory Bank 1 (CRAM) initialization */
6d0f6bcf JCPV	301	#define CONFIG_SYS_EBC_PB1AP 0x9C0201C0
6d0f6bcf JCPV	302	#define CONFIG_SYS_EBC_PB1CR 0x000bc000
c440bfe6 SR	303
c440bfe6 SR	304	/* Memory Bank 2 (CRAM) initialization */
6d0f6bcf JCPV	305	#define CONFIG_SYS_EBC_PB2AP 0x9C0201C0
6d0f6bcf JCPV	306	#define CONFIG_SYS_EBC_PB2CR 0x020bc000
c440bfe6	307	#endif
16c0cc1c	308
3cb86f3e	309	/* Memory Bank 4 (CPLD) initialization */
6d0f6bcf JCPV	310	#define CONFIG_SYS_EBC_PB4AP 0x04006000
6d0f6bcf JCPV	311	#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CPLD_BASE \| 0x18000)
16c0cc1c	312
6d0f6bcf	313	#define CONFIG_SYS_EBC_CFG 0xf8400000
16c0cc1c	314
3cb86f3e SR	315	/*-----------------------------------------------------------------------
	316	* GPIO Setup
	317	----------------------------------------------------------------------/
6d0f6bcf JCPV	318	#define CONFIG_SYS_GPIO_CRAM_CLK 8
	319	#define CONFIG_SYS_GPIO_CRAM_WAIT 9 /* GPIO-In */
	320	#define CONFIG_SYS_GPIO_CRAM_ADV 10
	321	#define CONFIG_SYS_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
3cb86f3e	322
16c0cc1c SR	323	/*-----------------------------------------------------------------------
	324	* Definitions for GPIO_0 setup (PPC405EZ specific)
	325	*
5d4a1790 SR	326	* GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
5d4a1790 SR	327	* GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
16c0cc1c SR	328	* GPIO0[4] - External Bus Controller Hold Input
	329	* GPIO0[5] - External Bus Controller Priority Input
	330	* GPIO0[6] - External Bus Controller HLDA Output
	331	* GPIO0[7] - External Bus Controller Bus Request Output
	332	* GPIO0[8] - CRAM Clk Output
	333	* GPIO0[9] - External Bus Controller Ready Input
	334	* GPIO0[10] - CRAM Adv Output
	335	* GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
	336	* GPIO0[25] - External DMA Request Input
	337	* GPIO0[26] - External DMA EOT I/O
	338	* GPIO0[25] - External DMA Ack_n Output
	339	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	340	* GPIO0[28-30] - Trace Outputs / PWM Inputs
	341	* GPIO0[31] - PWM_8 I/O
	342	*/
6d0f6bcf JCPV	343	#define CONFIG_SYS_GPIO0_TCR 0xC0A00000
	344	#define CONFIG_SYS_GPIO0_OSRL 0x50004400
	345	#define CONFIG_SYS_GPIO0_OSRH 0x02000055
	346	#define CONFIG_SYS_GPIO0_ISR1L 0x00001000
	347	#define CONFIG_SYS_GPIO0_ISR1H 0x00000055
	348	#define CONFIG_SYS_GPIO0_TSRL 0x02000000
	349	#define CONFIG_SYS_GPIO0_TSRH 0x00000055
16c0cc1c SR	350
	351	/*-----------------------------------------------------------------------
	352	* Definitions for GPIO_1 setup (PPC405EZ specific)
	353	*
	354	* GPIO1[0-6] - PWM_9 to PWM_15 I/O
	355	* GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
	356	* GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
	357	* GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
	358	* GPIO1[10-12] - UART0 Control Inputs
	359	* GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
	360	* GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
	361	* GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
	362	* GPIO1[16] - SPI_SS_1_N Output
	363	* GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
	364	*/
6d0f6bcf JCPV	365	#define CONFIG_SYS_GPIO1_TCR 0xFFFF8414
	366	#define CONFIG_SYS_GPIO1_OSRL 0x40000110
	367	#define CONFIG_SYS_GPIO1_OSRH 0x55455555
	368	#define CONFIG_SYS_GPIO1_ISR1L 0x15555445
	369	#define CONFIG_SYS_GPIO1_ISR1H 0x00000000
	370	#define CONFIG_SYS_GPIO1_TSRL 0x00000000
	371	#define CONFIG_SYS_GPIO1_TSRH 0x00000000
16c0cc1c	372
16c0cc1c	373	#endif /* __CONFIG_H */