[people/ms/u-boot.git] / include / configs / actux4.h

/*
 * (C) Copyright 2007
 * Michael Schwingen, michael@schwingen.org
 *
 * Configuration settings for the AcTux-4 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_IXP425			1
#define CONFIG_ACTUX4			1

#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

#define CONFIG_SYS_IXP425_CONSOLE		IXP425_UART1
#define CONFIG_BAUDRATE			115200
#define CONFIG_BOOTDELAY		3
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/***************************************************************
 * U-boot generic defines start here.
 ***************************************************************/
#undef CONFIG_USE_IRQ

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE		128

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF

#define CONFIG_BOOTCOMMAND		"run boot_flash"
/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG		1
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#if defined(CONFIG_CMD_KGDB)
# define CONFIG_KGDB_BAUDRATE		230400
/* which serial port to use */
# define CONFIG_KGDB_SER_INDEX		1
#endif

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT			"=> "
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE			256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS			16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START		0x00400000
#define CONFIG_SYS_MEMTEST_END			0x00800000

/* everything, incl board info, in Hz */
#undef  CONFIG_SYS_CLKS_IN_HZ
/* spec says 66.666 MHz, but it appears to be 33 */
#define CONFIG_SYS_HZ				3333333

/* default load address */
#define CONFIG_SYS_LOAD_ADDR			0x00010000

/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
					  115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE	1

/*
 * Stack sizes
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
#endif

/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0			0xbd113003

/* SDRAM settings */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			0x00000000
#define CONFIG_SYS_DRAM_BASE			0x00000000

/* 32MB SDRAM */
#define CONFIG_SYS_SDR_CONFIG			0x18
#define PHYS_SDRAM_1_SIZE		0x02000000
#define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
#define CONFIG_SYS_SDR_MODE_CONFIG		0x1
#define CONFIG_SYS_DRAM_SIZE			0x02000000

/* FLASH organization */
#define CONFIG_SYS_MAX_FLASH_BANKS		2
/* max # of sectors per chip */
#define CONFIG_SYS_MAX_FLASH_SECT		70
#define PHYS_FLASH_1			0x50000000
#define PHYS_FLASH_2			0x51000000
#define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1, PHYS_FLASH_2 }

#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN			(252 << 10)

/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* board provides its own flash_init code */
#define CONFIG_FLASH_CFI_LEGACY		1
/* no byte writes on IXP4xx */
#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
/* SST 39VF020 etc. support */
#define CONFIG_SYS_FLASH_LEGACY_256Kx8	1

/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO

/* Ethernet */

/* include IXP4xx NPE support */
#define CONFIG_IXP4XX_NPE		1
/* use separate flash sector with ucode images */
#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE	0x51000000

#define CONFIG_NET_MULTI		1
/* NPE0 PHY address */
#define	CONFIG_PHY_ADDR			0x1C
/* MII PHY management */
#define CONFIG_MII			1
/* Number of ethernet rx buffers & descriptors */
#define CONFIG_SYS_RX_ETH_BUFFER		16

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#undef  CONFIG_CMD_NFS

/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE		32

/* environment organization: one complete 4k flash sector */
#define	CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_SIZE			0x1000
#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x3f000)

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);"			\
	"IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0"		\
	"kerneladdr=51020000\0"						\
	"rootaddr=51160000\0"						\
	"loadaddr=10000\0"						\
	"updateboot_ser=mw.b 10000 ff 40000;"				\
	" loady ${loadaddr};"						\
	" run eraseboot writeboot\0"					\
	"updateboot_net=mw.b 10000 ff 40000;"				\
	" tftp ${loadaddr} u-boot.bin;"					\
	" run eraseboot writeboot\0"					\
	"eraseboot=protect off 50000000 5003efff;"			\
	" erase 50000000 +${filesize}\0"				\
	"writeboot=cp.b 10000 50000000 ${filesize}\0"			\
	"eraseenv=protect off 5003f000 5003ffff;"			\
	" erase 5003f000 5003ffff\0"					\
	"updateroot=tftp ${loadaddr} ${rootfile};"			\
	" era ${rootaddr} +${filesize};"				\
	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
	" era ${kerneladdr} +${filesize};"				\
	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4"	\
	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4"	\
	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
	"boot_flash=run flashargs addtty addeth;"			\
	" bootm ${kerneladdr}\0"					\
	"boot_net=run netargs addtty addeth;"				\
	" tftpboot ${loadaddr} ${kernelfile};"				\
	" bootm\0"

#endif /* __CONFIG_H */
Commit	Line	Data
66a4344a MS	1	/*
	2	* (C) Copyright 2007
	3	* Michael Schwingen, michael@schwingen.org
	4	*
	5	* Configuration settings for the AcTux-4 board.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	#define CONFIG_IXP425 1
	30	#define CONFIG_ACTUX4 1
	31
	32	#define CONFIG_DISPLAY_CPUINFO 1
	33	#define CONFIG_DISPLAY_BOARDINFO 1
	34
6d0f6bcf	35	#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1
66a4344a MS	36	#define CONFIG_BAUDRATE 115200
	37	#define CONFIG_BOOTDELAY 3
	38	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	39
	40	/***************************************************************
	41	* U-boot generic defines start here.
	42	***************************************************************/
	43	#undef CONFIG_USE_IRQ
	44
	45	/* Size of malloc() pool */
6d0f6bcf	46	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
66a4344a	47	/* size in bytes reserved for initial data */
6d0f6bcf	48	#define CONFIG_SYS_GBL_DATA_SIZE 128
66a4344a MS	49
	50	/* allow to overwrite serial and ethaddr */
	51	#define CONFIG_ENV_OVERWRITE
	52
	53	/* Command line configuration */
	54	#include <config_cmd_default.h>
	55
	56	#define CONFIG_CMD_ELF
	57
	58	#define CONFIG_BOOTCOMMAND "run boot_flash"
	59	/* enable passing of ATAGs */
	60	#define CONFIG_CMDLINE_TAG 1
	61	#define CONFIG_SETUP_MEMORY_TAGS 1
	62	#define CONFIG_INITRD_TAG 1
	63
	64	#if defined(CONFIG_CMD_KGDB)
	65	# define CONFIG_KGDB_BAUDRATE 230400
	66	/* which serial port to use */
	67	# define CONFIG_KGDB_SER_INDEX 1
	68	#endif
	69
	70	/* Miscellaneous configurable options */
6d0f6bcf JCPV	71	#define CONFIG_SYS_LONGHELP
6d0f6bcf JCPV	72	#define CONFIG_SYS_PROMPT "=> "
66a4344a	73	/* Console I/O Buffer Size */
6d0f6bcf	74	#define CONFIG_SYS_CBSIZE 256
66a4344a	75	/* Print Buffer Size */
6d0f6bcf	76	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
66a4344a	77	/* max number of command args */
6d0f6bcf	78	#define CONFIG_SYS_MAXARGS 16
66a4344a	79	/* Boot Argument Buffer Size */
6d0f6bcf	80	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
66a4344a	81
6d0f6bcf JCPV	82	#define CONFIG_SYS_MEMTEST_START 0x00400000
6d0f6bcf JCPV	83	#define CONFIG_SYS_MEMTEST_END 0x00800000
66a4344a MS	84
66a4344a MS	85	/* everything, incl board info, in Hz */
6d0f6bcf	86	#undef CONFIG_SYS_CLKS_IN_HZ
66a4344a	87	/* spec says 66.666 MHz, but it appears to be 33 */
6d0f6bcf	88	#define CONFIG_SYS_HZ 3333333
66a4344a MS	89
66a4344a MS	90	/* default load address */
6d0f6bcf	91	#define CONFIG_SYS_LOAD_ADDR 0x00010000
66a4344a MS	92
66a4344a MS	93	/* valid baudrates */
6d0f6bcf	94	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
66a4344a MS	95	115200, 230400 }
	96	#define CONFIG_SERIAL_RTS_ACTIVE 1
	97
	98	/*
	99	* Stack sizes
	100	* The stack sizes are set up in start.S using the settings below
	101	*/
	102	#define CONFIG_STACKSIZE (1281024) / regular stack */
	103	#ifdef CONFIG_USE_IRQ
	104	# define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	105	# define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	106	#endif
	107
	108	/* Expansion bus settings */
6d0f6bcf	109	#define CONFIG_SYS_EXP_CS0 0xbd113003
66a4344a MS	110
	111	/* SDRAM settings */
	112	#define CONFIG_NR_DRAM_BANKS 1
	113	#define PHYS_SDRAM_1 0x00000000
6d0f6bcf	114	#define CONFIG_SYS_DRAM_BASE 0x00000000
66a4344a MS	115
66a4344a MS	116	/* 32MB SDRAM */
6d0f6bcf	117	#define CONFIG_SYS_SDR_CONFIG 0x18
66a4344a	118	#define PHYS_SDRAM_1_SIZE 0x02000000
6d0f6bcf JCPV	119	#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
	120	#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
	121	#define CONFIG_SYS_DRAM_SIZE 0x02000000
66a4344a MS	122
66a4344a MS	123	/* FLASH organization */
6d0f6bcf	124	#define CONFIG_SYS_MAX_FLASH_BANKS 2
66a4344a	125	/* max # of sectors per chip */
6d0f6bcf	126	#define CONFIG_SYS_MAX_FLASH_SECT 70
66a4344a MS	127	#define PHYS_FLASH_1 0x50000000
66a4344a MS	128	#define PHYS_FLASH_2 0x51000000
6d0f6bcf	129	#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
66a4344a	130
6d0f6bcf JCPV	131	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	132	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
	133	#define CONFIG_SYS_MONITOR_LEN (252 << 10)
66a4344a MS	134
66a4344a MS	135	/* Use common CFI driver */
6d0f6bcf	136	#define CONFIG_SYS_FLASH_CFI
00b1883a	137	#define CONFIG_FLASH_CFI_DRIVER
66a4344a MS	138	/* board provides its own flash_init code */
	139	#define CONFIG_FLASH_CFI_LEGACY 1
	140	/* no byte writes on IXP4xx */
6d0f6bcf	141	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
66a4344a	142	/* SST 39VF020 etc. support */
6d0f6bcf	143	#define CONFIG_SYS_FLASH_LEGACY_256Kx8 1
66a4344a MS	144
66a4344a MS	145	/* print 'E' for empty sector on flinfo */
6d0f6bcf	146	#define CONFIG_SYS_FLASH_EMPTY_INFO
66a4344a MS	147
	148	/* Ethernet */
	149
	150	/* include IXP4xx NPE support */
	151	#define CONFIG_IXP4XX_NPE 1
	152	/* use separate flash sector with ucode images */
	153	#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x51000000
	154
	155	#define CONFIG_NET_MULTI 1
	156	/* NPE0 PHY address */
	157	#define CONFIG_PHY_ADDR 0x1C
	158	/* MII PHY management */
	159	#define CONFIG_MII 1
	160	/* Number of ethernet rx buffers & descriptors */
6d0f6bcf	161	#define CONFIG_SYS_RX_ETH_BUFFER 16
66a4344a MS	162
	163	#define CONFIG_CMD_DHCP
	164	#define CONFIG_CMD_NET
	165	#define CONFIG_CMD_MII
	166	#define CONFIG_CMD_PING
	167	#undef CONFIG_CMD_NFS
	168
	169	/* BOOTP options */
	170	#define CONFIG_BOOTP_BOOTFILESIZE
	171	#define CONFIG_BOOTP_BOOTPATH
	172	#define CONFIG_BOOTP_GATEWAY
	173	#define CONFIG_BOOTP_HOSTNAME
	174
	175	/* Cache Configuration */
6d0f6bcf	176	#define CONFIG_SYS_CACHELINE_SIZE 32
66a4344a MS	177
66a4344a MS	178	/* environment organization: one complete 4k flash sector */
5a1aceb0	179	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	180	#define CONFIG_ENV_SIZE 0x1000
0e8d1586 JCPV	181	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000)
66a4344a MS	182
	183	#define CONFIG_EXTRA_ENV_SETTINGS \
	184	"mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \
	185	"IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \
	186	"kerneladdr=51020000\0" \
	187	"rootaddr=51160000\0" \
	188	"loadaddr=10000\0" \
	189	"updateboot_ser=mw.b 10000 ff 40000;" \
	190	" loady ${loadaddr};" \
	191	" run eraseboot writeboot\0" \
	192	"updateboot_net=mw.b 10000 ff 40000;" \
	193	" tftp ${loadaddr} u-boot.bin;" \
	194	" run eraseboot writeboot\0" \
	195	"eraseboot=protect off 50000000 5003efff;" \
	196	" erase 50000000 +${filesize}\0" \
	197	"writeboot=cp.b 10000 50000000 ${filesize}\0" \
	198	"eraseenv=protect off 5003f000 5003ffff;" \
	199	" erase 5003f000 5003ffff\0" \
	200	"updateroot=tftp ${loadaddr} ${rootfile};" \
	201	" era ${rootaddr} +${filesize};" \
	202	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
	203	"updatekern=tftp ${loadaddr} ${kernelfile};" \
	204	" era ${kerneladdr} +${filesize};" \
	205	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
	206	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
	207	" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
	208	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
	209	" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
	210	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	211	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
	212	"boot_flash=run flashargs addtty addeth;" \
	213	" bootm ${kerneladdr}\0" \
	214	"boot_net=run netargs addtty addeth;" \
	215	" tftpboot ${loadaddr} ${kernelfile};" \
	216	" bootm\0"
	217
	218	#endif /* __CONFIG_H */