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1 | /* |
| 2 | * Copyright (C) 2011 Andes Technology Corporation |
| 3 | * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
| 4 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_H |
| 10 | #define __CONFIG_H |
| 11 | |
| 12 | #include <asm/arch-ae3xx/ae3xx.h> |
| 13 | |
| 14 | /* |
| 15 | * CPU and Board Configuration Options |
| 16 | */ |
| 17 | #define CONFIG_USE_INTERRUPT |
| 18 | |
| 19 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 20 | |
| 21 | #define CONFIG_SKIP_TRUNOFF_WATCHDOG |
| 22 | |
| 23 | #define CONFIG_CMDLINE_EDITING |
| 24 | #define CONFIG_PANIC_HANG |
| 25 | |
| 26 | #define CONFIG_SYS_ICACHE_OFF |
| 27 | #define CONFIG_SYS_DCACHE_OFF |
| 28 | |
| 29 | #define CONFIG_BOOTP_SEND_HOSTNAME |
| 30 | #define CONFIG_BOOTP_SERVERIP |
| 31 | |
| 32 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT |
| 33 | #define CONFIG_SYS_TEXT_BASE 0x00500000 |
| 34 | #ifdef CONFIG_OF_CONTROL |
| 35 | #undef CONFIG_OF_SEPARATE |
| 36 | #define CONFIG_OF_EMBED |
| 37 | #endif |
| 38 | #else |
| 39 | |
| 40 | #define CONFIG_SYS_TEXT_BASE 0x80000000 |
| 41 | #endif |
| 42 | |
| 43 | /* |
| 44 | * Timer |
| 45 | */ |
| 46 | #define CONFIG_SYS_CLK_FREQ 39062500 |
| 47 | #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ |
| 48 | |
| 49 | /* |
| 50 | * Use Externel CLOCK or PCLK |
| 51 | */ |
| 52 | #undef CONFIG_FTRTC010_EXTCLK |
| 53 | |
| 54 | #ifndef CONFIG_FTRTC010_EXTCLK |
| 55 | #define CONFIG_FTRTC010_PCLK |
| 56 | #endif |
| 57 | |
| 58 | #ifdef CONFIG_FTRTC010_EXTCLK |
| 59 | #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ |
| 60 | #else |
| 61 | #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ |
| 62 | #endif |
| 63 | |
| 64 | #define TIMER_LOAD_VAL 0xffffffff |
| 65 | |
| 66 | /* |
| 67 | * Real Time Clock |
| 68 | */ |
| 69 | #define CONFIG_RTC_FTRTC010 |
| 70 | |
| 71 | /* |
| 72 | * Real Time Clock Divider |
| 73 | * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) |
| 74 | */ |
| 75 | #define OSC_5MHZ (5*1000000) |
| 76 | #define OSC_CLK (4*OSC_5MHZ) |
| 77 | #define RTC_DIV_COUNT (0.5) /* Why?? */ |
| 78 | |
| 79 | /* |
| 80 | * Serial console configuration |
| 81 | */ |
| 82 | |
| 83 | /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ |
| 84 | #define CONFIG_CONS_INDEX 1 |
| 85 | #define CONFIG_SYS_NS16550_SERIAL |
| 86 | #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE |
| 87 | #ifndef CONFIG_DM_SERIAL |
| 88 | #define CONFIG_SYS_NS16550_REG_SIZE -4 |
| 89 | #endif |
| 90 | #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ |
| 91 | |
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92 | /* |
| 93 | * SD (MMC) controller |
| 94 | */ |
| 95 | #define CONFIG_FTSDC010 |
| 96 | #define CONFIG_FTSDC010_NUMBER 1 |
| 97 | #define CONFIG_FTSDC010_SDIO |
| 98 | |
| 99 | /* |
| 100 | * Miscellaneous configurable options |
| 101 | */ |
| 102 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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103 | |
| 104 | /* Print Buffer Size */ |
| 105 | #define CONFIG_SYS_PBSIZE \ |
| 106 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 107 | |
| 108 | /* max number of command args */ |
| 109 | #define CONFIG_SYS_MAXARGS 16 |
| 110 | |
| 111 | /* Boot Argument Buffer Size */ |
| 112 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 113 | |
| 114 | /* |
| 115 | * Size of malloc() pool |
| 116 | */ |
| 117 | /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ |
| 118 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) |
| 119 | |
| 120 | /* |
| 121 | * Physical Memory Map |
| 122 | */ |
| 123 | #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ |
| 124 | |
| 125 | #define PHYS_SDRAM_1 \ |
| 126 | (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ |
| 127 | |
| 128 | #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ |
| 129 | |
| 130 | #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ |
| 131 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ |
| 132 | |
| 133 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 |
| 134 | |
| 135 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ |
| 136 | GENERATED_GBL_DATA_SIZE) |
| 137 | |
| 138 | /* |
| 139 | * Load address and memory test area should agree with |
| 140 | * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. |
| 141 | */ |
| 142 | #define CONFIG_SYS_LOAD_ADDR 0x300000 |
| 143 | |
| 144 | /* memtest works on 63 MB in DRAM */ |
| 145 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 |
| 146 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) |
| 147 | |
| 148 | /* |
| 149 | * Static memory controller configuration |
| 150 | */ |
| 151 | #define CONFIG_FTSMC020 |
| 152 | |
| 153 | #ifdef CONFIG_FTSMC020 |
| 154 | #include <faraday/ftsmc020.h> |
| 155 | |
| 156 | #define CONFIG_SYS_FTSMC020_CONFIGS { \ |
| 157 | { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ |
| 158 | { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ |
| 159 | } |
| 160 | |
| 161 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ |
| 162 | #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ |
| 163 | FTSMC020_BANK_SIZE_32M | \ |
| 164 | FTSMC020_BANK_MBW_32) |
| 165 | |
| 166 | #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ |
| 167 | FTSMC020_TPR_AST(1) | \ |
| 168 | FTSMC020_TPR_CTW(1) | \ |
| 169 | FTSMC020_TPR_ATI(1) | \ |
| 170 | FTSMC020_TPR_AT2(1) | \ |
| 171 | FTSMC020_TPR_WTC(1) | \ |
| 172 | FTSMC020_TPR_AHT(1) | \ |
| 173 | FTSMC020_TPR_TRNA(1)) |
| 174 | #endif |
| 175 | |
| 176 | /* |
| 177 | * FLASH on ADP_AG101P is connected to BANK0 |
| 178 | * Just disalbe the other BANK to avoid detection error. |
| 179 | */ |
| 180 | #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ |
| 181 | FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ |
| 182 | FTSMC020_BANK_SIZE_32M | \ |
| 183 | FTSMC020_BANK_MBW_32) |
| 184 | |
| 185 | #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ |
| 186 | FTSMC020_TPR_CTW(3) | \ |
| 187 | FTSMC020_TPR_ATI(0xf) | \ |
| 188 | FTSMC020_TPR_AT2(3) | \ |
| 189 | FTSMC020_TPR_WTC(3) | \ |
| 190 | FTSMC020_TPR_AHT(3) | \ |
| 191 | FTSMC020_TPR_TRNA(0xf)) |
| 192 | |
| 193 | #define FTSMC020_BANK1_CONFIG (0x00) |
| 194 | #define FTSMC020_BANK1_TIMING (0x00) |
| 195 | #endif /* CONFIG_FTSMC020 */ |
| 196 | |
| 197 | /* |
| 198 | * FLASH and environment organization |
| 199 | */ |
| 200 | /* use CFI framework */ |
| 201 | #define CONFIG_SYS_FLASH_CFI |
| 202 | #define CONFIG_FLASH_CFI_DRIVER |
| 203 | |
| 204 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| 205 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 206 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL |
| 207 | |
| 208 | /* support JEDEC */ |
| 209 | #ifdef CONFIG_CFI_FLASH |
| 210 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 |
| 211 | #endif |
| 212 | |
| 213 | /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ |
| 214 | #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ |
| 215 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
| 216 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } |
| 217 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
| 218 | |
| 219 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ |
| 220 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ |
| 221 | |
| 222 | /* max number of memory banks */ |
| 223 | /* |
| 224 | * There are 4 banks supported for this Controller, |
| 225 | * but we have only 1 bank connected to flash on board |
| 226 | */ |
| 227 | #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT |
| 228 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 229 | #endif |
| 230 | #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} |
| 231 | |
| 232 | /* max number of sectors on one chip */ |
| 233 | #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) |
| 234 | #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE |
| 235 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
| 236 | |
| 237 | /* environments */ |
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238 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) |
| 239 | #define CONFIG_ENV_SIZE 8192 |
| 240 | #define CONFIG_ENV_OVERWRITE |
| 241 | |
| 242 | /* |
| 243 | * For booting Linux, the board info and command line data |
| 244 | * have to be in the first 16 MB of memory, since this is |
| 245 | * the maximum mapped by the Linux kernel during initialization. |
| 246 | */ |
| 247 | |
| 248 | /* Initial Memory map for Linux*/ |
| 249 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) |
| 250 | /* Increase max gunzip size */ |
| 251 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) |
| 252 | |
| 253 | #endif /* __CONFIG_H */ |
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