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8993e54b | 1 | /* |
a99715b8 | 2 | * (C) Copyright 2007, 2008 DENX Software Engineering |
8993e54b RJ |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * ADS5121 board configuration file | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
16bee7b0 | 30 | #define CONFIG_ADS5121 1 |
8993e54b RJ |
31 | /* |
32 | * Memory map for the ADS5121 board: | |
33 | * | |
34 | * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) | |
35 | * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) | |
36 | * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) | |
37 | * 0x8200_0000 - 0x8200_001F CPLD (32 B) | |
5f91db7f JR |
38 | * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) |
39 | * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) | |
40 | * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) | |
8993e54b RJ |
41 | * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) |
42 | */ | |
43 | ||
44 | /* | |
45 | * High Level Configuration Options | |
46 | */ | |
47 | #define CONFIG_E300 1 /* E300 Family */ | |
48 | #define CONFIG_MPC512X 1 /* MPC512X family */ | |
0e1bad47 YS |
49 | #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ |
50 | ||
51 | /* video */ | |
52 | #undef CONFIG_VIDEO | |
53 | ||
54 | #if defined(CONFIG_VIDEO) | |
55 | #define CONFIG_CFB_CONSOLE | |
56 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
57 | #endif | |
8993e54b | 58 | |
5f91db7f | 59 | /* CONFIG_PCI is defined at config time */ |
8993e54b | 60 | |
f31c49db | 61 | #ifdef CONFIG_ADS5121_REV2 |
6d0f6bcf | 62 | #define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */ |
f31c49db | 63 | #else |
6d0f6bcf | 64 | #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ |
f31c49db MM |
65 | #define CONFIG_PCI |
66 | #endif | |
8993e54b RJ |
67 | |
68 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ | |
0e1bad47 | 69 | #define CONFIG_MISC_INIT_R |
8993e54b | 70 | |
6d0f6bcf JCPV |
71 | #define CONFIG_SYS_IMMR 0x80000000 |
72 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) | |
8993e54b | 73 | |
6d0f6bcf JCPV |
74 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
75 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
8993e54b RJ |
76 | |
77 | /* | |
78 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
79 | */ | |
f31c49db | 80 | #ifdef CONFIG_ADS5121_REV2 |
6d0f6bcf | 81 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
f31c49db | 82 | #else |
6d0f6bcf | 83 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
f31c49db | 84 | #endif |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
86 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
8993e54b RJ |
87 | |
88 | /* DDR Controller Configuration | |
b1b54e35 WD |
89 | * |
90 | * SYS_CFG: | |
91 | * [31:31] MDDRC Soft Reset: Diabled | |
92 | * [30:30] DRAM CKE pin: Enabled | |
93 | * [29:29] DRAM CLK: Enabled | |
94 | * [28:28] Command Mode: Enabled (For initialization only) | |
95 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
96 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
97 | * [20:19] Read Test: DON'T USE | |
98 | * [18:18] Self Refresh: Enabled | |
99 | * [17:17] 16bit Mode: Disabled | |
100 | * [16:13] Ready Delay: 2 | |
101 | * [12:12] Half DQS Delay: Disabled | |
102 | * [11:11] Quarter DQS Delay: Disabled | |
103 | * [10:08] Write Delay: 2 | |
104 | * [07:07] Early ODT: Disabled | |
105 | * [06:06] On DIE Termination: Disabled | |
106 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
107 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
108 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
109 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
110 | * [01:01] FIFO Overlfow Enabled: Enabled | |
111 | * [00:00] FIFO Underflow Enabled: Enabled | |
112 | * TIME_CFG0 | |
113 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
114 | * [15:8] DRAM Command Time: 0 CSB clocks | |
115 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
116 | * TIME_CFG1 | |
117 | * [31:26] DRAM tRFC: | |
118 | * [25:21] DRAM tWR1: | |
119 | * [20:17] DRAM tWRT1: | |
120 | * [16:11] DRAM tDRR: | |
121 | * [10:05] DRAM tRC: | |
122 | * [04:00] DRAM tRAS: | |
123 | * TIME_CFG2 | |
124 | * [31:28] DRAM tRCD: | |
125 | * [27:23] DRAM tFAW: | |
126 | * [22:19] DRAM tRTW1: | |
127 | * [18:15] DRAM tCCD: | |
128 | * [14:10] DRAM tRTP: | |
129 | * [09:05] DRAM tRP: | |
130 | * [04:00] DRAM tRPA | |
131 | */ | |
f31c49db | 132 | #ifdef CONFIG_ADS5121_REV2 |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 |
134 | #define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 | |
135 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 | |
136 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 | |
f31c49db | 137 | #else |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 |
139 | #define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 | |
140 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 | |
141 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 | |
f31c49db | 142 | #endif |
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 |
144 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E | |
145 | #define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E | |
146 | ||
147 | #define CONFIG_SYS_MICRON_NOP 0x01380000 | |
148 | #define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 | |
149 | #define CONFIG_SYS_MICRON_EM2 0x01020000 | |
150 | #define CONFIG_SYS_MICRON_EM3 0x01030000 | |
151 | #define CONFIG_SYS_MICRON_EN_DLL 0x01010000 | |
152 | #define CONFIG_SYS_MICRON_RFSH 0x01080000 | |
153 | #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 | |
154 | #define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 | |
8993e54b RJ |
155 | |
156 | /* DDR Priority Manager Configuration */ | |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 |
158 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 | |
159 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 | |
160 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC | |
161 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA | |
162 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 | |
163 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 | |
164 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 | |
165 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 | |
166 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 | |
167 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 | |
168 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 | |
169 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 | |
170 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa | |
171 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa | |
172 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 | |
173 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 | |
174 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 | |
175 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 | |
176 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 | |
177 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 | |
178 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 | |
179 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 | |
8993e54b RJ |
180 | |
181 | /* | |
182 | * NOR FLASH on the Local Bus | |
183 | */ | |
f31c49db | 184 | #undef CONFIG_BKUP_FLASH |
6d0f6bcf | 185 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 186 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
f31c49db | 187 | #ifdef CONFIG_BKUP_FLASH |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
189 | #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */ | |
f31c49db | 190 | #else |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ |
192 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */ | |
f31c49db | 193 | #endif |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
195 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
196 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
197 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
8993e54b | 198 | |
6d0f6bcf | 199 | #undef CONFIG_SYS_FLASH_CHECKSUM |
8993e54b RJ |
200 | |
201 | /* | |
202 | * CPLD registers area is really only 32 bytes in size, but the smallest possible LP | |
203 | * window is 64KB | |
204 | */ | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_CPLD_BASE 0x82000000 |
206 | #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ | |
8993e54b | 207 | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_SRAM_BASE 0x30000000 |
209 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ | |
8993e54b | 210 | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ |
212 | #define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ | |
213 | #define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ | |
8993e54b RJ |
214 | |
215 | /* Use SRAM for initial stack */ | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */ |
217 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */ | |
8993e54b | 218 | |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
220 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
221 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
8993e54b | 222 | |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */ |
224 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
0e1bad47 | 225 | #ifdef CONFIG_FSL_DIU_FB |
6d0f6bcf | 226 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ |
0e1bad47 | 227 | #else |
6d0f6bcf | 228 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
0e1bad47 | 229 | #endif |
8993e54b RJ |
230 | |
231 | /* | |
232 | * Serial Port | |
233 | */ | |
234 | #define CONFIG_CONS_INDEX 1 | |
235 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
236 | ||
237 | /* | |
238 | * Serial console configuration | |
239 | */ | |
240 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ | |
241 | #if CONFIG_PSC_CONSOLE != 3 | |
242 | #error CONFIG_PSC_CONSOLE must be 3 | |
243 | #endif | |
244 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 245 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8993e54b RJ |
246 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
247 | ||
248 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
249 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
250 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
251 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
252 | ||
253 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
254 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
255 | #define CONFIG_SYS_HUSH_PARSER |
256 | #ifdef CONFIG_SYS_HUSH_PARSER | |
257 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
8993e54b RJ |
258 | #endif |
259 | ||
5f91db7f JR |
260 | /* |
261 | * PCI | |
262 | */ | |
263 | #ifdef CONFIG_PCI | |
264 | ||
265 | /* | |
266 | * General PCI | |
267 | */ | |
6d0f6bcf JCPV |
268 | #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 |
269 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
270 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
271 | #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE) | |
272 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
273 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
274 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
275 | #define CONFIG_SYS_PCI_IO_PHYS 0x84000000 | |
276 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ | |
5f91db7f JR |
277 | |
278 | ||
279 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
280 | ||
281 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
282 | ||
283 | #endif | |
284 | ||
8993e54b RJ |
285 | /* I2C */ |
286 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
287 | #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ | |
288 | #define CONFIG_I2C_MULTI_BUS | |
289 | #define CONFIG_I2C_CMD_TREE | |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
291 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
8993e54b | 292 | #if 0 |
6d0f6bcf | 293 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
8993e54b RJ |
294 | #endif |
295 | ||
80020120 GB |
296 | /* |
297 | * EEPROM configuration | |
298 | */ | |
6d0f6bcf JCPV |
299 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ |
300 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ | |
301 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ | |
302 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ | |
80020120 | 303 | |
8993e54b RJ |
304 | /* |
305 | * Ethernet configuration | |
306 | */ | |
307 | #define CONFIG_MPC512x_FEC 1 | |
308 | #define CONFIG_NET_MULTI | |
309 | #define CONFIG_PHY_ADDR 0x1 | |
310 | #define CONFIG_MII 1 /* MII PHY management */ | |
f31c49db | 311 | #define CONFIG_FEC_AN_TIMEOUT 1 |
ef11df6b | 312 | #define CONFIG_HAS_ETH0 |
8993e54b | 313 | |
8993e54b RJ |
314 | /* |
315 | * Configure on-board RTC | |
316 | */ | |
f31c49db | 317 | #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ |
6d0f6bcf | 318 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
8993e54b RJ |
319 | |
320 | /* | |
321 | * Environment | |
322 | */ | |
5a1aceb0 | 323 | #define CONFIG_ENV_IS_IN_FLASH 1 |
8993e54b | 324 | /* This has to be a multiple of the Flash sector size */ |
6d0f6bcf | 325 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 | 326 | #define CONFIG_ENV_SIZE 0x2000 |
f31c49db | 327 | #ifdef CONFIG_BKUP_FLASH |
0e8d1586 | 328 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */ |
f31c49db | 329 | #else |
0e8d1586 | 330 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ |
f31c49db | 331 | #endif |
8993e54b RJ |
332 | |
333 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
334 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
335 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
8993e54b RJ |
336 | |
337 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 338 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
8993e54b | 339 | |
e27f3a6e WD |
340 | #include <config_cmd_default.h> |
341 | ||
342 | #define CONFIG_CMD_ASKENV | |
343 | #define CONFIG_CMD_DHCP | |
344 | #define CONFIG_CMD_I2C | |
345 | #define CONFIG_CMD_MII | |
346 | #define CONFIG_CMD_NFS | |
347 | #define CONFIG_CMD_PING | |
348 | #define CONFIG_CMD_REGINFO | |
80020120 | 349 | #define CONFIG_CMD_EEPROM |
f31c49db | 350 | #define CONFIG_CMD_DATE |
e27f3a6e | 351 | |
8993e54b | 352 | #if defined(CONFIG_PCI) |
e27f3a6e | 353 | #define CONFIG_CMD_PCI |
8993e54b RJ |
354 | #endif |
355 | ||
8993e54b | 356 | /* |
6d0f6bcf JCPV |
357 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. |
358 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set | |
8993e54b RJ |
359 | * to 0xFFFF, watchdog timeouts after about 64s. For details refer |
360 | * to chapter 36 of the MPC5121e Reference Manual. | |
361 | */ | |
66ffb188 | 362 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ |
6d0f6bcf | 363 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF |
8993e54b RJ |
364 | |
365 | /* | |
366 | * Miscellaneous configurable options | |
367 | */ | |
6d0f6bcf JCPV |
368 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
369 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
370 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
8993e54b | 371 | |
e27f3a6e | 372 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 373 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8993e54b | 374 | #else |
6d0f6bcf | 375 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8993e54b RJ |
376 | #endif |
377 | ||
378 | ||
6d0f6bcf JCPV |
379 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ |
380 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
381 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
382 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
8993e54b RJ |
383 | |
384 | /* | |
385 | * For booting Linux, the board info and command line data | |
386 | * have to be in the first 8 MB of memory, since this is | |
387 | * the maximum mapped by the Linux kernel during initialization. | |
388 | */ | |
6d0f6bcf | 389 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
8993e54b RJ |
390 | |
391 | /* Cache Configuration */ | |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_DCACHE_SIZE 32768 |
393 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
e27f3a6e | 394 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 395 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
8993e54b RJ |
396 | #endif |
397 | ||
6d0f6bcf JCPV |
398 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
399 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
400 | #define CONFIG_SYS_HID2 HID2_HBE | |
8993e54b | 401 | |
31d82672 BB |
402 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
403 | ||
8993e54b RJ |
404 | /* |
405 | * Internal Definitions | |
406 | * | |
407 | * Boot Flags | |
408 | */ | |
66ffb188 WD |
409 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
410 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
8993e54b | 411 | |
e27f3a6e | 412 | #ifdef CONFIG_CMD_KGDB |
8993e54b RJ |
413 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
414 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
415 | #endif | |
416 | ||
417 | /* | |
418 | * Environment Configuration | |
419 | */ | |
66ffb188 | 420 | #define CONFIG_TIMESTAMP |
8993e54b RJ |
421 | |
422 | #define CONFIG_HOSTNAME ads5121 | |
8d103071 | 423 | #define CONFIG_BOOTFILE ads5121/uImage |
dd820b03 | 424 | #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx |
8993e54b | 425 | |
8d103071 | 426 | #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ |
8993e54b | 427 | |
e27f3a6e | 428 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
8993e54b RJ |
429 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
430 | ||
431 | #define CONFIG_BAUDRATE 115200 | |
432 | ||
433 | #define CONFIG_PREBOOT "echo;" \ | |
5b0b2b6f | 434 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
8993e54b RJ |
435 | "echo" |
436 | ||
437 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8d103071 | 438 | "u-boot_addr_r=200000\0" \ |
51e46e28 WD |
439 | "kernel_addr_r=600000\0" \ |
440 | "fdt_addr_r=880000\0" \ | |
441 | "ramdisk_addr_r=900000\0" \ | |
8d103071 | 442 | "u-boot_addr=FFF00000\0" \ |
51e46e28 WD |
443 | "kernel_addr=FFC40000\0" \ |
444 | "fdt_addr=FFEC0000\0" \ | |
445 | "ramdisk_addr=FC040000\0" \ | |
8d103071 | 446 | "ramdiskfile=ads5121/uRamdisk\0" \ |
8d103071 | 447 | "u-boot=ads5121/u-boot.bin\0" \ |
51e46e28 WD |
448 | "bootfile=ads5121/uImage\0" \ |
449 | "fdtfile=ads5121/ads5121.dtb\0" \ | |
450 | "rootpath=/opt/eldk/ppc_6xx\n" \ | |
8993e54b | 451 | "netdev=eth0\0" \ |
8d103071 | 452 | "consdev=ttyPSC0\0" \ |
8993e54b RJ |
453 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
454 | "nfsroot=${serverip}:${rootpath}\0" \ | |
455 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
456 | "addip=setenv bootargs ${bootargs} " \ | |
457 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
458 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8d103071 WD |
459 | "addtty=setenv bootargs ${bootargs} " \ |
460 | "console=${consdev},${baudrate}\0" \ | |
8993e54b | 461 | "flash_nfs=run nfsargs addip addtty;" \ |
a99715b8 | 462 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
8993e54b | 463 | "flash_self=run ramargs addip addtty;" \ |
8d103071 WD |
464 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
465 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
466 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
467 | "run nfsargs addip addtty;" \ | |
468 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
469 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
470 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
a99715b8 | 471 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
8d103071 | 472 | "run ramargs addip addtty;" \ |
5b0b2b6f | 473 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ |
a99715b8 | 474 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ |
8d103071 WD |
475 | "update=protect off ${u-boot_addr} +${filesize};" \ |
476 | "era ${u-boot_addr} +${filesize};" \ | |
477 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
478 | "upd=run load update\0" \ | |
8993e54b RJ |
479 | "" |
480 | ||
8993e54b RJ |
481 | #define CONFIG_BOOTCOMMAND "run flash_self" |
482 | ||
281ff9a4 GB |
483 | #define CONFIG_OF_LIBFDT 1 |
484 | #define CONFIG_OF_BOARD_SETUP 1 | |
ef11df6b | 485 | #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 |
281ff9a4 GB |
486 | |
487 | #define OF_CPU "PowerPC,5121@0" | |
ef11df6b | 488 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" |
281ff9a4 | 489 | #define OF_TBCLK (bd->bi_busfreq / 4) |
ac915283 | 490 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" |
281ff9a4 | 491 | |
8993e54b | 492 | #endif /* __CONFIG_H */ |