[people/ms/u-boot.git] / include / configs / at91cap9adk.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian.pop@leadtechdesign.com>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * Configuation settings for the AT91CAP9ADK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
#define AT91_CPU_NAME		"AT91CAP9"
#define AT91_MAIN_CLOCK		200000000	/* from 12 MHz crystal */
#define AT91_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
#define CONFIG_SYS_HZ			1000000		/* 1us resolution */

#define AT91_SLOW_CLOCK		32768	/* slow clock */

#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
#define CONFIG_AT91CAP9		1	/* It's an Atmel AT91CAP9 SoC	*/
#define CONFIG_AT91CAP9ADK	1	/* on an AT91CAP9ADK Board	*/
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT

/*
 * Hardware drivers
 */
#define CONFIG_ATMEL_USART	1
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
#define CONFIG_USART3		1	/* USART 3 is DBGU */

/* LCD */
#define CONFIG_LCD			1
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO			1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO			1
#define CONFIG_LCD_INFO_BELOW_LOGO	1
#define CONFIG_SYS_WHITE_ON_BLACK		1
#define CONFIG_ATMEL_LCD		1
#define CONFIG_ATMEL_LCD_BGR555		1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1

#define CONFIG_BOOTDELAY	3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE	1
#define CONFIG_BOOTP_BOOTPATH		1
#define CONFIG_BOOTP_GATEWAY		1
#define CONFIG_BOOTP_HOSTNAME		1

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS

#define CONFIG_CMD_PING		1
#define CONFIG_CMD_DHCP		1
#define CONFIG_CMD_NAND		1
#define CONFIG_CMD_USB		1

/* SDRAM: Careful: this supposes an AT91CAP-MEM33 expansion card */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			0x70000000
#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */

/* DataFlash */
#define CONFIG_HAS_DATAFLASH		1
#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
#define AT91_SPI_CLK			15000000
#define DATAFLASH_TCSS			(0x1a << 16)
#define DATAFLASH_TCHS			(0x1 << 24)

/* NOR flash */
#define CONFIG_SYS_FLASH_CFI			1
#define CONFIG_FLASH_CFI_DRIVER		1
#define PHYS_FLASH_1			0x10000000
#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT		256
#define CONFIG_SYS_MAX_FLASH_BANKS		1

/* NAND flash */
#define NAND_MAX_CHIPS			1
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8			1

/* Ethernet */
#define CONFIG_MACB			1
#define CONFIG_RMII			1
#define CONFIG_NET_MULTI		1
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R		1

/* USB */
#define CONFIG_USB_OHCI_NEW		1
#define LITTLEENDIAN			1
#define CONFIG_DOS_PARTITION		1
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00700000	/* AT91_BASE_UHP */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91cap9"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2

#define CONFIG_SYS_LOAD_ADDR			0x72000000	/* load address */

#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END			0x73e00000

#define CONFIG_SYS_USE_DATAFLASH		1
#undef CONFIG_SYS_USE_NORFLASH

#ifdef CONFIG_SYS_USE_DATAFLASH

/* bootstrap + u-boot + env + linux in dataflash */
#define CONFIG_ENV_IS_IN_DATAFLASH	1
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET		0x4200
#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x72000000 0x210000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock1 "			\
				"mtdparts=physmap-flash.0:-(nor);"	\
				"at91_nand:-(root) "			\
				"rw rootfstype=jffs2"

#else

/* bootstrap + u-boot + env + linux in norflash */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_SYS_MONITOR_BASE	(PHYS_FLASH_1 + 0x8000)
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x4000
#define CONFIG_BOOTCOMMAND	"cp.b 0x10040000 0x72000000 0x200000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock4 "			\
				"mtdparts=physmap-flash.0:16k(bootstrap)ro,"\
				"16k(env),224k(uboot)ro,-(linux);"	\
				"at91_nand:-(root) "			\
				"rw rootfstype=jffs2"

#endif

#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }

#define CONFIG_SYS_PROMPT		"U-Boot> "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1

#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		ROUND(CONFIG_ENV_SIZE + 128*1024, 0x1000)
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */

#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#endif
Commit	Line	Data
6afcabf1	1	/*
983c1db0	2	* (C) Copyright 2007-2008
567fb852	3	* Stelian Pop <stelian.pop@leadtechdesign.com>
6afcabf1 SP	4	* Lead Tech Design <www.leadtechdesign.com>
	5	*
	6	* Configuation settings for the AT91CAP9ADK board.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/* ARM asynchronous clock */
c139b17d	31	#define AT91_CPU_NAME "AT91CAP9"
983c1db0 SP	32	#define AT91_MAIN_CLOCK 200000000 /* from 12 MHz crystal */
983c1db0 SP	33	#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */
6d0f6bcf	34	#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
6afcabf1 SP	35
	36	#define AT91_SLOW_CLOCK 32768 /* slow clock */
	37
	38	#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
	39	#define CONFIG_AT91CAP9 1 /* It's an Atmel AT91CAP9 SoC */
	40	#define CONFIG_AT91CAP9ADK 1 /* on an AT91CAP9ADK Board */
	41	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	42
	43	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	44	#define CONFIG_SETUP_MEMORY_TAGS 1
	45	#define CONFIG_INITRD_TAG 1
	46
	47	#define CONFIG_SKIP_LOWLEVEL_INIT
	48	#define CONFIG_SKIP_RELOCATE_UBOOT
	49
6afcabf1 SP	50	/*
	51	* Hardware drivers
	52	*/
6afcabf1 SP	53	#define CONFIG_ATMEL_USART 1
	54	#undef CONFIG_USART0
	55	#undef CONFIG_USART1
	56	#undef CONFIG_USART2
	57	#define CONFIG_USART3 1 /* USART 3 is DBGU */
	58
c139b17d SP	59	/* LCD */
	60	#define CONFIG_LCD 1
	61	#define LCD_BPP LCD_COLOR8
	62	#define CONFIG_LCD_LOGO 1
	63	#undef LCD_TEST_PATTERN
	64	#define CONFIG_LCD_INFO 1
	65	#define CONFIG_LCD_INFO_BELOW_LOGO 1
6d0f6bcf	66	#define CONFIG_SYS_WHITE_ON_BLACK 1
c139b17d SP	67	#define CONFIG_ATMEL_LCD 1
c139b17d SP	68	#define CONFIG_ATMEL_LCD_BGR555 1
6d0f6bcf	69	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
c139b17d	70
6afcabf1	71	#define CONFIG_BOOTDELAY 3
6afcabf1	72
6afcabf1 SP	73	/*
	74	* BOOTP options
	75	*/
	76	#define CONFIG_BOOTP_BOOTFILESIZE 1
	77	#define CONFIG_BOOTP_BOOTPATH 1
	78	#define CONFIG_BOOTP_GATEWAY 1
	79	#define CONFIG_BOOTP_HOSTNAME 1
	80
	81	/*
	82	* Command line configuration.
	83	*/
	84	#include <config_cmd_default.h>
	85	#undef CONFIG_CMD_BDI
	86	#undef CONFIG_CMD_IMI
	87	#undef CONFIG_CMD_AUTOSCRIPT
	88	#undef CONFIG_CMD_FPGA
	89	#undef CONFIG_CMD_LOADS
	90
	91	#define CONFIG_CMD_PING 1
	92	#define CONFIG_CMD_DHCP 1
	93	#define CONFIG_CMD_NAND 1
	94	#define CONFIG_CMD_USB 1
	95
	96	/* SDRAM: Careful: this supposes an AT91CAP-MEM33 expansion card */
	97	#define CONFIG_NR_DRAM_BANKS 1
	98	#define PHYS_SDRAM 0x70000000
	99	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	100
	101	/* DataFlash */
	102	#define CONFIG_HAS_DATAFLASH 1
6d0f6bcf JCPV	103	#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
	104	#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
	105	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
93da48b9 SP	106	#define AT91_SPI_CLK 15000000
	107	#define DATAFLASH_TCSS (0x1a << 16)
	108	#define DATAFLASH_TCHS (0x1 << 24)
6afcabf1 SP	109
6afcabf1 SP	110	/* NOR flash */
6d0f6bcf	111	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	112	#define CONFIG_FLASH_CFI_DRIVER 1
6afcabf1	113	#define PHYS_FLASH_1 0x10000000
6d0f6bcf JCPV	114	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	115	#define CONFIG_SYS_MAX_FLASH_SECT 256
	116	#define CONFIG_SYS_MAX_FLASH_BANKS 1
6afcabf1	117
6afcabf1 SP	118	/* NAND flash */
6afcabf1 SP	119	#define NAND_MAX_CHIPS 1
6d0f6bcf JCPV	120	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	121	#define CONFIG_SYS_NAND_BASE 0x40000000
	122	#define CONFIG_SYS_NAND_DBW_8 1
6afcabf1	123
6afcabf1 SP	124	/* Ethernet */
	125	#define CONFIG_MACB 1
	126	#define CONFIG_RMII 1
	127	#define CONFIG_NET_MULTI 1
	128	#define CONFIG_NET_RETRY_COUNT 20
	129	#define CONFIG_RESET_PHY_R 1
	130
	131	/* USB */
	132	#define CONFIG_USB_OHCI_NEW 1
	133	#define LITTLEENDIAN 1
	134	#define CONFIG_DOS_PARTITION 1
6d0f6bcf JCPV	135	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	136	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91_BASE_UHP */
	137	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91cap9"
	138	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
6afcabf1	139
6d0f6bcf	140	#define CONFIG_SYS_LOAD_ADDR 0x72000000 /* load address */
6afcabf1	141
6d0f6bcf JCPV	142	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
6d0f6bcf JCPV	143	#define CONFIG_SYS_MEMTEST_END 0x73e00000
6afcabf1	144
6d0f6bcf JCPV	145	#define CONFIG_SYS_USE_DATAFLASH 1
6d0f6bcf JCPV	146	#undef CONFIG_SYS_USE_NORFLASH
6afcabf1	147
6d0f6bcf	148	#ifdef CONFIG_SYS_USE_DATAFLASH
6afcabf1 SP	149
6afcabf1 SP	150	/* bootstrap + u-boot + env + linux in dataflash */
057c849c	151	#define CONFIG_ENV_IS_IN_DATAFLASH 1
6d0f6bcf	152	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
0e8d1586	153	#define CONFIG_ENV_OFFSET 0x4200
6d0f6bcf	154	#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
0e8d1586	155	#define CONFIG_ENV_SIZE 0x4200
ab52640f	156	#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm"
3267508e SP	157	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	158	"root=/dev/mtdblock1 " \
	159	"mtdparts=physmap-flash.0:-(nor);" \
	160	"at91_nand:-(root) " \
	161	"rw rootfstype=jffs2"
6afcabf1 SP	162
	163	#else
	164
	165	/* bootstrap + u-boot + env + linux in norflash */
5a1aceb0	166	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	167	#define CONFIG_SYS_MONITOR_BASE (PHYS_FLASH_1 + 0x8000)
0e8d1586 JCPV	168	#define CONFIG_ENV_OFFSET 0x4000
	169	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_ENV_OFFSET)
	170	#define CONFIG_ENV_SIZE 0x4000
6afcabf1	171	#define CONFIG_BOOTCOMMAND "cp.b 0x10040000 0x72000000 0x200000; bootm"
3267508e SP	172	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	173	"root=/dev/mtdblock4 " \
	174	"mtdparts=physmap-flash.0:16k(bootstrap)ro,"\
	175	"16k(env),224k(uboot)ro,-(linux);" \
	176	"at91_nand:-(root) " \
	177	"rw rootfstype=jffs2"
6afcabf1 SP	178
	179	#endif
	180
983c1db0	181	#define CONFIG_BAUDRATE 115200
6d0f6bcf	182	#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
6afcabf1	183
6d0f6bcf JCPV	184	#define CONFIG_SYS_PROMPT "U-Boot> "
	185	#define CONFIG_SYS_CBSIZE 256
	186	#define CONFIG_SYS_MAXARGS 16
	187	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	188	#define CONFIG_SYS_LONGHELP 1
6afcabf1 SP	189	#define CONFIG_CMDLINE_EDITING 1
6afcabf1 SP	190
983c1db0 SP	191	#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
	192	/*
	193	* Size of malloc() pool
	194	*/
6d0f6bcf JCPV	195	#define CONFIG_SYS_MALLOC_LEN ROUND(CONFIG_ENV_SIZE + 128*1024, 0x1000)
6d0f6bcf JCPV	196	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
983c1db0	197
6afcabf1 SP	198	#define CONFIG_STACKSIZE (321024) / regular stack */
	199
	200	#ifdef CONFIG_USE_IRQ
	201	#error CONFIG_USE_IRQ not supported
	202	#endif
	203
	204	#endif