[people/ms/u-boot.git] / include / configs / at91sam9263ek.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * Configuation settings for the AT91SAM9263EK board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * SoC must be defined first, before hardware.h is included.
 * In this case SoC is defined in boards.cfg.
 */
#include <asm/hardware.h>

#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
#define CONFIG_SYS_TEXT_BASE		0x21F00000
#else
#define CONFIG_SYS_TEXT_BASE		0x0000000
#endif

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768

#define CONFIG_AT91SAM9263EK	1	/* It's an AT91SAM9263EK Board */

#define CONFIG_ARCH_CPU_INIT

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
#define CONFIG_SKIP_LOWLEVEL_INIT
#else
#define CONFIG_SYS_USE_NORFLASH
#endif

/*
 * Hardware drivers
 */
#define CONFIG_ATMEL_LEGACY

/* LCD */
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO			1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO			1
#define CONFIG_LCD_INFO_BELOW_LOGO	1
#define CONFIG_ATMEL_LCD		1
#define CONFIG_ATMEL_LCD_BGR555		1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE	1
#define CONFIG_BOOTP_BOOTPATH		1
#define CONFIG_BOOTP_GATEWAY		1
#define CONFIG_BOOTP_HOSTNAME		1

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE		0x04000000

#define CONFIG_SYS_INIT_SP_ADDR \
	(ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)

/* NOR flash, if populated */
#ifdef CONFIG_SYS_USE_NORFLASH
#define CONFIG_SYS_FLASH_CFI			1
#define CONFIG_FLASH_CFI_DRIVER			1
#define PHYS_FLASH_1				0x10000000
#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT		256
#define CONFIG_SYS_MAX_FLASH_BANKS		1

#define CONFIG_SYS_MONITOR_SEC	1:0-3
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007E0000)
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)

/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_SIZE		0x10000

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
	"update=" \
		"protect off ${monitor_base} +${filesize};" \
		"erase ${monitor_base} +${filesize};" \
		"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
		"protect on ${monitor_base} +${filesize}\0"

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define MASTER_PLL_MUL		171
#define MASTER_PLL_DIV		14
#define MASTER_PLL_OUT		3

/* clocks */
#define CONFIG_SYS_MOR_VAL						\
		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
#define CONFIG_SYS_PLLAR_VAL					\
	(AT91_PMC_PLLAR_29 |					\
	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL		\
	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
	 AT91_PMC_MCKR_MDIV_2)

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL		\
	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
	AT91_PMC_MCKR_MDIV_2)

/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBICSA_VAL					\
	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
	 AT91_MATRIX_CSA_EBI_CS1A)

/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1		0
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL							\
		(AT91_SDRAMC_NC_9 |						\
		 AT91_SDRAMC_NR_13 |						\
		 AT91_SDRAMC_NB_4 |						\
		 AT91_SDRAMC_CAS_3 |						\
		 AT91_SDRAMC_DBW_32 |						\
		 (1 <<  8) |		/* Write Recovery Delay */		\
		 (7 << 12) |		/* Row Cycle Delay */			\
		 (2 << 16) |		/* Row Precharge Delay */		\
		 (2 << 20) |		/* Row to Column Delay */		\
		 (5 << 24) |		/* Active to Precharge Delay */		\
		 (1 << 28))		/* Exit Self Refresh to Active Delay */

/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL				\
	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL				\
	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
	 AT91_SMC_MODE_DBW_16 |					\
	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_MR_URSTEN |		\
		AT91_RSTC_MR_ERSTL(15))

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
		 AT91_WDT_MR_WDV(0xfff) |			\
		 AT91_WDT_MR_WDDIS |				\
		 AT91_WDT_MR_WDD(0xfff))

#endif
#endif

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8			1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
#endif

/* Ethernet */
#define CONFIG_RESET_PHY_R		1
#define CONFIG_AT91_WANTS_COMMON_PHY

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW		1
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2

#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END			0x23e00000

#ifdef CONFIG_SYS_USE_DATAFLASH

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_ENV_SECT_SIZE	0x210
#define CONFIG_ENV_SPI_MAX_HZ	15000000
#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
				"sf read 0x22000000 0x84000 0x294000; " \
				"bootm 0x22000000"

#elif CONFIG_SYS_USE_NANDFLASH

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_OFFSET		0x120000
#define CONFIG_ENV_OFFSET_REDUND	0x100000
#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
#endif

#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)

#endif
Commit	Line	Data
8e429b3e SP	1	/*
8e429b3e SP	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
8e429b3e SP	4	* Lead Tech Design <www.leadtechdesign.com>
	5	*
	6	* Configuation settings for the AT91SAM9263EK board.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
8e429b3e SP	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
cd46b0f2 XH	14	/*
	15	* SoC must be defined first, before hardware.h is included.
	16	* In this case SoC is defined in boards.cfg.
	17	*/
	18	#include <asm/hardware.h>
	19
5e7d0917	20	#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
cd46b0f2	21	#define CONFIG_SYS_TEXT_BASE 0x21F00000
5e7d0917	22	#else
	23	#define CONFIG_SYS_TEXT_BASE 0x0000000
	24	#endif
cd46b0f2	25
8e429b3e	26	/* ARM asynchronous clock */
cd46b0f2 XH	27	#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
cd46b0f2 XH	28	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
cd46b0f2 XH	29
cd46b0f2 XH	30	#define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */
8e429b3e	31
dc39ae95	32	#define CONFIG_ARCH_CPU_INIT
8e429b3e SP	33
	34	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	35	#define CONFIG_SETUP_MEMORY_TAGS 1
	36	#define CONFIG_INITRD_TAG 1
	37
1b3b7c64	38	#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
8e429b3e	39	#define CONFIG_SKIP_LOWLEVEL_INIT
cd46b0f2 XH	40	#else
cd46b0f2 XH	41	#define CONFIG_SYS_USE_NORFLASH
1b3b7c64	42	#endif
8e429b3e SP	43
	44	/*
	45	* Hardware drivers
	46	*/
cd46b0f2	47	#define CONFIG_ATMEL_LEGACY
8e429b3e	48
56a2479c	49	/* LCD */
56a2479c SP	50	#define LCD_BPP LCD_COLOR8
	51	#define CONFIG_LCD_LOGO 1
	52	#undef LCD_TEST_PATTERN
	53	#define CONFIG_LCD_INFO 1
	54	#define CONFIG_LCD_INFO_BELOW_LOGO 1
56a2479c SP	55	#define CONFIG_ATMEL_LCD 1
56a2479c SP	56	#define CONFIG_ATMEL_LCD_BGR555 1
56a2479c	57
8e429b3e SP	58	/*
	59	* BOOTP options
	60	*/
	61	#define CONFIG_BOOTP_BOOTFILESIZE 1
	62	#define CONFIG_BOOTP_BOOTPATH 1
	63	#define CONFIG_BOOTP_GATEWAY 1
	64	#define CONFIG_BOOTP_HOSTNAME 1
	65
8e429b3e SP	66	/* SDRAM */
8e429b3e SP	67	#define CONFIG_NR_DRAM_BANKS 1
cd46b0f2 XH	68	#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
	69	#define CONFIG_SYS_SDRAM_SIZE 0x04000000
	70
	71	#define CONFIG_SYS_INIT_SP_ADDR \
0b8908f9	72	(ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
8e429b3e	73
8e429b3e	74	/* NOR flash, if populated */
1b3b7c64	75	#ifdef CONFIG_SYS_USE_NORFLASH
6d0f6bcf	76	#define CONFIG_SYS_FLASH_CFI 1
1b3b7c64 JCPV	77	#define CONFIG_FLASH_CFI_DRIVER 1
1b3b7c64 JCPV	78	#define PHYS_FLASH_1 0x10000000
6d0f6bcf JCPV	79	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	80	#define CONFIG_SYS_MAX_FLASH_SECT 256
	81	#define CONFIG_SYS_MAX_FLASH_BANKS 1
1b3b7c64 JCPV	82
	83	#define CONFIG_SYS_MONITOR_SEC 1:0-3
	84	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	85	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
5e7d0917	86	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000)
1b3b7c64 JCPV	87	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
	88
	89	/* Address and size of Primary Environment Sector */
5e7d0917	90	#define CONFIG_ENV_SIZE 0x10000
1b3b7c64	91
1b3b7c64	92	#define CONFIG_EXTRA_ENV_SETTINGS \
93ea89f0	93	"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
1b3b7c64 JCPV	94	"update=" \
	95	"protect off ${monitor_base} +${filesize};" \
	96	"erase ${monitor_base} +${filesize};" \
88461f16	97	"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
1b3b7c64 JCPV	98	"protect on ${monitor_base} +${filesize}\0"
	99
	100	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	101	#define MASTER_PLL_MUL 171
	102	#define MASTER_PLL_DIV 14
1b34f00c	103	#define MASTER_PLL_OUT 3
1b3b7c64 JCPV	104
	105	/* clocks */
	106	#define CONFIG_SYS_MOR_VAL \
1b34f00c JS	107	(AT91_PMC_MOR_MOSCEN \| AT91_PMC_MOR_OSCOUNT(255))
	108	#define CONFIG_SYS_PLLAR_VAL \
	109	(AT91_PMC_PLLAR_29 \| \
	110	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) \| \
	111	AT91_PMC_PLLXR_PLLCOUNT(63) \| \
	112	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) \| \
	113	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
1b3b7c64 JCPV	114
	115	/* PCK/2 = MCK Master Clock from PLLA */
	116	#define CONFIG_SYS_MCKR1_VAL \
1b34f00c JS	117	(AT91_PMC_MCKR_CSS_SLOW \| AT91_PMC_MCKR_PRES_1 \| \
	118	AT91_PMC_MCKR_MDIV_2)
	119
1b3b7c64 JCPV	120	/* PCK/2 = MCK Master Clock from PLLA */
1b3b7c64 JCPV	121	#define CONFIG_SYS_MCKR2_VAL \
1b34f00c JS	122	(AT91_PMC_MCKR_CSS_PLLA \| AT91_PMC_MCKR_PRES_1 \| \
1b34f00c JS	123	AT91_PMC_MCKR_MDIV_2)
1b3b7c64 JCPV	124
	125	/* define PDC[31:16] as DATA[31:16] */
	126	#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
	127	/* no pull-up for D[31:16] */
	128	#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
	129	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
1b34f00c JS	130	#define CONFIG_SYS_MATRIX_EBICSA_VAL \
	131	(AT91_MATRIX_CSA_DBPUC \| AT91_MATRIX_CSA_VDDIOMSEL_3_3V \| \
	132	AT91_MATRIX_CSA_EBI_CS1A)
1b3b7c64 JCPV	133
	134	/* SDRAM */
	135	/* SDRAMC_MR Mode register */
	136	#define CONFIG_SYS_SDRC_MR_VAL1 0
	137	/* SDRAMC_TR - Refresh Timer register */
	138	#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
	139	/* SDRAMC_CR - Configuration register*/
	140	#define CONFIG_SYS_SDRC_CR_VAL \
	141	(AT91_SDRAMC_NC_9 \| \
	142	AT91_SDRAMC_NR_13 \| \
	143	AT91_SDRAMC_NB_4 \| \
	144	AT91_SDRAMC_CAS_3 \| \
	145	AT91_SDRAMC_DBW_32 \| \
	146	(1 << 8) \| /* Write Recovery Delay */ \
	147	(7 << 12) \| /* Row Cycle Delay */ \
	148	(2 << 16) \| /* Row Precharge Delay */ \
	149	(2 << 20) \| /* Row to Column Delay */ \
	150	(5 << 24) \| /* Active to Precharge Delay */ \
	151	(1 << 28)) /* Exit Self Refresh to Active Delay */
	152
	153	/* Memory Device Register -> SDRAM */
	154	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
	155	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
	156	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
	157	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
	158	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
	159	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
	160	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
	161	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
	162	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
	163	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
	164	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
	165	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
	166	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
	167	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
	168	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
	169	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
	170	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
	171	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
	172
	173	/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
1b34f00c JS	174	#define CONFIG_SYS_SMC0_SETUP0_VAL \
	175	(AT91_SMC_SETUP_NWE(10) \| AT91_SMC_SETUP_NCS_WR(10) \| \
	176	AT91_SMC_SETUP_NRD(10) \| AT91_SMC_SETUP_NCS_RD(10))
	177	#define CONFIG_SYS_SMC0_PULSE0_VAL \
	178	(AT91_SMC_PULSE_NWE(11) \| AT91_SMC_PULSE_NCS_WR(11) \| \
	179	AT91_SMC_PULSE_NRD(11) \| AT91_SMC_PULSE_NCS_RD(11))
1b3b7c64	180	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
1b34f00c	181	(AT91_SMC_CYCLE_NWE(22) \| AT91_SMC_CYCLE_NRD(22))
1b3b7c64	182	#define CONFIG_SYS_SMC0_MODE0_VAL \
1b34f00c JS	183	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	184	AT91_SMC_MODE_DBW_16 \| \
	185	AT91_SMC_MODE_TDF \| AT91_SMC_MODE_TDF_CYCLE(6))
1b3b7c64 JCPV	186
	187	/* user reset enable */
	188	#define CONFIG_SYS_RSTC_RMR_VAL \
	189	(AT91_RSTC_KEY \| \
1b34f00c JS	190	AT91_RSTC_MR_URSTEN \| \
1b34f00c JS	191	AT91_RSTC_MR_ERSTL(15))
1b3b7c64 JCPV	192
	193	/* Disable Watchdog */
	194	#define CONFIG_SYS_WDTC_WDMR_VAL \
1b34f00c JS	195	(AT91_WDT_MR_WDIDLEHLT \| AT91_WDT_MR_WDDBGHLT \| \
	196	AT91_WDT_MR_WDV(0xfff) \| \
	197	AT91_WDT_MR_WDDIS \| \
	198	AT91_WDT_MR_WDD(0xfff))
	199
1b3b7c64	200	#endif
8e429b3e SP	201	#endif
	202
	203	/* NAND flash */
74c076d6 JCPV	204	#ifdef CONFIG_CMD_NAND
74c076d6 JCPV	205	#define CONFIG_NAND_ATMEL
6d0f6bcf	206	#define CONFIG_SYS_MAX_NAND_DEVICE 1
cd46b0f2	207	#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
6d0f6bcf	208	#define CONFIG_SYS_NAND_DBW_8 1
74c076d6 JCPV	209	/* our ALE is AD21 */
	210	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	211	/* our CLE is AD22 */
	212	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
cd46b0f2 XH	213	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
cd46b0f2 XH	214	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
74c076d6	215	#endif
8e429b3e SP	216
8e429b3e SP	217	/* Ethernet */
8e429b3e	218	#define CONFIG_RESET_PHY_R 1
4535a24c	219	#define CONFIG_AT91_WANTS_COMMON_PHY
8e429b3e SP	220
8e429b3e SP	221	/* USB */
2b7178af	222	#define CONFIG_USB_ATMEL
dcd2f1a0	223	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
8e429b3e	224	#define CONFIG_USB_OHCI_NEW 1
6d0f6bcf JCPV	225	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	226	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
	227	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
	228	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
8e429b3e	229
6d0f6bcf	230	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
8e429b3e	231
cd46b0f2	232	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
6d0f6bcf	233	#define CONFIG_SYS_MEMTEST_END 0x23e00000
8e429b3e	234
6d0f6bcf	235	#ifdef CONFIG_SYS_USE_DATAFLASH
8e429b3e SP	236
8e429b3e SP	237	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
eab36f6d	238	#define CONFIG_ENV_OFFSET 0x4200
0e8d1586	239	#define CONFIG_ENV_SIZE 0x4200
eab36f6d WY	240	#define CONFIG_ENV_SECT_SIZE 0x210
	241	#define CONFIG_ENV_SPI_MAX_HZ 15000000
	242	#define CONFIG_BOOTCOMMAND "sf probe 0; " \
	243	"sf read 0x22000000 0x84000 0x294000; " \
	244	"bootm 0x22000000"
8e429b3e	245
1b3b7c64	246	#elif CONFIG_SYS_USE_NANDFLASH
8e429b3e SP	247
8e429b3e SP	248	/* bootstrap + u-boot + env + linux in nandflash */
0b8908f9	249	#define CONFIG_ENV_OFFSET 0x120000
0c58cfa9	250	#define CONFIG_ENV_OFFSET_REDUND 0x100000
0e8d1586	251	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
0c58cfa9	252	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
8e429b3e SP	253	#endif
8e429b3e SP	254
6d0f6bcf	255	#define CONFIG_SYS_LONGHELP 1
cd46b0f2	256	#define CONFIG_CMDLINE_EDITING 1
03bab009	257	#define CONFIG_AUTO_COMPLETE
8e429b3e	258
8e429b3e SP	259	/*
	260	* Size of malloc() pool
	261	*/
cd46b0f2	262	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
8e429b3e	263
8e429b3e	264	#endif