[people/ms/u-boot.git] / include / configs / at91sam9x5ek.h

/*
 * Copyright (C) 2012 Atmel Corporation
 *
 * Configuation settings for the AT91SAM9X5EK board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H__
#define __CONFIG_H__

#define CONFIG_SYS_TEXT_BASE		0x26f00000

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT

/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */

/* LCD */
#define LCD_BPP			LCD_COLOR16
#define LCD_OUTPUT_BPP		24
#define CONFIG_LCD_LOGO
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
 * NB: in this case, USB 1.1 devices won't be recognized.
 */

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */

#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)

/* DataFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED		30000000
#endif

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_DBW_8		1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5

#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif

/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC		1
#define CONFIG_ATMEL_NAND_HW_PMECC	1
#define CONFIG_PMECC_CAP		2
#define CONFIG_PMECC_SECTOR_SIZE	512

/* USB */
#ifdef CONFIG_CMD_USB
#ifndef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9x5"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
#endif
#endif

#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		0x26e00000

#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_OFFSET		0x120000
#define CONFIG_ENV_OFFSET_REDUND	0x100000
#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read " \
				"0x22000000 0x200000 0x300000; " \
				"bootm 0x22000000"
#elif defined(CONFIG_SPI_BOOT)
/* bootstrap + u-boot + env + linux in spi flash */
#define CONFIG_ENV_OFFSET	0x5000
#define CONFIG_ENV_SIZE		0x3000
#define CONFIG_ENV_SECT_SIZE	0x1000
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
				"sf read 0x22000000 0x100000 0x300000; " \
				"bootm 0x22000000"
#elif defined(CONFIG_SYS_USE_DATAFLASH)
/* bootstrap + u-boot + env + linux in data flash */
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_ENV_SECT_SIZE	0x210
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
				"sf read 0x22000000 0x84000 0x294000; " \
				"bootm 0x22000000"
#else /* CONFIG_SD_BOOT */
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_SIZE		0x4000
#endif

#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(512 * 1024 + 0x1000)

/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x300000
#define CONFIG_SPL_MAX_SIZE		0x6000
#define CONFIG_SPL_STACK		0x308000

#define CONFIG_SPL_BSS_START_ADDR	0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000

#define CONFIG_SYS_MONITOR_LEN		(512 << 10)

#define CONFIG_SYS_MASTER_CLOCK		132096000
#define CONFIG_SYS_AT91_PLLA		0x20c73f03
#define CONFIG_SYS_MCKR			0x1301
#define CONFIG_SYS_MCKR_CSS		0x1302

#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"

#elif CONFIG_SPI_BOOT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400

#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

#endif
Commit	Line	Data
f7fa2f37 BS	1	/*
	2	* Copyright (C) 2012 Atmel Corporation
	3	*
	4	* Configuation settings for the AT91SAM9X5EK board.
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
f7fa2f37 BS	7	*/
	8
	9	#ifndef __CONFIG_H__
	10	#define __CONFIG_H__
	11
77461a65 BS	12	#define CONFIG_SYS_TEXT_BASE 0x26f00000
77461a65 BS	13
f7fa2f37 BS	14	/* ARM asynchronous clock */
	15	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
	16	#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
f7fa2f37	17
f7fa2f37 BS	18	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	19	#define CONFIG_SETUP_MEMORY_TAGS
	20	#define CONFIG_INITRD_TAG
	21	#define CONFIG_SKIP_LOWLEVEL_INIT
f7fa2f37 BS	22
	23	/* general purpose I/O */
	24	#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
f7fa2f37 BS	25
f7fa2f37 BS	26	/* LCD */
f7fa2f37 BS	27	#define LCD_BPP LCD_COLOR16
	28	#define LCD_OUTPUT_BPP 24
	29	#define CONFIG_LCD_LOGO
f7fa2f37 BS	30	#define CONFIG_LCD_INFO
f7fa2f37 BS	31	#define CONFIG_LCD_INFO_BELOW_LOGO
f7fa2f37 BS	32	#define CONFIG_ATMEL_HLCD
f7fa2f37 BS	33	#define CONFIG_ATMEL_LCD_RGB565
f7fa2f37	34
f7fa2f37 BS	35
	36	/*
	37	* BOOTP options
	38	*/
	39	#define CONFIG_BOOTP_BOOTFILESIZE
	40	#define CONFIG_BOOTP_BOOTPATH
	41	#define CONFIG_BOOTP_GATEWAY
	42	#define CONFIG_BOOTP_HOSTNAME
	43
b030e731	44	/*
8850c5d5	45	* define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
b030e731 RG	46	* NB: in this case, USB 1.1 devices won't be recognized.
	47	*/
	48
f7fa2f37 BS	49	/* SDRAM */
	50	#define CONFIG_NR_DRAM_BANKS 1
	51	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	52	#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
	53
	54	#define CONFIG_SYS_INIT_SP_ADDR \
74631b69	55	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
f7fa2f37 BS	56
f7fa2f37 BS	57	/* DataFlash */
1d7442e6	58	#ifdef CONFIG_CMD_SF
1d7442e6	59	#define CONFIG_SF_DEFAULT_SPEED 30000000
f7fa2f37 BS	60	#endif
f7fa2f37 BS	61
f7fa2f37 BS	62	/* NAND flash */
	63	#ifdef CONFIG_CMD_NAND
	64	#define CONFIG_NAND_ATMEL
	65	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	66	#define CONFIG_SYS_NAND_BASE 0x40000000
	67	#define CONFIG_SYS_NAND_DBW_8 1
	68	/* our ALE is AD21 */
	69	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	70	/* our CLE is AD22 */
	71	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	72	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
	73	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
	74
8f1a80e9 TR	75	#define CONFIG_MTD_DEVICE
	76	#define CONFIG_MTD_PARTITIONS
	77	#endif
	78
df95321c WJ	79	/* PMECC & PMERRLOC */
	80	#define CONFIG_ATMEL_NAND_HWECC 1
	81	#define CONFIG_ATMEL_NAND_HW_PMECC 1
	82	#define CONFIG_PMECC_CAP 2
	83	#define CONFIG_PMECC_SECTOR_SIZE 512
df95321c	84
b030e731 RG	85	/* USB */
b030e731 RG	86	#ifdef CONFIG_CMD_USB
8850c5d5	87	#ifndef CONFIG_USB_EHCI_HCD
dcd2f1a0 BS	88	#define CONFIG_USB_ATMEL
dcd2f1a0 BS	89	#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
b030e731 RG	90	#define CONFIG_USB_OHCI_NEW
	91	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	92	#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
	93	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
	94	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
	95	#endif
b030e731 RG	96	#endif
b030e731 RG	97
f7fa2f37 BS	98	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
	99
	100	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	101	#define CONFIG_SYS_MEMTEST_END 0x26e00000
	102
5541543f	103	#ifdef CONFIG_NAND_BOOT
f7fa2f37	104	/* bootstrap + u-boot + env + linux in nandflash */
74631b69	105	#define CONFIG_ENV_OFFSET 0x120000
f7fa2f37 BS	106	#define CONFIG_ENV_OFFSET_REDUND 0x100000
	107	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
	108	#define CONFIG_BOOTCOMMAND "nand read " \
	109	"0x22000000 0x200000 0x300000; " \
	110	"bootm 0x22000000"
5541543f	111	#elif defined(CONFIG_SPI_BOOT)
1d7442e6	112	/* bootstrap + u-boot + env + linux in spi flash */
1d7442e6 BS	113	#define CONFIG_ENV_OFFSET 0x5000
	114	#define CONFIG_ENV_SIZE 0x3000
	115	#define CONFIG_ENV_SECT_SIZE 0x1000
	116	#define CONFIG_ENV_SPI_MAX_HZ 30000000
	117	#define CONFIG_BOOTCOMMAND "sf probe 0; " \
	118	"sf read 0x22000000 0x100000 0x300000; " \
	119	"bootm 0x22000000"
961ffc77 BS	120	#elif defined(CONFIG_SYS_USE_DATAFLASH)
961ffc77 BS	121	/* bootstrap + u-boot + env + linux in data flash */
961ffc77 BS	122	#define CONFIG_ENV_OFFSET 0x4200
	123	#define CONFIG_ENV_SIZE 0x4200
	124	#define CONFIG_ENV_SECT_SIZE 0x210
	125	#define CONFIG_ENV_SPI_MAX_HZ 30000000
	126	#define CONFIG_BOOTCOMMAND "sf probe 0; " \
	127	"sf read 0x22000000 0x84000 0x294000; " \
	128	"bootm 0x22000000"
5541543f	129	#else /* CONFIG_SD_BOOT */
b7e3129e	130	/* bootstrap + u-boot + env + linux in mmc */
26961772	131	#define CONFIG_ENV_SIZE 0x4000
f7fa2f37 BS	132	#endif
f7fa2f37 BS	133
f7fa2f37 BS	134	#define CONFIG_SYS_LONGHELP
	135	#define CONFIG_CMDLINE_EDITING
	136	#define CONFIG_AUTO_COMPLETE
f7fa2f37 BS	137
	138	/*
	139	* Size of malloc() pool
	140	*/
	141	#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
	142
d85e8914 BS	143	/* SPL */
	144	#define CONFIG_SPL_FRAMEWORK
	145	#define CONFIG_SPL_TEXT_BASE 0x300000
	146	#define CONFIG_SPL_MAX_SIZE 0x6000
	147	#define CONFIG_SPL_STACK 0x308000
	148
	149	#define CONFIG_SPL_BSS_START_ADDR 0x20000000
	150	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	151	#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
	152	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	153
d85e8914 BS	154	#define CONFIG_SYS_MONITOR_LEN (512 << 10)
	155
	156	#define CONFIG_SYS_MASTER_CLOCK 132096000
	157	#define CONFIG_SYS_AT91_PLLA 0x20c73f03
	158	#define CONFIG_SYS_MCKR 0x1301
	159	#define CONFIG_SYS_MCKR_CSS 0x1302
	160
5541543f	161	#ifdef CONFIG_SD_BOOT
d85e8914 BS	162	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
d85e8914 BS	163	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
d85e8914	164
5541543f WY	165	#elif CONFIG_SPI_BOOT
	166	#define CONFIG_SPL_SPI_LOAD
	167	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
	168
	169	#elif CONFIG_NAND_BOOT
d85e8914 BS	170	#define CONFIG_SPL_NAND_DRIVERS
d85e8914 BS	171	#define CONFIG_SPL_NAND_BASE
5541543f	172	#endif
d85e8914 BS	173	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	174	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	175	#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	176	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	177	#define CONFIG_SYS_NAND_OOBSIZE 64
	178	#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
	179	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
	180	#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
	181
f7fa2f37	182	#endif