[people/ms/u-boot.git] / include / configs / atstk1002.h

/*
 * Copyright (C) 2005-2006 Atmel Corporation
 *
 * Configuration settings for the ATSTK1002 CPU daughterboard
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/hardware.h>

#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_ATSTK1002
#define CONFIG_ATSTK1000

/*
 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
 * PLL frequency.
 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
 */
#define CONFIG_PLL
#define CONFIG_SYS_POWER_MANAGER
#define CONFIG_SYS_OSC0_HZ			20000000
#define CONFIG_SYS_PLL0_DIV			1
#define CONFIG_SYS_PLL0_MUL			7
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
/*
 * Set the CPU running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
 */
#define CONFIG_SYS_CLKDIV_CPU			0
/*
 * Set the HSB running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
 */
#define CONFIG_SYS_CLKDIV_HSB			1
/*
 * Set the PBA running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
 */
#define CONFIG_SYS_CLKDIV_PBA			2
/*
 * Set the PBB running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
 */
#define CONFIG_SYS_CLKDIV_PBB			1

/* Reserve VM regions for SDRAM and NOR flash */
#define CONFIG_SYS_NR_VM_REGIONS		2

/*
 * The PLLOPT register controls the PLL like this:
 *   icp = PLLOPT<2>
 *   ivco = PLLOPT<1:0>
 *
 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
 */
#define CONFIG_SYS_PLL0_OPT			0x04

#define CONFIG_USART_BASE		ATMEL_BASE_USART1
#define CONFIG_USART_ID			1

/* User serviceable stuff */

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#define CONFIG_STACKSIZE		(2048)

#define CONFIG_BAUDRATE			115200
#define CONFIG_BOOTARGS							\
	"console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"

#define CONFIG_BOOTCOMMAND						\
	"fsload; bootm $(fileaddr)"


/*
 * After booting the board for the first time, new ethernet addresses
 * should be generated and assigned to the environment variables
 * "ethaddr" and "eth1addr". This is normally done during production.
 */
#define CONFIG_OVERWRITE_ETHADDR_ONCE

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY

/* generic board */
#define CONFIG_BOARD_EARLY_INIT_R

/*
 * Command line configuration.
 */
#define CONFIG_CMD_JFFS2

#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_PORTMUX_PIO
#define CONFIG_SYS_NR_PIOS			5
#define CONFIG_SYS_HSDRAMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_GENERIC_MMC

#define CONFIG_SYS_DCACHE_LINESZ		32
#define CONFIG_SYS_ICACHE_LINESZ		32

#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

#define CONFIG_SYS_FLASH_BASE			0x00000000
#define CONFIG_SYS_FLASH_SIZE			0x800000
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_MAX_FLASH_SECT		135

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_TEXT_BASE		0x00000000

#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE			65536
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)

#define CONFIG_SYS_MALLOC_LEN			(256*1024)

/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)

/* Other configuration settings that shouldn't have to change all that often */
#define CONFIG_SYS_CBSIZE			256
#define CONFIG_SYS_MAXARGS			16
#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP

#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x700000)
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }

#endif /* __CONFIG_H */
Commit	Line	Data
6ccec449 WD	1	/*
	2	* Copyright (C) 2005-2006 Atmel Corporation
	3	*
	4	* Configuration settings for the ATSTK1002 CPU daughterboard
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
6ccec449 WD	7	*/
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
5d73bc7a	11	#include <asm/arch/hardware.h>
a23e277c	12
e3e8d463 AB	13	#define CONFIG_AT32AP
	14	#define CONFIG_AT32AP7000
	15	#define CONFIG_ATSTK1002
	16	#define CONFIG_ATSTK1000
6ccec449	17
6ccec449	18	/*
a4f3aab6 EA	19	* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
	20	* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
	21	* PLL frequency.
6d0f6bcf	22	* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
6ccec449	23	*/
e3e8d463 AB	24	#define CONFIG_PLL
e3e8d463 AB	25	#define CONFIG_SYS_POWER_MANAGER
6d0f6bcf JCPV	26	#define CONFIG_SYS_OSC0_HZ 20000000
	27	#define CONFIG_SYS_PLL0_DIV 1
	28	#define CONFIG_SYS_PLL0_MUL 7
	29	#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
a4f3aab6 EA	30	/*
a4f3aab6 EA	31	* Set the CPU running at:
6d0f6bcf	32	* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
a4f3aab6	33	*/
6d0f6bcf	34	#define CONFIG_SYS_CLKDIV_CPU 0
a4f3aab6 EA	35	/*
a4f3aab6 EA	36	* Set the HSB running at:
6d0f6bcf	37	* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
a4f3aab6	38	*/
6d0f6bcf	39	#define CONFIG_SYS_CLKDIV_HSB 1
a4f3aab6 EA	40	/*
a4f3aab6 EA	41	* Set the PBA running at:
6d0f6bcf	42	* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
a4f3aab6	43	*/
6d0f6bcf	44	#define CONFIG_SYS_CLKDIV_PBA 2
a4f3aab6 EA	45	/*
a4f3aab6 EA	46	* Set the PBB running at:
6d0f6bcf	47	* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
a4f3aab6	48	*/
6d0f6bcf	49	#define CONFIG_SYS_CLKDIV_PBB 1
6ccec449	50
1f36f73f HS	51	/* Reserve VM regions for SDRAM and NOR flash */
	52	#define CONFIG_SYS_NR_VM_REGIONS 2
	53
6ccec449 WD	54	/*
	55	* The PLLOPT register controls the PLL like this:
	56	* icp = PLLOPT<2>
	57	* ivco = PLLOPT<1:0>
	58	*
	59	* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
	60	*/
6d0f6bcf	61	#define CONFIG_SYS_PLL0_OPT 0x04
6ccec449	62
f4278b71 AB	63	#define CONFIG_USART_BASE ATMEL_BASE_USART1
f4278b71 AB	64	#define CONFIG_USART_ID 1
6ccec449 WD	65
6ccec449 WD	66	/* User serviceable stuff */
8e687518	67
e3e8d463 AB	68	#define CONFIG_CMDLINE_TAG
	69	#define CONFIG_SETUP_MEMORY_TAGS
	70	#define CONFIG_INITRD_TAG
6ccec449 WD	71
	72	#define CONFIG_STACKSIZE (2048)
	73
	74	#define CONFIG_BAUDRATE 115200
	75	#define CONFIG_BOOTARGS \
e80e585b	76	"console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
1b804b22 HS	77
	78	#define CONFIG_BOOTCOMMAND \
	79	"fsload; bootm $(fileaddr)"
	80
6ccec449	81
9a24f477	82	/*
8b6684a6 HS	83	* After booting the board for the first time, new ethernet addresses
	84	* should be generated and assigned to the environment variables
	85	* "ethaddr" and "eth1addr". This is normally done during production.
9a24f477	86	*/
e3e8d463	87	#define CONFIG_OVERWRITE_ETHADDR_ONCE
9a24f477	88
2fd90ce5 JL	89	/*
	90	* BOOTP options
	91	*/
	92	#define CONFIG_BOOTP_SUBNETMASK
	93	#define CONFIG_BOOTP_GATEWAY
	94
5c98d7ff	95	/* generic board */
5c98d7ff	96	#define CONFIG_BOARD_EARLY_INIT_R
6ccec449	97
0b361c91 JL	98	/*
	99	* Command line configuration.
	100	*/
0b361c91	101	#define CONFIG_CMD_JFFS2
0b361c91	102
e3e8d463 AB	103	#define CONFIG_ATMEL_USART
	104	#define CONFIG_MACB
	105	#define CONFIG_PORTMUX_PIO
6d0f6bcf	106	#define CONFIG_SYS_NR_PIOS 5
e3e8d463	107	#define CONFIG_SYS_HSDRAMC
72fa4679 SS	108	#define CONFIG_GENERIC_ATMEL_MCI
72fa4679 SS	109	#define CONFIG_GENERIC_MMC
6ccec449	110
6d0f6bcf JCPV	111	#define CONFIG_SYS_DCACHE_LINESZ 32
6d0f6bcf JCPV	112	#define CONFIG_SYS_ICACHE_LINESZ 32
6ccec449 WD	113
	114	#define CONFIG_NR_DRAM_BANKS 1
	115
22178652 AB	116	#define CONFIG_SYS_FLASH_CFI
22178652 AB	117	#define CONFIG_FLASH_CFI_DRIVER
6ccec449	118
6d0f6bcf JCPV	119	#define CONFIG_SYS_FLASH_BASE 0x00000000
	120	#define CONFIG_SYS_FLASH_SIZE 0x800000
	121	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	122	#define CONFIG_SYS_MAX_FLASH_SECT 135
6ccec449	123
6d0f6bcf	124	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
47293c18	125	#define CONFIG_SYS_TEXT_BASE 0x00000000
6ccec449	126
6d0f6bcf JCPV	127	#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
	128	#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
	129	#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
6ccec449	130
e3e8d463	131	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586	132	#define CONFIG_ENV_SIZE 65536
6d0f6bcf	133	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
6ccec449	134
6d0f6bcf	135	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
6ccec449	136
6d0f6bcf	137	#define CONFIG_SYS_MALLOC_LEN (256*1024)
1f4f2121	138
8269ab53	139	/* Allow 4MB for the kernel run-time image */
6d0f6bcf JCPV	140	#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
6d0f6bcf JCPV	141	#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
6ccec449 WD	142
6ccec449 WD	143	/* Other configuration settings that shouldn't have to change all that often */
6d0f6bcf JCPV	144	#define CONFIG_SYS_CBSIZE 256
	145	#define CONFIG_SYS_MAXARGS 16
	146	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
e3e8d463	147	#define CONFIG_SYS_LONGHELP
6d0f6bcf JCPV	148
	149	#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
	150	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
	151	#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
6ccec449 WD	152
6ccec449 WD	153	#endif /* __CONFIG_H */