[people/ms/u-boot.git] / include / configs / balloon3.h

/*
 * Balloon3 configuration file
 *
 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef	__CONFIG_H
#define	__CONFIG_H

/*
 * High Level Board Configuration Options
 */
#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
#define	CONFIG_BALLOON3		1	/* Balloon3 board */

/*
 * Environment settings
 */
#define	CONFIG_ENV_OVERWRITE
#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
#define	CONFIG_ARCH_CPU_INIT
#define	CONFIG_BOOTCOMMAND						\
	"fpga load 0x0 0x50000 0x62638; "				\
	"if usb reset && fatload usb 0 0xa4000000 uImage; then "	\
		"bootm 0xa4000000; "					\
	"fi; "								\
	"bootm 0xd0000;"
#define	CONFIG_BOOTARGS			"console=tty0 console=ttyS2,115200"
#define	CONFIG_TIMESTAMP
#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
#define	CONFIG_CMDLINE_TAG
#define	CONFIG_SETUP_MEMORY_TAGS
#define	CONFIG_SYS_TEXT_BASE		0x0
#define	CONFIG_LZMA			/* LZMA compression support */

/*
 * Serial Console Configuration
 */
#define	CONFIG_PXA_SERIAL
#define	CONFIG_STUART			1
#define CONFIG_CONS_INDEX		2
#define	CONFIG_BAUDRATE			115200

/*
 * Bootloader Components Configuration
 */
#include <config_cmd_default.h>

#undef	CONFIG_CMD_NET
#undef	CONFIG_CMD_NFS
#undef	CONFIG_CMD_ENV
#undef	CONFIG_CMD_IMLS
#define	CONFIG_CMD_USB
#define	CONFIG_CMD_FPGA
#undef	CONFIG_LCD

/*
 * KGDB
 */
#ifdef	CONFIG_CMD_KGDB
#define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
#define	CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
#endif

/*
 * HUSH Shell Configuration
 */
#define	CONFIG_SYS_HUSH_PARSER		1

#define	CONFIG_SYS_LONGHELP
#ifdef	CONFIG_SYS_HUSH_PARSER
#define	CONFIG_SYS_PROMPT		"$ "
#else
#define	CONFIG_SYS_PROMPT		"=> "
#endif
#define	CONFIG_SYS_CBSIZE		256
#define	CONFIG_SYS_PBSIZE		\
	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define	CONFIG_SYS_MAXARGS		16
#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define	CONFIG_SYS_DEVICE_NULLDEV	1

/*
 * Clock Configuration
 */
#undef	CONFIG_SYS_CLKS_IN_HZ
#define	CONFIG_SYS_HZ			3250000		/* Timer @ 3250000 Hz */
#define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */

/*
 * DRAM Map
 */
#define	CONFIG_NR_DRAM_BANKS		3		/* 2 banks of DRAM */
#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
#define	PHYS_SDRAM_1_SIZE		0x08000000	/* 128 MB */
#define	PHYS_SDRAM_2			0xb0000000	/* SDRAM Bank #2 */
#define	PHYS_SDRAM_2_SIZE		0x08000000	/* 128 MB */
#define	PHYS_SDRAM_3			0x80000000	/* SDRAM Bank #2 */
#define	PHYS_SDRAM_3_SIZE		0x08000000	/* 128 MB */

#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
#define	CONFIG_SYS_DRAM_SIZE		0x18000000	/* 384 MB DRAM */

#define	CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
#define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */

#define	CONFIG_SYS_LOAD_ADDR		0xa1000000

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		\
	(PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)

/*
 * NOR FLASH
 */
#ifdef	CONFIG_CMD_FLASH
#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
#define	PHYS_FLASH_SIZE			0x00800000	/* 8 MB */
#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

#define	CONFIG_SYS_FLASH_CFI
#define	CONFIG_FLASH_CFI_DRIVER		1
#define	CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT

#define	CONFIG_SYS_MAX_FLASH_BANKS	1
#define	CONFIG_SYS_MAX_FLASH_SECT	256

#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1

#define	CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_LOCK_TOUT	(2*CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	(2*CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_PROTECTION
#define	CONFIG_ENV_IS_IN_FLASH
#else
#define	CONFIG_SYS_NO_FLASH
#define	CONFIG_SYS_ENV_IS_NOWHERE
#endif

#define	CONFIG_SYS_MONITOR_BASE		0x000000
#define	CONFIG_SYS_MONITOR_LEN		0x40000

#define	CONFIG_ENV_SIZE			0x2000
#define	CONFIG_ENV_ADDR			0x40000
#define	CONFIG_ENV_SECT_SIZE		0x10000

/*
 * GPIO settings
 */
#define	CONFIG_SYS_GPSR0_VAL	0x307dc7fd
#define	CONFIG_SYS_GPSR1_VAL	0x03cffa4e
#define	CONFIG_SYS_GPSR2_VAL	0x7131c000
#define	CONFIG_SYS_GPSR3_VAL	0x01e1f3ff

#define	CONFIG_SYS_GPCR0_VAL	0x0
#define	CONFIG_SYS_GPCR1_VAL	0x0
#define	CONFIG_SYS_GPCR2_VAL	0x0
#define	CONFIG_SYS_GPCR3_VAL	0x0

#define	CONFIG_SYS_GPDR0_VAL	0xc0f98e02
#define	CONFIG_SYS_GPDR1_VAL	0xfcffa8b7
#define	CONFIG_SYS_GPDR2_VAL	0x22e3ffff
#define	CONFIG_SYS_GPDR3_VAL	0x000201fe

#define	CONFIG_SYS_GAFR0_L_VAL	0x96c00000
#define	CONFIG_SYS_GAFR0_U_VAL	0xa5e5459b
#define	CONFIG_SYS_GAFR1_L_VAL	0x699b759a
#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa5a5aa
#define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
#define	CONFIG_SYS_GAFR2_U_VAL	0x01f9a6aa
#define	CONFIG_SYS_GAFR3_L_VAL	0x54510003
#define	CONFIG_SYS_GAFR3_U_VAL	0x00001599

#define	CONFIG_SYS_PSSR_VAL	0x30

/*
 * Clock settings
 */
#define	CONFIG_SYS_CKEN		0xffffffff
#define	CONFIG_SYS_CCCR		0x00000290

/*
 * Memory settings
 */
#define	CONFIG_SYS_MSC0_VAL	0x7ff07ff8
#define	CONFIG_SYS_MSC1_VAL	0x7ff07ff0
#define	CONFIG_SYS_MSC2_VAL	0x74a42491
#define	CONFIG_SYS_MDCNFG_VAL	0x89d309d3
#define	CONFIG_SYS_MDREFR_VAL	0x001d8018
#define	CONFIG_SYS_MDMRS_VAL	0x00220022
#define	CONFIG_SYS_FLYCNFG_VAL	0x00000000
#define	CONFIG_SYS_SXCNFG_VAL	0x00000000
#define	CONFIG_SYS_MEM_BUF_IMP	0x0f

/*
 * PCMCIA and CF Interfaces
 */
#define	CONFIG_SYS_MECR_VAL	0x00000000
#define	CONFIG_SYS_MCMEM0_VAL	0x00014307
#define	CONFIG_SYS_MCMEM1_VAL	0x00014307
#define	CONFIG_SYS_MCATT0_VAL	0x0001c787
#define	CONFIG_SYS_MCATT1_VAL	0x0001c787
#define	CONFIG_SYS_MCIO0_VAL	0x0001430f
#define	CONFIG_SYS_MCIO1_VAL	0x0001430f

/*
 * LCD
 */
#ifdef	CONFIG_LCD
#define	CONFIG_BALLOON3LCD
#define	CONFIG_VIDEO_LOGO
#define	CONFIG_CMD_BMP
#define	CONFIG_SPLASH_SCREEN
#define	CONFIG_SPLASH_SCREEN_ALIGN
#define	CONFIG_VIDEO_BMP_GZIP
#define	CONFIG_VIDEO_BMP_RLE8
#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
#endif

/*
 * USB
 */
#ifdef	CONFIG_CMD_USB
#define	CONFIG_USB_OHCI_NEW
#define	CONFIG_SYS_USB_OHCI_CPU_INIT
#define	CONFIG_SYS_USB_OHCI_BOARD_INIT
#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define	CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
#define	CONFIG_SYS_USB_OHCI_SLOT_NAME	"balloon3"
#define	CONFIG_USB_STORAGE
#define	CONFIG_DOS_PARTITION
#define	CONFIG_CMD_FAT
#define	CONFIG_CMD_EXT2
#endif

/*
 * FPGA
 */
#ifdef	CONFIG_CMD_FPGA
#define	CONFIG_FPGA
#define	CONFIG_FPGA_XILINX
#define	CONFIG_FPGA_SPARTAN3
#define	CONFIG_SYS_FPGA_PROG_FEEDBACK
#define	CONFIG_SYS_FPGA_WAIT	1000
#define	CONFIG_MAX_FPGA_DEVICES	1
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
10da95a1 MV	1	/*
	2	* Balloon3 configuration file
	3	*
	4	* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
10da95a1 MV	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Board Configuration Options
	14	*/
abc20aba	15	#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
10da95a1 MV	16	#define CONFIG_BALLOON3 1 /* Balloon3 board */
	17
	18	/*
	19	* Environment settings
	20	*/
	21	#define CONFIG_ENV_OVERWRITE
	22	#define CONFIG_SYS_MALLOC_LEN (128*1024)
20ae5193	23	#define CONFIG_ARCH_CPU_INIT
10da95a1	24	#define CONFIG_BOOTCOMMAND \
20ae5193	25	"fpga load 0x0 0x50000 0x62638; " \
10da95a1 MV	26	"if usb reset && fatload usb 0 0xa4000000 uImage; then " \
	27	"bootm 0xa4000000; " \
	28	"fi; " \
20ae5193	29	"bootm 0xd0000;"
10da95a1 MV	30	#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200"
	31	#define CONFIG_TIMESTAMP
	32	#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
	33	#define CONFIG_CMDLINE_TAG
	34	#define CONFIG_SETUP_MEMORY_TAGS
20ae5193	35	#define CONFIG_SYS_TEXT_BASE 0x0
10da95a1 MV	36	#define CONFIG_LZMA /* LZMA compression support */
	37
	38	/*
	39	* Serial Console Configuration
	40	*/
	41	#define CONFIG_PXA_SERIAL
	42	#define CONFIG_STUART 1
ce6971cd	43	#define CONFIG_CONS_INDEX 2
10da95a1	44	#define CONFIG_BAUDRATE 115200
10da95a1 MV	45
	46	/*
	47	* Bootloader Components Configuration
	48	*/
	49	#include <config_cmd_default.h>
	50
	51	#undef CONFIG_CMD_NET
6d8962e8	52	#undef CONFIG_CMD_NFS
10da95a1 MV	53	#undef CONFIG_CMD_ENV
	54	#undef CONFIG_CMD_IMLS
	55	#define CONFIG_CMD_USB
	56	#define CONFIG_CMD_FPGA
	57	#undef CONFIG_LCD
	58
	59	/*
	60	* KGDB
	61	*/
	62	#ifdef CONFIG_CMD_KGDB
	63	#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
	64	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	65	#endif
	66
	67	/*
	68	* HUSH Shell Configuration
	69	*/
	70	#define CONFIG_SYS_HUSH_PARSER 1
10da95a1 MV	71
	72	#define CONFIG_SYS_LONGHELP
	73	#ifdef CONFIG_SYS_HUSH_PARSER
	74	#define CONFIG_SYS_PROMPT "$ "
	75	#else
	76	#define CONFIG_SYS_PROMPT "=> "
	77	#endif
	78	#define CONFIG_SYS_CBSIZE 256
	79	#define CONFIG_SYS_PBSIZE \
	80	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	81	#define CONFIG_SYS_MAXARGS 16
	82	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	83	#define CONFIG_SYS_DEVICE_NULLDEV 1
	84
	85	/*
	86	* Clock Configuration
	87	*/
	88	#undef CONFIG_SYS_CLKS_IN_HZ
	89	#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
	90	#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
	91
10da95a1 MV	92	/*
	93	* DRAM Map
	94	*/
	95	#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */
	96	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	97	#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
	98	#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
	99	#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
	100	#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */
	101	#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
	102
	103	#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
	104	#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */
	105
	106	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
	107	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	108
	109	#define CONFIG_SYS_LOAD_ADDR 0xa1000000
	110
6ef6eb91	111	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
20ae5193	112	#define CONFIG_SYS_INIT_SP_ADDR \
25ddd1fb	113	(PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
6ef6eb91	114
10da95a1 MV	115	/*
	116	* NOR FLASH
	117	*/
	118	#ifdef CONFIG_CMD_FLASH
	119	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	120	#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
	121	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	122
	123	#define CONFIG_SYS_FLASH_CFI
	124	#define CONFIG_FLASH_CFI_DRIVER 1
	125	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	126
	127	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	128	#define CONFIG_SYS_MAX_FLASH_SECT 256
	129
	130	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	131
	132	#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
	133	#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
	134	#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
	135	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
	136	#define CONFIG_SYS_FLASH_PROTECTION
	137	#define CONFIG_ENV_IS_IN_FLASH
	138	#else
	139	#define CONFIG_SYS_NO_FLASH
	140	#define CONFIG_SYS_ENV_IS_NOWHERE
	141	#endif
	142
	143	#define CONFIG_SYS_MONITOR_BASE 0x000000
	144	#define CONFIG_SYS_MONITOR_LEN 0x40000
	145
	146	#define CONFIG_ENV_SIZE 0x2000
	147	#define CONFIG_ENV_ADDR 0x40000
	148	#define CONFIG_ENV_SECT_SIZE 0x10000
	149
	150	/*
	151	* GPIO settings
	152	*/
	153	#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd
	154	#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e
	155	#define CONFIG_SYS_GPSR2_VAL 0x7131c000
	156	#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff
	157
	158	#define CONFIG_SYS_GPCR0_VAL 0x0
	159	#define CONFIG_SYS_GPCR1_VAL 0x0
	160	#define CONFIG_SYS_GPCR2_VAL 0x0
	161	#define CONFIG_SYS_GPCR3_VAL 0x0
	162
	163	#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02
	164	#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7
	165	#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff
	166	#define CONFIG_SYS_GPDR3_VAL 0x000201fe
	167
	168	#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000
	169	#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b
	170	#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a
	171	#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa
	172	#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
	173	#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa
	174	#define CONFIG_SYS_GAFR3_L_VAL 0x54510003
	175	#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
	176
	177	#define CONFIG_SYS_PSSR_VAL 0x30
	178
179	/*
180	* Clock settings
181	*/
182	#define CONFIG_SYS_CKEN 0xffffffff
183	#define CONFIG_SYS_CCCR 0x00000290
184
185	/*
186	* Memory settings
187	*/
188	#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8
189	#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
190	#define CONFIG_SYS_MSC2_VAL 0x74a42491
191	#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3
192	#define CONFIG_SYS_MDREFR_VAL 0x001d8018
193	#define CONFIG_SYS_MDMRS_VAL 0x00220022
194	#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
195	#define CONFIG_SYS_SXCNFG_VAL 0x00000000
196	#define CONFIG_SYS_MEM_BUF_IMP 0x0f
197
198	/*
199	* PCMCIA and CF Interfaces
200	*/
201	#define CONFIG_SYS_MECR_VAL 0x00000000
202	#define CONFIG_SYS_MCMEM0_VAL 0x00014307
203	#define CONFIG_SYS_MCMEM1_VAL 0x00014307
204	#define CONFIG_SYS_MCATT0_VAL 0x0001c787
205	#define CONFIG_SYS_MCATT1_VAL 0x0001c787
206	#define CONFIG_SYS_MCIO0_VAL 0x0001430f
207	#define CONFIG_SYS_MCIO1_VAL 0x0001430f
208
209	/*
210	* LCD
211	*/
212	#ifdef CONFIG_LCD
213	#define CONFIG_BALLOON3LCD
214	#define CONFIG_VIDEO_LOGO
215	#define CONFIG_CMD_BMP
216	#define CONFIG_SPLASH_SCREEN
217	#define CONFIG_SPLASH_SCREEN_ALIGN
218	#define CONFIG_VIDEO_BMP_GZIP
219	#define CONFIG_VIDEO_BMP_RLE8
220	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
221	#endif
222
223	/*
224	* USB
225	*/
226	#ifdef CONFIG_CMD_USB
227	#define CONFIG_USB_OHCI_NEW
228	#define CONFIG_SYS_USB_OHCI_CPU_INIT
229	#define CONFIG_SYS_USB_OHCI_BOARD_INIT
230	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
231	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
232	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3"
233	#define CONFIG_USB_STORAGE
234	#define CONFIG_DOS_PARTITION
235	#define CONFIG_CMD_FAT
236	#define CONFIG_CMD_EXT2
237	#endif
238
239	/*
240	* FPGA
241	*/
242	#ifdef CONFIG_CMD_FPGA
243	#define CONFIG_FPGA
244	#define CONFIG_FPGA_XILINX
245	#define CONFIG_FPGA_SPARTAN3
246	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
247	#define CONFIG_SYS_FPGA_WAIT 1000
248	#define CONFIG_MAX_FPGA_DEVICES 1
249	#endif
250
251	#endif /* __CONFIG_H */