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Commit | Line | Data |
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06399329 PM |
1 | /* |
2 | * U-boot - Configuration file for BF536 brettl2 board | |
3 | */ | |
4 | ||
5 | #ifndef __CONFIG_BCT_BRETTL2_H__ | |
6 | #define __CONFIG_BCT_BRETTL2_H__ | |
7 | ||
8 | #include <asm/config-pre.h> | |
9 | ||
10 | ||
11 | /* | |
12 | * Processor Settings | |
13 | */ | |
071bc923 | 14 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
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15 | |
16 | ||
17 | /* | |
18 | * Clock Settings | |
19 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
20 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
21 | */ | |
22 | /* CONFIG_CLKIN_HZ is any value in Hz */ | |
23 | #define CONFIG_CLKIN_HZ 16384000 | |
071bc923 WD |
24 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
25 | /* 1 = CLKIN / 2 */ | |
06399329 PM |
26 | #define CONFIG_CLKIN_HALF 0 |
27 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
071bc923 | 28 | /* 1 = bypass PLL */ |
06399329 PM |
29 | #define CONFIG_PLL_BYPASS 0 |
30 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
31 | /* Values can range from 0-63 (where 0 means 64) */ | |
32 | #define CONFIG_VCO_MULT 24 | |
33 | /* CCLK_DIV controls the core clock divider */ | |
34 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
35 | #define CONFIG_CCLK_DIV 1 | |
36 | /* SCLK_DIV controls the system clock divider */ | |
37 | /* Values can range from 1-15 */ | |
38 | #define CONFIG_SCLK_DIV 3 | |
071bc923 | 39 | #define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) |
06399329 PM |
40 | |
41 | ||
42 | /* | |
43 | * Memory Settings | |
44 | */ | |
45 | #define CONFIG_MEM_ADD_WDTH 9 | |
46 | #define CONFIG_MEM_SIZE 32 | |
47 | ||
48 | ||
49 | /* | |
50 | * SDRAM Settings | |
51 | */ | |
52 | #define CONFIG_EBIU_SDRRC_VAL 0x07f6 | |
53 | #define CONFIG_EBIU_SDGCTL_VAL 0x9111cd | |
54 | ||
55 | #define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) | |
56 | #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) | |
57 | #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) | |
58 | ||
59 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
60 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) | |
61 | ||
62 | ||
63 | /* | |
64 | * Network Settings | |
65 | */ | |
66 | #ifndef __ADSPBF534__ | |
67 | #define ADI_CMDS_NETWORK 1 | |
68 | #define CONFIG_BFIN_MAC 1 | |
69 | #define CONFIG_NETCONSOLE 1 | |
70 | #define CONFIG_NET_MULTI 1 | |
71 | #define CONFIG_HOSTNAME brettl2 | |
72 | #define CONFIG_IPADDR 192.168.233.224 | |
73 | #define CONFIG_GATEWAYIP 192.168.233.1 | |
74 | #define CONFIG_SERVERIP 192.168.233.53 | |
75 | #define CONFIG_ROOTPATH /romfs/brettl2 | |
76 | /* Uncomment next line to use fixed MAC address */ | |
77 | /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ | |
78 | #endif | |
79 | ||
80 | ||
81 | /* | |
82 | * Flash Settings | |
83 | */ | |
84 | #define CONFIG_FLASH_CFI_DRIVER | |
85 | #define CONFIG_SYS_FLASH_CFI | |
86 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
87 | #define CONFIG_SYS_FLASH_PROTECTION | |
88 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
89 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
90 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
91 | ||
92 | ||
93 | /* | |
94 | * Env Storage Settings | |
95 | */ | |
96 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
97 | #define CONFIG_ENV_OFFSET 0x4000 | |
98 | #define CONFIG_ENV_SIZE 0x2000 | |
99 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
100 | ||
101 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) | |
102 | #define ENV_IS_EMBEDDED | |
103 | #else | |
104 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR | |
105 | #endif | |
106 | ||
107 | #ifdef ENV_IS_EMBEDDED | |
108 | /* WARNING - the following is hand-optimized to fit within | |
109 | * the sector before the environment sector. If it throws | |
110 | * an error during compilation remove an object here to get | |
111 | * it linked after the configuration sector. | |
112 | */ | |
113 | # define LDS_BOARD_TEXT \ | |
071bc923 WD |
114 | arch/blackfin/cpu/traps.o (.text .text.*); \ |
115 | arch/blackfin/cpu/interrupt.o (.text .text.*); \ | |
116 | arch/blackfin/cpu/serial.o (.text .text.*); \ | |
117 | common/dlmalloc.o (.text .text.*); \ | |
118 | lib/crc32.o (.text .text.*); \ | |
119 | . = DEFINED(env_offset) ? env_offset : .; \ | |
120 | common/env_embedded.o (.text .text.*); | |
06399329 PM |
121 | #endif |
122 | ||
123 | ||
124 | /* | |
125 | * I2C Settings | |
126 | */ | |
127 | #define CONFIG_BFIN_TWI_I2C 1 | |
128 | #define CONFIG_HARD_I2C 1 | |
129 | ||
130 | ||
131 | /* | |
132 | * Misc Settings | |
133 | */ | |
134 | #define CONFIG_BOOTDELAY 1 | |
135 | #define CONFIG_LOADADDR 0x800000 | |
136 | #define CONFIG_MISC_INIT_R | |
137 | #define CONFIG_UART_CONSOLE 0 | |
138 | #define CONFIG_BAUDRATE 115200 | |
139 | #define CONFIG_MTD_DEVICE | |
140 | #define CONFIG_MTD_PARTITIONS | |
141 | #define CONFIG_SYS_HUSH_PARSER | |
142 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
143 | ||
144 | ||
145 | /* | |
146 | * Pull in common ADI header for remaining command/environment setup | |
147 | */ | |
148 | #include <configs/bfin_adi_common.h> | |
149 | ||
150 | /* disable unnecessary features */ | |
151 | #undef CONFIG_BOOTM_RTEMS | |
152 | #undef CONFIG_BZIP2 | |
153 | #undef CONFIG_KALLSYMS | |
154 | ||
155 | #endif |