[people/ms/u-boot.git] / include / configs / bf533-ezkit.h

/*
 * U-boot - Configuration file for BF533 EZKIT board
 */

#ifndef __CONFIG_EZKIT533_H__
#define __CONFIG_EZKIT533_H__

#include <asm/blackfin-config-pre.h>

#define CONFIG_BAUDRATE		57600

#define CONFIG_BOOTDELAY	5
#define CONFIG_SYS_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */

#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_LOADADDR		0x01000000	/* default load address */
#define CONFIG_BOOTCOMMAND	"tftp $(loadaddr) linux"
/* #define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw" */

#define CONFIG_DRIVER_SMC91111	1
#define CONFIG_SMC91111_BASE	0x20310300

#if 0
#define	CONFIG_MII
#define CONFIG_SYS_DISCOVER_PHY
#endif

#define CONFIG_RTC_BFIN		1
#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */

#define CONFIG_PANIC_HANG 1

#define CONFIG_BFIN_CPU	bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS

/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON

/* CONFIG_CLKIN_HZ is any value in Hz				*/
#define CONFIG_CLKIN_HZ		27000000
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
/*						    1=CLKIN/2	*/
#define CONFIG_CLKIN_HALF	0
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
/*						 1=bypass PLL	*/
#define CONFIG_PLL_BYPASS	0
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
/* Values can range from 1-64					*/
#define CONFIG_VCO_MULT		22
/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
/* Values can be 1, 2, 4, or 8 ONLY				*/
#define CONFIG_CCLK_DIV		1
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
/* Values can range from 1-15					*/
#define CONFIG_SCLK_DIV		5
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
/* Values can range from 2-65535				*/
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
#define CONFIG_SPI_BAUD		2
#define CONFIG_SPI_BAUD_INITBLOCK	4

#if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#else
#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
#endif

#if (CONFIG_PLL_BYPASS == 0)
#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
#else
#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
#endif

#define CONFIG_MEM_SIZE		32	/* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH	9	/* 8, 9, 10, 11    */
#define CONFIG_MEM_MT48LC16M16A2TG_75	1

#define CONFIG_LOADS_ECHO	1


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_DATE


#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"

#define	CONFIG_SYS_PROMPT		"bfin> "	/* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024 * 1024)	/* 1 ... 31 MB in DRAM */
#define	CONFIG_SYS_LOAD_ADDR		0x01000000	/* default load address */
#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 10 ms ticks */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 * 1024)
#define CONFIG_SYS_FLASH_BASE		0x20000000

#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_GBL_DATA_SIZE	0x4000
#define CONFIG_SYS_GBL_DATA_ADDR	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_STACKBASE	(CONFIG_SYS_GBL_DATA_ADDR  - 4)

#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
#define CONFIG_SYS_FLASH0_BASE		0x20000000
#define CONFIG_SYS_FLASH1_BASE		0x20200000
#define CONFIG_SYS_FLASH2_BASE		0x20280000
#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	40	/* max number of sectors on one chip */

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0x20020000
#define	CONFIG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */

/* JFFS Partition offset set  */
#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	1
/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11


/*
 * Stack sizes
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */

#define POLL_MODE		1
#define FLASH_TOT_SECT		40
#define FLASH_SIZE		0x220000
#define CONFIG_SYS_FLASH_SIZE		0x220000

/*
 * Initialize PSD4256 registers for using I2C
 */
#define	CONFIG_MISC_INIT_R

/*
 * I2C settings
 * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
 */
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged */
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PF_SCL			PF0
#define PF_SDA			PF1

#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
#define I2C_SDA(bit)	if(bit) { \
				*pFIO_FLAG_S = PF_SDA; \
				asm("ssync;"); \
				} \
			else    { \
				*pFIO_FLAG_C = PF_SDA; \
				asm("ssync;"); \
				}
#define I2C_SCL(bit)	if(bit) { \
				*pFIO_FLAG_S = PF_SCL; \
				asm("ssync;"); \
				} \
			else    { \
				*pFIO_FLAG_C = PF_SCL; \
				asm("ssync;"); \
				}
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

#define CONFIG_SYS_I2C_SPEED		50000
#define CONFIG_SYS_I2C_SLAVE		0xFE

#define CONFIG_SYS_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */

#define CONFIG_EBIU_SDRRC_VAL  0x398
#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
#define CONFIG_EBIU_SDBCTL_VAL 0x13

#define CONFIG_EBIU_AMGCTL_VAL		0xFF
#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0

#include <asm/blackfin-config-post.h>

#endif
Commit	Line	Data
3f0606ad AL	1	/*
	2	* U-boot - Configuration file for BF533 EZKIT board
	3	*/
	4
	5	#ifndef __CONFIG_EZKIT533_H__
	6	#define __CONFIG_EZKIT533_H__
	7
f7ce12cb MF	8	#include <asm/blackfin-config-pre.h>
f7ce12cb MF	9
3f0606ad	10	#define CONFIG_BAUDRATE 57600
3f0606ad AL	11
3f0606ad AL	12	#define CONFIG_BOOTDELAY 5
6d0f6bcf	13	#define CONFIG_SYS_AUTOLOAD "no" /rarpb, bootp or dhcp commands will perform only a /
3f0606ad	14
6d0f6bcf	15	#define CONFIG_SYS_LONGHELP 1
3f0606ad	16	#define CONFIG_CMDLINE_EDITING 1
8db13d63	17	#define CONFIG_LOADADDR 0x01000000 /* default load address */
3f0606ad	18	#define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux"
8db13d63	19	/* #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" */
3f0606ad AL	20
	21	#define CONFIG_DRIVER_SMC91111 1
	22	#define CONFIG_SMC91111_BASE 0x20310300
	23
	24	#if 0
	25	#define CONFIG_MII
6d0f6bcf	26	#define CONFIG_SYS_DISCOVER_PHY
3f0606ad AL	27	#endif
	28
	29	#define CONFIG_RTC_BFIN 1
	30	#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
	31
3f0606ad AL	32	#define CONFIG_PANIC_HANG 1
3f0606ad AL	33
f7ce12cb	34	#define CONFIG_BFIN_CPU bf533-0.3
9171fc81	35	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
3f0606ad AL	36
	37	/* This sets the default state of the cache on U-Boot's boot */
	38	#define CONFIG_ICACHE_ON
	39	#define CONFIG_DCACHE_ON
	40
8db13d63 AL	41	/* CONFIG_CLKIN_HZ is any value in Hz */
	42	#define CONFIG_CLKIN_HZ 27000000
	43	/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
	44	/* 1=CLKIN/2 */
	45	#define CONFIG_CLKIN_HALF 0
	46	/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
	47	/* 1=bypass PLL */
	48	#define CONFIG_PLL_BYPASS 0
	49	/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
	50	/* Values can range from 1-64 */
	51	#define CONFIG_VCO_MULT 22
	52	/* CONFIG_CCLK_DIV controls what the core clock divider is */
	53	/* Values can be 1, 2, 4, or 8 ONLY */
	54	#define CONFIG_CCLK_DIV 1
3f0606ad	55	/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
8db13d63 AL	56	/* Values can range from 1-15 */
	57	#define CONFIG_SCLK_DIV 5
	58	/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
	59	/* Values can range from 2-65535 */
	60	/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
	61	#define CONFIG_SPI_BAUD 2
	62	#define CONFIG_SPI_BAUD_INITBLOCK 4
3f0606ad AL	63
3f0606ad AL	64	#if ( CONFIG_CLKIN_HALF == 0 )
8db13d63	65	#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
3f0606ad	66	#else
8db13d63	67	#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
3f0606ad AL	68	#endif
	69
	70	#if (CONFIG_PLL_BYPASS == 0)
8db13d63 AL	71	#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
8db13d63 AL	72	#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
3f0606ad	73	#else
8db13d63 AL	74	#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
8db13d63 AL	75	#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
3f0606ad AL	76	#endif
3f0606ad AL	77
8440bb14	78	#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
8db13d63 AL	79	#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
8db13d63 AL	80	#define CONFIG_MEM_MT48LC16M16A2TG_75 1
3f0606ad AL	81
	82	#define CONFIG_LOADS_ECHO 1
	83
	84
079a136c JL	85	/*
	86	* BOOTP options
	87	*/
	88	#define CONFIG_BOOTP_BOOTFILESIZE
	89	#define CONFIG_BOOTP_BOOTPATH
	90	#define CONFIG_BOOTP_GATEWAY
	91	#define CONFIG_BOOTP_HOSTNAME
	92
	93
ba2351f9 JL	94	/*
	95	* Command line configuration.
	96	*/
	97	#include <config_cmd_default.h>
3f0606ad	98
ba2351f9 JL	99	#define CONFIG_CMD_PING
	100	#define CONFIG_CMD_ELF
	101	#define CONFIG_CMD_I2C
	102	#define CONFIG_CMD_JFFS2
	103	#define CONFIG_CMD_DATE
	104
	105
	106	#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
3f0606ad	107
6d0f6bcf	108	#define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */
ba2351f9	109	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	110	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
3f0606ad	111	#else
6d0f6bcf	112	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
3f0606ad	113	#endif
6d0f6bcf JCPV	114	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	115	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	116	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	117	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
	118	#define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024) /* 1 ... 31 MB in DRAM */
	119	#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */
	120	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
	121	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	122	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	123	#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
	124	#define CONFIG_SYS_FLASH_BASE 0x20000000
	125
	126	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	127	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
	128	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	129	#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
	130	#define CONFIG_SYS_GBL_DATA_SIZE 0x4000
	131	#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
	132	#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
	133
	134	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	135	#define CONFIG_SYS_FLASH0_BASE 0x20000000
	136	#define CONFIG_SYS_FLASH1_BASE 0x20200000
	137	#define CONFIG_SYS_FLASH2_BASE 0x20280000
	138	#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
	139	#define CONFIG_SYS_MAX_FLASH_SECT 40 /* max number of sectors on one chip */
3f0606ad	140
5a1aceb0	141	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	142	#define CONFIG_ENV_ADDR 0x20020000
0e8d1586 JCPV	143	#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
3f0606ad AL	144
3f0606ad AL	145	/* JFFS Partition offset set */
6d0f6bcf JCPV	146	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
6d0f6bcf JCPV	147	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
3f0606ad	148	/* 512k reserved for u-boot */
6d0f6bcf	149	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
3f0606ad AL	150
	151
	152	/*
	153	* Stack sizes
	154	*/
8db13d63	155	#define CONFIG_STACKSIZE (1281024) / regular stack */
3f0606ad AL	156
	157	#define POLL_MODE 1
	158	#define FLASH_TOT_SECT 40
	159	#define FLASH_SIZE 0x220000
6d0f6bcf	160	#define CONFIG_SYS_FLASH_SIZE 0x220000
3f0606ad AL	161
	162	/*
	163	* Initialize PSD4256 registers for using I2C
	164	*/
	165	#define CONFIG_MISC_INIT_R
	166
	167	/*
	168	* I2C settings
	169	* By default PF1 is used as SDA and PF0 as SCL on the Stamp board
	170	*/
8db13d63	171	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
3f0606ad AL	172	/*
	173	* Software (bit-bang) I2C driver configuration
	174	*/
8db13d63 AL	175	#define PF_SCL PF0
	176	#define PF_SDA PF1
	177
	178	#define I2C_INIT (*pFIO_DIR \|= PF_SCL); asm("ssync;")
	179	#define I2C_ACTIVE (pFIO_DIR \|= PF_SDA); pFIO_INEN &= ~PF_SDA; asm("ssync;")
	180	#define I2C_TRISTATE (pFIO_DIR &= ~PF_SDA); pFIO_INEN \|= PF_SDA; asm("ssync;")
	181	#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
	182	#define I2C_SDA(bit) if(bit) { \
	183	*pFIO_FLAG_S = PF_SDA; \
	184	asm("ssync;"); \
	185	} \
	186	else { \
	187	*pFIO_FLAG_C = PF_SDA; \
	188	asm("ssync;"); \
	189	}
	190	#define I2C_SCL(bit) if(bit) { \
	191	*pFIO_FLAG_S = PF_SCL; \
	192	asm("ssync;"); \
	193	} \
	194	else { \
	195	*pFIO_FLAG_C = PF_SCL; \
	196	asm("ssync;"); \
	197	}
	198	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	199
6d0f6bcf JCPV	200	#define CONFIG_SYS_I2C_SPEED 50000
6d0f6bcf JCPV	201	#define CONFIG_SYS_I2C_SLAVE 0xFE
3f0606ad	202
6d0f6bcf	203	#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
3f0606ad	204
9171fc81 MF	205	#define CONFIG_EBIU_SDRRC_VAL 0x398
	206	#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
	207	#define CONFIG_EBIU_SDBCTL_VAL 0x13
	208
	209	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	210	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	211	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	212
	213	#include <asm/blackfin-config-post.h>
3f0606ad AL	214
3f0606ad AL	215	#endif